radar_system_top_50t.v
1 `timescale 1ns / 1ps 2 3 /** 4 * radar_system_top_50t.v 5 * 6 * 50T Production Wrapper for radar_system_top 7 * 8 * The XC7A50T-FTG256 has only 69 usable IO pins, but radar_system_top 9 * declares many port bits (including FT601 USB 3.0, debug outputs, and 10 * status signals that have no physical connections on the 50T board). 11 * 12 * This wrapper exposes the physically-connected ports and ties off unused 13 * inputs. Unused outputs remain internally connected so the full radar 14 * pipeline is preserved in the netlist. 15 * 16 * USB: FT2232H (USB 2.0, 8-bit, 245 Synchronous FIFO mode) 17 * - USB_MODE=1 selects the FT2232H interface in radar_system_top 18 * - FT2232H CLKOUT (60 MHz) connected to ft601_clk_in (shared clock port) 19 * - 15 signals on Bank 35 (VCCO=3.3V, LVCMOS33) 20 */ 21 22 module radar_system_top_50t ( 23 // ===== System Clocks (Bank 15: 3.3V) ===== 24 input wire clk_100m, 25 input wire clk_120m_dac, 26 input wire reset_n, 27 28 // ===== DAC Interface (Bank 15: 3.3V) ===== 29 output wire [7:0] dac_data, 30 output wire dac_sleep, 31 32 // ===== RF Control (Bank 15: 3.3V) ===== 33 output wire fpga_rf_switch, 34 output wire rx_mixer_en, 35 output wire tx_mixer_en, 36 37 // ===== ADAR1000 Beamformer (Bank 34: 1.8V) ===== 38 output wire adar_tx_load_1, adar_rx_load_1, 39 output wire adar_tx_load_2, adar_rx_load_2, 40 output wire adar_tx_load_3, adar_rx_load_3, 41 output wire adar_tx_load_4, adar_rx_load_4, 42 output wire adar_tr_1, adar_tr_2, adar_tr_3, adar_tr_4, 43 44 // ===== STM32 SPI 3.3V side (Bank 15) ===== 45 input wire stm32_sclk_3v3, 46 input wire stm32_mosi_3v3, 47 output wire stm32_miso_3v3, 48 input wire stm32_cs_adar1_3v3, stm32_cs_adar2_3v3, 49 input wire stm32_cs_adar3_3v3, stm32_cs_adar4_3v3, 50 51 // ===== STM32 SPI 1.8V side (Bank 34) ===== 52 output wire stm32_sclk_1v8, 53 output wire stm32_mosi_1v8, 54 input wire stm32_miso_1v8, 55 output wire stm32_cs_adar1_1v8, stm32_cs_adar2_1v8, 56 output wire stm32_cs_adar3_1v8, stm32_cs_adar4_1v8, 57 58 // ===== ADC Interface (Bank 14: LVDS_25) ===== 59 input wire [7:0] adc_d_p, 60 input wire [7:0] adc_d_n, 61 input wire adc_dco_p, 62 input wire adc_dco_n, 63 output wire adc_pwdn, 64 65 // ===== STM32 Control (Bank 15: 3.3V) ===== 66 input wire stm32_new_chirp, 67 input wire stm32_new_elevation, 68 input wire stm32_new_azimuth, 69 input wire stm32_mixers_enable, 70 71 // ===== FT2232H USB 2.0 Interface (Bank 35: 3.3V) ===== 72 input wire ft_clkout, // 60 MHz from FT2232H CLKOUT (MRCC pin C4) 73 inout wire [7:0] ft_data, // 8-bit bidirectional data bus 74 input wire ft_rxf_n, // RX FIFO not empty (active low) 75 input wire ft_txe_n, // TX FIFO not full (active low) 76 output wire ft_rd_n, // Read strobe (active low) 77 output wire ft_wr_n, // Write strobe (active low) 78 output wire ft_oe_n, // Output enable / bus direction 79 output wire ft_siwu // Send Immediate / WakeUp 80 ); 81 82 // ===== Tie-off wires for unconstrained FT601 inputs (inactive with USB_MODE=1) ===== 83 wire ft601_txe_tied = 1'b0; 84 wire ft601_rxf_tied = 1'b0; 85 wire [1:0] ft601_srb_tied = 2'b00; 86 wire [1:0] ft601_swb_tied = 2'b00; 87 88 // ===== FT601 inout bus — tie to high-Z ===== 89 wire [31:0] ft601_data_internal; 90 assign ft601_data_internal = 32'hZZZZZZZZ; 91 92 // ===== Unconnected output wires (synthesis preserves driving logic) ===== 93 wire dac_clk_nc; 94 wire [3:0] ft601_be_nc; 95 wire ft601_txe_n_nc; 96 wire ft601_rxf_n_nc; 97 wire ft601_wr_n_nc; 98 wire ft601_rd_n_nc; 99 wire ft601_oe_n_nc; 100 wire ft601_siwu_n_nc; 101 wire ft601_clk_out_nc; 102 wire [5:0] current_elevation_nc; 103 wire [5:0] current_azimuth_nc; 104 wire [5:0] current_chirp_nc; 105 wire new_chirp_frame_nc; 106 wire [31:0] dbg_doppler_data_nc; 107 wire dbg_doppler_valid_nc; 108 wire [4:0] dbg_doppler_bin_nc; 109 wire [5:0] dbg_range_bin_nc; 110 wire [3:0] system_status_nc; 111 112 (* DONT_TOUCH = "TRUE" *) 113 radar_system_top #( 114 .USB_MODE(1) // FT2232H (8-bit USB 2.0) for 50T production 115 ) u_core ( 116 // ----- Clocks & Reset ----- 117 .clk_100m (clk_100m), 118 .clk_120m_dac (clk_120m_dac), 119 .ft601_clk_in (ft_clkout), // FT2232H 60 MHz CLKOUT → shared USB clock port 120 .reset_n (reset_n), 121 122 // ----- DAC ----- 123 .dac_data (dac_data), 124 .dac_clk (dac_clk_nc), 125 .dac_sleep (dac_sleep), 126 127 // ----- RF ----- 128 .fpga_rf_switch (fpga_rf_switch), 129 .rx_mixer_en (rx_mixer_en), 130 .tx_mixer_en (tx_mixer_en), 131 132 // ----- Beamformer ----- 133 .adar_tx_load_1 (adar_tx_load_1), 134 .adar_rx_load_1 (adar_rx_load_1), 135 .adar_tx_load_2 (adar_tx_load_2), 136 .adar_rx_load_2 (adar_rx_load_2), 137 .adar_tx_load_3 (adar_tx_load_3), 138 .adar_rx_load_3 (adar_rx_load_3), 139 .adar_tx_load_4 (adar_tx_load_4), 140 .adar_rx_load_4 (adar_rx_load_4), 141 .adar_tr_1 (adar_tr_1), 142 .adar_tr_2 (adar_tr_2), 143 .adar_tr_3 (adar_tr_3), 144 .adar_tr_4 (adar_tr_4), 145 146 // ----- SPI 3.3V ----- 147 .stm32_sclk_3v3 (stm32_sclk_3v3), 148 .stm32_mosi_3v3 (stm32_mosi_3v3), 149 .stm32_miso_3v3 (stm32_miso_3v3), 150 .stm32_cs_adar1_3v3 (stm32_cs_adar1_3v3), 151 .stm32_cs_adar2_3v3 (stm32_cs_adar2_3v3), 152 .stm32_cs_adar3_3v3 (stm32_cs_adar3_3v3), 153 .stm32_cs_adar4_3v3 (stm32_cs_adar4_3v3), 154 155 // ----- SPI 1.8V ----- 156 .stm32_sclk_1v8 (stm32_sclk_1v8), 157 .stm32_mosi_1v8 (stm32_mosi_1v8), 158 .stm32_miso_1v8 (stm32_miso_1v8), 159 .stm32_cs_adar1_1v8 (stm32_cs_adar1_1v8), 160 .stm32_cs_adar2_1v8 (stm32_cs_adar2_1v8), 161 .stm32_cs_adar3_1v8 (stm32_cs_adar3_1v8), 162 .stm32_cs_adar4_1v8 (stm32_cs_adar4_1v8), 163 164 // ----- ADC ----- 165 .adc_d_p (adc_d_p), 166 .adc_d_n (adc_d_n), 167 .adc_dco_p (adc_dco_p), 168 .adc_dco_n (adc_dco_n), 169 .adc_pwdn (adc_pwdn), 170 171 // ----- STM32 Control ----- 172 .stm32_new_chirp (stm32_new_chirp), 173 .stm32_new_elevation (stm32_new_elevation), 174 .stm32_new_azimuth (stm32_new_azimuth), 175 .stm32_mixers_enable (stm32_mixers_enable), 176 177 // ----- FT2232H USB 2.0 (active on 50T, USB_MODE=1) ----- 178 .ft_data (ft_data), 179 .ft_rxf_n (ft_rxf_n), 180 .ft_txe_n (ft_txe_n), 181 .ft_rd_n (ft_rd_n), 182 .ft_wr_n (ft_wr_n), 183 .ft_oe_n (ft_oe_n), 184 .ft_siwu (ft_siwu), 185 186 // ----- FT601 (inactive with USB_MODE=1 — generate block ties off) ----- 187 .ft601_data (ft601_data_internal), 188 .ft601_be (ft601_be_nc), 189 .ft601_txe_n (ft601_txe_n_nc), 190 .ft601_rxf_n (ft601_rxf_n_nc), 191 .ft601_txe (ft601_txe_tied), 192 .ft601_rxf (ft601_rxf_tied), 193 .ft601_wr_n (ft601_wr_n_nc), 194 .ft601_rd_n (ft601_rd_n_nc), 195 .ft601_oe_n (ft601_oe_n_nc), 196 .ft601_siwu_n (ft601_siwu_n_nc), 197 .ft601_srb (ft601_srb_tied), 198 .ft601_swb (ft601_swb_tied), 199 .ft601_clk_out (ft601_clk_out_nc), 200 201 // ----- Status/Debug (no pins on 50T) ----- 202 .current_elevation (current_elevation_nc), 203 .current_azimuth (current_azimuth_nc), 204 .current_chirp (current_chirp_nc), 205 .new_chirp_frame (new_chirp_frame_nc), 206 .dbg_doppler_data (dbg_doppler_data_nc), 207 .dbg_doppler_valid (dbg_doppler_valid_nc), 208 .dbg_doppler_bin (dbg_doppler_bin_nc), 209 .dbg_range_bin (dbg_range_bin_nc), 210 .system_status (system_status_nc) 211 ); 212 213 endmodule