1  `timescale 1ns / 1ps
 2  
 3  module radar_system_top_te0712_dev (
 4      input wire clk_100m,
 5      input wire reset_n,
 6      output wire [3:0] user_led,
 7      output wire [3:0] system_status
 8  );
 9  
10  wire clk_100m_buf;
11  wire sys_reset_n;
12  reg [31:0] hb_counter;
13  
14  BUFG bufg_100m (
15      .I(clk_100m),
16      .O(clk_100m_buf)
17  );
18  
19  (* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync;
20  always @(posedge clk_100m_buf or negedge reset_n) begin
21      if (!reset_n) begin
22          reset_sync <= 2'b00;
23      end else begin
24          reset_sync <= {reset_sync[0], 1'b1};
25      end
26  end
27  assign sys_reset_n = reset_sync[1];
28  
29  always @(posedge clk_100m_buf or negedge sys_reset_n) begin
30      if (!sys_reset_n) begin
31          hb_counter <= 32'd0;
32      end else begin
33          hb_counter <= hb_counter + 1'b1;
34      end
35  end
36  
37  assign user_led[0] = hb_counter[24];
38  assign user_led[1] = hb_counter[25];
39  assign user_led[2] = hb_counter[26];
40  assign user_led[3] = sys_reset_n;
41  
42  assign system_status[0] = sys_reset_n;
43  assign system_status[1] = hb_counter[23];
44  assign system_status[2] = hb_counter[24];
45  assign system_status[3] = hb_counter[25];
46  
47  endmodule