1  `timescale 1ns / 1ps
 2  //
 3  // AERIS-10 TE0713+TE0701 Dev Heartbeat
 4  //
 5  // Minimal design to verify FPGA configuration and clock.
 6  // Uses TE0713 FIFO0CLK (50 MHz, Bank 14, LVCMOS15) at pin U20.
 7  // LEDs and status outputs on Bank 16 FMC LA pins (LVCMOS33).
 8  //
 9  // At 50 MHz:
10  //   user_led[0] toggles at ~1.49 Hz  (bit 24)
11  //   user_led[1] toggles at ~0.75 Hz  (bit 25)
12  //   user_led[2] toggles at ~0.37 Hz  (bit 26)
13  //   user_led[3] toggles at ~0.19 Hz  (bit 27)
14  //
15  
16  module radar_system_top_te0713_dev (
17      input wire clk_100m,        // TE0713 FIFO0CLK (actually 50 MHz)
18      output wire [3:0] user_led,
19      output wire [3:0] system_status
20  );
21  
22  wire clk_buf;
23  reg [31:0] hb_counter = 32'd0;
24  
25  BUFG bufg_clk (
26      .I(clk_100m),
27      .O(clk_buf)
28  );
29  
30  always @(posedge clk_buf) begin
31      hb_counter <= hb_counter + 1'b1;
32  end
33  
34  assign user_led[0] = hb_counter[24];
35  assign user_led[1] = hb_counter[25];
36  assign user_led[2] = hb_counter[26];
37  assign user_led[3] = hb_counter[27];
38  
39  assign system_status[0] = hb_counter[23];
40  assign system_status[1] = hb_counter[24];
41  assign system_status[2] = hb_counter[25];
42  assign system_status[3] = hb_counter[26];
43  
44  endmodule