cmsis_armclang_ltm.h
1 /**************************************************************************//** 2 * @file cmsis_armclang_ltm.h 3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file 4 * @version V1.5.3 5 * @date 27. May 2021 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2018-2021 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ 26 27 #ifndef __CMSIS_ARMCLANG_H 28 #define __CMSIS_ARMCLANG_H 29 30 #pragma clang system_header /* treat file as system include file */ 31 32 /* CMSIS compiler specific defines */ 33 #ifndef __ASM 34 #define __ASM __asm 35 #endif 36 #ifndef __INLINE 37 #define __INLINE __inline 38 #endif 39 #ifndef __STATIC_INLINE 40 #define __STATIC_INLINE static __inline 41 #endif 42 #ifndef __STATIC_FORCEINLINE 43 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline 44 #endif 45 #ifndef __NO_RETURN 46 #define __NO_RETURN __attribute__((__noreturn__)) 47 #endif 48 #ifndef __USED 49 #define __USED __attribute__((used)) 50 #endif 51 #ifndef __WEAK 52 #define __WEAK __attribute__((weak)) 53 #endif 54 #ifndef __PACKED 55 #define __PACKED __attribute__((packed, aligned(1))) 56 #endif 57 #ifndef __PACKED_STRUCT 58 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 59 #endif 60 #ifndef __PACKED_UNION 61 #define __PACKED_UNION union __attribute__((packed, aligned(1))) 62 #endif 63 #ifndef __UNALIGNED_UINT32 /* deprecated */ 64 #pragma clang diagnostic push 65 #pragma clang diagnostic ignored "-Wpacked" 66 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ 67 struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 68 #pragma clang diagnostic pop 69 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 70 #endif 71 #ifndef __UNALIGNED_UINT16_WRITE 72 #pragma clang diagnostic push 73 #pragma clang diagnostic ignored "-Wpacked" 74 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ 75 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 76 #pragma clang diagnostic pop 77 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 78 #endif 79 #ifndef __UNALIGNED_UINT16_READ 80 #pragma clang diagnostic push 81 #pragma clang diagnostic ignored "-Wpacked" 82 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ 83 __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 84 #pragma clang diagnostic pop 85 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 86 #endif 87 #ifndef __UNALIGNED_UINT32_WRITE 88 #pragma clang diagnostic push 89 #pragma clang diagnostic ignored "-Wpacked" 90 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ 91 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 92 #pragma clang diagnostic pop 93 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 94 #endif 95 #ifndef __UNALIGNED_UINT32_READ 96 #pragma clang diagnostic push 97 #pragma clang diagnostic ignored "-Wpacked" 98 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ 99 __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 100 #pragma clang diagnostic pop 101 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 102 #endif 103 #ifndef __ALIGNED 104 #define __ALIGNED(x) __attribute__((aligned(x))) 105 #endif 106 #ifndef __RESTRICT 107 #define __RESTRICT __restrict 108 #endif 109 #ifndef __COMPILER_BARRIER 110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 111 #endif 112 113 /* ######################### Startup and Lowlevel Init ######################## */ 114 115 #ifndef __PROGRAM_START 116 #define __PROGRAM_START __main 117 #endif 118 119 #ifndef __INITIAL_SP 120 #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit 121 #endif 122 123 #ifndef __STACK_LIMIT 124 #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base 125 #endif 126 127 #ifndef __VECTOR_TABLE 128 #define __VECTOR_TABLE __Vectors 129 #endif 130 131 #ifndef __VECTOR_TABLE_ATTRIBUTE 132 #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) 133 #endif 134 135 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 136 #ifndef __STACK_SEAL 137 #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base 138 #endif 139 140 #ifndef __TZ_STACK_SEAL_SIZE 141 #define __TZ_STACK_SEAL_SIZE 8U 142 #endif 143 144 #ifndef __TZ_STACK_SEAL_VALUE 145 #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL 146 #endif 147 148 149 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { 150 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; 151 } 152 #endif 153 154 155 /* ########################## Core Instruction Access ######################### */ 156 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 157 Access to dedicated instructions 158 @{ 159 */ 160 161 /* Define macros for porting to both thumb1 and thumb2. 162 * For thumb1, use low register (r0-r7), specified by constraint "l" 163 * Otherwise, use general registers, specified by constraint "r" */ 164 #if defined (__thumb__) && !defined (__thumb2__) 165 #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 166 #define __CMSIS_GCC_USE_REG(r) "l" (r) 167 #else 168 #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 169 #define __CMSIS_GCC_USE_REG(r) "r" (r) 170 #endif 171 172 /** 173 \brief No Operation 174 \details No Operation does nothing. This instruction can be used for code alignment purposes. 175 */ 176 #define __NOP __builtin_arm_nop 177 178 /** 179 \brief Wait For Interrupt 180 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. 181 */ 182 #define __WFI __builtin_arm_wfi 183 184 185 /** 186 \brief Wait For Event 187 \details Wait For Event is a hint instruction that permits the processor to enter 188 a low-power state until one of a number of events occurs. 189 */ 190 #define __WFE __builtin_arm_wfe 191 192 193 /** 194 \brief Send Event 195 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 196 */ 197 #define __SEV __builtin_arm_sev 198 199 200 /** 201 \brief Instruction Synchronization Barrier 202 \details Instruction Synchronization Barrier flushes the pipeline in the processor, 203 so that all instructions following the ISB are fetched from cache or memory, 204 after the instruction has been completed. 205 */ 206 #define __ISB() __builtin_arm_isb(0xF) 207 208 /** 209 \brief Data Synchronization Barrier 210 \details Acts as a special kind of Data Memory Barrier. 211 It completes when all explicit memory accesses before this instruction complete. 212 */ 213 #define __DSB() __builtin_arm_dsb(0xF) 214 215 216 /** 217 \brief Data Memory Barrier 218 \details Ensures the apparent order of the explicit memory operations before 219 and after the instruction, without ensuring their completion. 220 */ 221 #define __DMB() __builtin_arm_dmb(0xF) 222 223 224 /** 225 \brief Reverse byte order (32 bit) 226 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. 227 \param [in] value Value to reverse 228 \return Reversed value 229 */ 230 #define __REV(value) __builtin_bswap32(value) 231 232 233 /** 234 \brief Reverse byte order (16 bit) 235 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. 236 \param [in] value Value to reverse 237 \return Reversed value 238 */ 239 #define __REV16(value) __ROR(__REV(value), 16) 240 241 242 /** 243 \brief Reverse byte order (16 bit) 244 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. 245 \param [in] value Value to reverse 246 \return Reversed value 247 */ 248 #define __REVSH(value) (int16_t)__builtin_bswap16(value) 249 250 251 /** 252 \brief Rotate Right in unsigned value (32 bit) 253 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 254 \param [in] op1 Value to rotate 255 \param [in] op2 Number of Bits to rotate 256 \return Rotated value 257 */ 258 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 259 { 260 op2 %= 32U; 261 if (op2 == 0U) 262 { 263 return op1; 264 } 265 return (op1 >> op2) | (op1 << (32U - op2)); 266 } 267 268 269 /** 270 \brief Breakpoint 271 \details Causes the processor to enter Debug state. 272 Debug tools can use this to investigate system state when the instruction at a particular address is reached. 273 \param [in] value is ignored by the processor. 274 If required, a debugger can use it to store additional information about the breakpoint. 275 */ 276 #define __BKPT(value) __ASM volatile ("bkpt "#value) 277 278 279 /** 280 \brief Reverse bit order of value 281 \details Reverses the bit order of the given value. 282 \param [in] value Value to reverse 283 \return Reversed value 284 */ 285 #define __RBIT __builtin_arm_rbit 286 287 /** 288 \brief Count leading zeros 289 \details Counts the number of leading zeros of a data value. 290 \param [in] value Value to count the leading zeros 291 \return number of leading zeros in value 292 */ 293 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) 294 { 295 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally 296 __builtin_clz(0) is undefined behaviour, so handle this case specially. 297 This guarantees ARM-compatible results if happening to compile on a non-ARM 298 target, and ensures the compiler doesn't decide to activate any 299 optimisations using the logic "value was passed to __builtin_clz, so it 300 is non-zero". 301 ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a 302 single CLZ instruction. 303 */ 304 if (value == 0U) 305 { 306 return 32U; 307 } 308 return __builtin_clz(value); 309 } 310 311 312 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 313 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 314 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 315 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 316 /** 317 \brief LDR Exclusive (8 bit) 318 \details Executes a exclusive LDR instruction for 8 bit value. 319 \param [in] ptr Pointer to data 320 \return value of type uint8_t at (*ptr) 321 */ 322 #define __LDREXB (uint8_t)__builtin_arm_ldrex 323 324 325 /** 326 \brief LDR Exclusive (16 bit) 327 \details Executes a exclusive LDR instruction for 16 bit values. 328 \param [in] ptr Pointer to data 329 \return value of type uint16_t at (*ptr) 330 */ 331 #define __LDREXH (uint16_t)__builtin_arm_ldrex 332 333 334 /** 335 \brief LDR Exclusive (32 bit) 336 \details Executes a exclusive LDR instruction for 32 bit values. 337 \param [in] ptr Pointer to data 338 \return value of type uint32_t at (*ptr) 339 */ 340 #define __LDREXW (uint32_t)__builtin_arm_ldrex 341 342 343 /** 344 \brief STR Exclusive (8 bit) 345 \details Executes a exclusive STR instruction for 8 bit values. 346 \param [in] value Value to store 347 \param [in] ptr Pointer to location 348 \return 0 Function succeeded 349 \return 1 Function failed 350 */ 351 #define __STREXB (uint32_t)__builtin_arm_strex 352 353 354 /** 355 \brief STR Exclusive (16 bit) 356 \details Executes a exclusive STR instruction for 16 bit values. 357 \param [in] value Value to store 358 \param [in] ptr Pointer to location 359 \return 0 Function succeeded 360 \return 1 Function failed 361 */ 362 #define __STREXH (uint32_t)__builtin_arm_strex 363 364 365 /** 366 \brief STR Exclusive (32 bit) 367 \details Executes a exclusive STR instruction for 32 bit values. 368 \param [in] value Value to store 369 \param [in] ptr Pointer to location 370 \return 0 Function succeeded 371 \return 1 Function failed 372 */ 373 #define __STREXW (uint32_t)__builtin_arm_strex 374 375 376 /** 377 \brief Remove the exclusive lock 378 \details Removes the exclusive lock which is created by LDREX. 379 */ 380 #define __CLREX __builtin_arm_clrex 381 382 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 383 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 384 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 385 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 386 387 388 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 389 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 390 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 391 392 /** 393 \brief Signed Saturate 394 \details Saturates a signed value. 395 \param [in] value Value to be saturated 396 \param [in] sat Bit position to saturate to (1..32) 397 \return Saturated value 398 */ 399 #define __SSAT __builtin_arm_ssat 400 401 402 /** 403 \brief Unsigned Saturate 404 \details Saturates an unsigned value. 405 \param [in] value Value to be saturated 406 \param [in] sat Bit position to saturate to (0..31) 407 \return Saturated value 408 */ 409 #define __USAT __builtin_arm_usat 410 411 412 /** 413 \brief Rotate Right with Extend (32 bit) 414 \details Moves each bit of a bitstring right by one bit. 415 The carry input is shifted in at the left end of the bitstring. 416 \param [in] value Value to rotate 417 \return Rotated value 418 */ 419 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) 420 { 421 uint32_t result; 422 423 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 424 return(result); 425 } 426 427 428 /** 429 \brief LDRT Unprivileged (8 bit) 430 \details Executes a Unprivileged LDRT instruction for 8 bit value. 431 \param [in] ptr Pointer to data 432 \return value of type uint8_t at (*ptr) 433 */ 434 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) 435 { 436 uint32_t result; 437 438 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); 439 return ((uint8_t) result); /* Add explicit type cast here */ 440 } 441 442 443 /** 444 \brief LDRT Unprivileged (16 bit) 445 \details Executes a Unprivileged LDRT instruction for 16 bit values. 446 \param [in] ptr Pointer to data 447 \return value of type uint16_t at (*ptr) 448 */ 449 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) 450 { 451 uint32_t result; 452 453 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 454 return ((uint16_t) result); /* Add explicit type cast here */ 455 } 456 457 458 /** 459 \brief LDRT Unprivileged (32 bit) 460 \details Executes a Unprivileged LDRT instruction for 32 bit values. 461 \param [in] ptr Pointer to data 462 \return value of type uint32_t at (*ptr) 463 */ 464 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) 465 { 466 uint32_t result; 467 468 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 469 return(result); 470 } 471 472 473 /** 474 \brief STRT Unprivileged (8 bit) 475 \details Executes a Unprivileged STRT instruction for 8 bit values. 476 \param [in] value Value to store 477 \param [in] ptr Pointer to location 478 */ 479 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) 480 { 481 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 482 } 483 484 485 /** 486 \brief STRT Unprivileged (16 bit) 487 \details Executes a Unprivileged STRT instruction for 16 bit values. 488 \param [in] value Value to store 489 \param [in] ptr Pointer to location 490 */ 491 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) 492 { 493 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 494 } 495 496 497 /** 498 \brief STRT Unprivileged (32 bit) 499 \details Executes a Unprivileged STRT instruction for 32 bit values. 500 \param [in] value Value to store 501 \param [in] ptr Pointer to location 502 */ 503 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) 504 { 505 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); 506 } 507 508 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 509 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 510 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 511 512 /** 513 \brief Signed Saturate 514 \details Saturates a signed value. 515 \param [in] value Value to be saturated 516 \param [in] sat Bit position to saturate to (1..32) 517 \return Saturated value 518 */ 519 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) 520 { 521 if ((sat >= 1U) && (sat <= 32U)) 522 { 523 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 524 const int32_t min = -1 - max ; 525 if (val > max) 526 { 527 return max; 528 } 529 else if (val < min) 530 { 531 return min; 532 } 533 } 534 return val; 535 } 536 537 /** 538 \brief Unsigned Saturate 539 \details Saturates an unsigned value. 540 \param [in] value Value to be saturated 541 \param [in] sat Bit position to saturate to (0..31) 542 \return Saturated value 543 */ 544 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) 545 { 546 if (sat <= 31U) 547 { 548 const uint32_t max = ((1U << sat) - 1U); 549 if (val > (int32_t)max) 550 { 551 return max; 552 } 553 else if (val < 0) 554 { 555 return 0U; 556 } 557 } 558 return (uint32_t)val; 559 } 560 561 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 562 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 563 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 564 565 566 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 567 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 568 /** 569 \brief Load-Acquire (8 bit) 570 \details Executes a LDAB instruction for 8 bit value. 571 \param [in] ptr Pointer to data 572 \return value of type uint8_t at (*ptr) 573 */ 574 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) 575 { 576 uint32_t result; 577 578 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 579 return ((uint8_t) result); 580 } 581 582 583 /** 584 \brief Load-Acquire (16 bit) 585 \details Executes a LDAH instruction for 16 bit values. 586 \param [in] ptr Pointer to data 587 \return value of type uint16_t at (*ptr) 588 */ 589 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) 590 { 591 uint32_t result; 592 593 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 594 return ((uint16_t) result); 595 } 596 597 598 /** 599 \brief Load-Acquire (32 bit) 600 \details Executes a LDA instruction for 32 bit values. 601 \param [in] ptr Pointer to data 602 \return value of type uint32_t at (*ptr) 603 */ 604 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) 605 { 606 uint32_t result; 607 608 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 609 return(result); 610 } 611 612 613 /** 614 \brief Store-Release (8 bit) 615 \details Executes a STLB instruction for 8 bit values. 616 \param [in] value Value to store 617 \param [in] ptr Pointer to location 618 */ 619 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) 620 { 621 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 622 } 623 624 625 /** 626 \brief Store-Release (16 bit) 627 \details Executes a STLH instruction for 16 bit values. 628 \param [in] value Value to store 629 \param [in] ptr Pointer to location 630 */ 631 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) 632 { 633 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 634 } 635 636 637 /** 638 \brief Store-Release (32 bit) 639 \details Executes a STL instruction for 32 bit values. 640 \param [in] value Value to store 641 \param [in] ptr Pointer to location 642 */ 643 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) 644 { 645 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 646 } 647 648 649 /** 650 \brief Load-Acquire Exclusive (8 bit) 651 \details Executes a LDAB exclusive instruction for 8 bit value. 652 \param [in] ptr Pointer to data 653 \return value of type uint8_t at (*ptr) 654 */ 655 #define __LDAEXB (uint8_t)__builtin_arm_ldaex 656 657 658 /** 659 \brief Load-Acquire Exclusive (16 bit) 660 \details Executes a LDAH exclusive instruction for 16 bit values. 661 \param [in] ptr Pointer to data 662 \return value of type uint16_t at (*ptr) 663 */ 664 #define __LDAEXH (uint16_t)__builtin_arm_ldaex 665 666 667 /** 668 \brief Load-Acquire Exclusive (32 bit) 669 \details Executes a LDA exclusive instruction for 32 bit values. 670 \param [in] ptr Pointer to data 671 \return value of type uint32_t at (*ptr) 672 */ 673 #define __LDAEX (uint32_t)__builtin_arm_ldaex 674 675 676 /** 677 \brief Store-Release Exclusive (8 bit) 678 \details Executes a STLB exclusive instruction for 8 bit values. 679 \param [in] value Value to store 680 \param [in] ptr Pointer to location 681 \return 0 Function succeeded 682 \return 1 Function failed 683 */ 684 #define __STLEXB (uint32_t)__builtin_arm_stlex 685 686 687 /** 688 \brief Store-Release Exclusive (16 bit) 689 \details Executes a STLH exclusive instruction for 16 bit values. 690 \param [in] value Value to store 691 \param [in] ptr Pointer to location 692 \return 0 Function succeeded 693 \return 1 Function failed 694 */ 695 #define __STLEXH (uint32_t)__builtin_arm_stlex 696 697 698 /** 699 \brief Store-Release Exclusive (32 bit) 700 \details Executes a STL exclusive instruction for 32 bit values. 701 \param [in] value Value to store 702 \param [in] ptr Pointer to location 703 \return 0 Function succeeded 704 \return 1 Function failed 705 */ 706 #define __STLEX (uint32_t)__builtin_arm_stlex 707 708 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 709 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 710 711 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 712 713 714 /* ########################### Core Function Access ########################### */ 715 /** \ingroup CMSIS_Core_FunctionInterface 716 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 717 @{ 718 */ 719 720 /** 721 \brief Enable IRQ Interrupts 722 \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. 723 Can only be executed in Privileged modes. 724 */ 725 #ifndef __ARM_COMPAT_H 726 __STATIC_FORCEINLINE void __enable_irq(void) 727 { 728 __ASM volatile ("cpsie i" : : : "memory"); 729 } 730 #endif 731 732 733 /** 734 \brief Disable IRQ Interrupts 735 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. 736 Can only be executed in Privileged modes. 737 */ 738 #ifndef __ARM_COMPAT_H 739 __STATIC_FORCEINLINE void __disable_irq(void) 740 { 741 __ASM volatile ("cpsid i" : : : "memory"); 742 } 743 #endif 744 745 746 /** 747 \brief Get Control Register 748 \details Returns the content of the Control Register. 749 \return Control Register value 750 */ 751 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 752 { 753 uint32_t result; 754 755 __ASM volatile ("MRS %0, control" : "=r" (result) ); 756 return(result); 757 } 758 759 760 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 761 /** 762 \brief Get Control Register (non-secure) 763 \details Returns the content of the non-secure Control Register when in secure mode. 764 \return non-secure Control Register value 765 */ 766 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 767 { 768 uint32_t result; 769 770 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 771 return(result); 772 } 773 #endif 774 775 776 /** 777 \brief Set Control Register 778 \details Writes the given value to the Control Register. 779 \param [in] control Control Register value to set 780 */ 781 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 782 { 783 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 784 __ISB(); 785 } 786 787 788 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 789 /** 790 \brief Set Control Register (non-secure) 791 \details Writes the given value to the non-secure Control Register when in secure state. 792 \param [in] control Control Register value to set 793 */ 794 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 795 { 796 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 797 __ISB(); 798 } 799 #endif 800 801 802 /** 803 \brief Get IPSR Register 804 \details Returns the content of the IPSR Register. 805 \return IPSR Register value 806 */ 807 __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 808 { 809 uint32_t result; 810 811 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 812 return(result); 813 } 814 815 816 /** 817 \brief Get APSR Register 818 \details Returns the content of the APSR Register. 819 \return APSR Register value 820 */ 821 __STATIC_FORCEINLINE uint32_t __get_APSR(void) 822 { 823 uint32_t result; 824 825 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 826 return(result); 827 } 828 829 830 /** 831 \brief Get xPSR Register 832 \details Returns the content of the xPSR Register. 833 \return xPSR Register value 834 */ 835 __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 836 { 837 uint32_t result; 838 839 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 840 return(result); 841 } 842 843 844 /** 845 \brief Get Process Stack Pointer 846 \details Returns the current value of the Process Stack Pointer (PSP). 847 \return PSP Register value 848 */ 849 __STATIC_FORCEINLINE uint32_t __get_PSP(void) 850 { 851 uint32_t result; 852 853 __ASM volatile ("MRS %0, psp" : "=r" (result) ); 854 return(result); 855 } 856 857 858 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 859 /** 860 \brief Get Process Stack Pointer (non-secure) 861 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. 862 \return PSP Register value 863 */ 864 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 865 { 866 uint32_t result; 867 868 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 869 return(result); 870 } 871 #endif 872 873 874 /** 875 \brief Set Process Stack Pointer 876 \details Assigns the given value to the Process Stack Pointer (PSP). 877 \param [in] topOfProcStack Process Stack Pointer value to set 878 */ 879 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 880 { 881 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 882 } 883 884 885 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 886 /** 887 \brief Set Process Stack Pointer (non-secure) 888 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. 889 \param [in] topOfProcStack Process Stack Pointer value to set 890 */ 891 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 892 { 893 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 894 } 895 #endif 896 897 898 /** 899 \brief Get Main Stack Pointer 900 \details Returns the current value of the Main Stack Pointer (MSP). 901 \return MSP Register value 902 */ 903 __STATIC_FORCEINLINE uint32_t __get_MSP(void) 904 { 905 uint32_t result; 906 907 __ASM volatile ("MRS %0, msp" : "=r" (result) ); 908 return(result); 909 } 910 911 912 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 913 /** 914 \brief Get Main Stack Pointer (non-secure) 915 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. 916 \return MSP Register value 917 */ 918 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 919 { 920 uint32_t result; 921 922 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 923 return(result); 924 } 925 #endif 926 927 928 /** 929 \brief Set Main Stack Pointer 930 \details Assigns the given value to the Main Stack Pointer (MSP). 931 \param [in] topOfMainStack Main Stack Pointer value to set 932 */ 933 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 934 { 935 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 936 } 937 938 939 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 940 /** 941 \brief Set Main Stack Pointer (non-secure) 942 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 943 \param [in] topOfMainStack Main Stack Pointer value to set 944 */ 945 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 946 { 947 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 948 } 949 #endif 950 951 952 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 953 /** 954 \brief Get Stack Pointer (non-secure) 955 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 956 \return SP Register value 957 */ 958 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 959 { 960 uint32_t result; 961 962 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 963 return(result); 964 } 965 966 967 /** 968 \brief Set Stack Pointer (non-secure) 969 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 970 \param [in] topOfStack Stack Pointer value to set 971 */ 972 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 973 { 974 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 975 } 976 #endif 977 978 979 /** 980 \brief Get Priority Mask 981 \details Returns the current state of the priority mask bit from the Priority Mask Register. 982 \return Priority Mask value 983 */ 984 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 985 { 986 uint32_t result; 987 988 __ASM volatile ("MRS %0, primask" : "=r" (result) ); 989 return(result); 990 } 991 992 993 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 994 /** 995 \brief Get Priority Mask (non-secure) 996 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. 997 \return Priority Mask value 998 */ 999 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 1000 { 1001 uint32_t result; 1002 1003 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); 1004 return(result); 1005 } 1006 #endif 1007 1008 1009 /** 1010 \brief Set Priority Mask 1011 \details Assigns the given value to the Priority Mask Register. 1012 \param [in] priMask Priority Mask 1013 */ 1014 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 1015 { 1016 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 1017 } 1018 1019 1020 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1021 /** 1022 \brief Set Priority Mask (non-secure) 1023 \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 1024 \param [in] priMask Priority Mask 1025 */ 1026 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 1027 { 1028 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 1029 } 1030 #endif 1031 1032 1033 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1034 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1035 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 1036 /** 1037 \brief Enable FIQ 1038 \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. 1039 Can only be executed in Privileged modes. 1040 */ 1041 __STATIC_FORCEINLINE void __enable_fault_irq(void) 1042 { 1043 __ASM volatile ("cpsie f" : : : "memory"); 1044 } 1045 1046 1047 /** 1048 \brief Disable FIQ 1049 \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. 1050 Can only be executed in Privileged modes. 1051 */ 1052 __STATIC_FORCEINLINE void __disable_fault_irq(void) 1053 { 1054 __ASM volatile ("cpsid f" : : : "memory"); 1055 } 1056 1057 1058 /** 1059 \brief Get Base Priority 1060 \details Returns the current value of the Base Priority register. 1061 \return Base Priority register value 1062 */ 1063 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 1064 { 1065 uint32_t result; 1066 1067 __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 1068 return(result); 1069 } 1070 1071 1072 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1073 /** 1074 \brief Get Base Priority (non-secure) 1075 \details Returns the current value of the non-secure Base Priority register when in secure state. 1076 \return Base Priority register value 1077 */ 1078 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 1079 { 1080 uint32_t result; 1081 1082 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 1083 return(result); 1084 } 1085 #endif 1086 1087 1088 /** 1089 \brief Set Base Priority 1090 \details Assigns the given value to the Base Priority register. 1091 \param [in] basePri Base Priority value to set 1092 */ 1093 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 1094 { 1095 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 1096 } 1097 1098 1099 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1100 /** 1101 \brief Set Base Priority (non-secure) 1102 \details Assigns the given value to the non-secure Base Priority register when in secure state. 1103 \param [in] basePri Base Priority value to set 1104 */ 1105 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 1106 { 1107 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 1108 } 1109 #endif 1110 1111 1112 /** 1113 \brief Set Base Priority with condition 1114 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, 1115 or the new value increases the BASEPRI priority level. 1116 \param [in] basePri Base Priority value to set 1117 */ 1118 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 1119 { 1120 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 1121 } 1122 1123 1124 /** 1125 \brief Get Fault Mask 1126 \details Returns the current value of the Fault Mask register. 1127 \return Fault Mask register value 1128 */ 1129 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 1130 { 1131 uint32_t result; 1132 1133 __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 1134 return(result); 1135 } 1136 1137 1138 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1139 /** 1140 \brief Get Fault Mask (non-secure) 1141 \details Returns the current value of the non-secure Fault Mask register when in secure state. 1142 \return Fault Mask register value 1143 */ 1144 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 1145 { 1146 uint32_t result; 1147 1148 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 1149 return(result); 1150 } 1151 #endif 1152 1153 1154 /** 1155 \brief Set Fault Mask 1156 \details Assigns the given value to the Fault Mask register. 1157 \param [in] faultMask Fault Mask value to set 1158 */ 1159 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 1160 { 1161 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 1162 } 1163 1164 1165 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1166 /** 1167 \brief Set Fault Mask (non-secure) 1168 \details Assigns the given value to the non-secure Fault Mask register when in secure state. 1169 \param [in] faultMask Fault Mask value to set 1170 */ 1171 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 1172 { 1173 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 1174 } 1175 #endif 1176 1177 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1178 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1179 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 1180 1181 1182 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1183 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 1184 1185 /** 1186 \brief Get Process Stack Pointer Limit 1187 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1188 Stack Pointer Limit register hence zero is returned always in non-secure 1189 mode. 1190 1191 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 1192 \return PSPLIM Register value 1193 */ 1194 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 1195 { 1196 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 1197 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 1198 // without main extensions, the non-secure PSPLIM is RAZ/WI 1199 return 0U; 1200 #else 1201 uint32_t result; 1202 __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 1203 return result; 1204 #endif 1205 } 1206 1207 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 1208 /** 1209 \brief Get Process Stack Pointer Limit (non-secure) 1210 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1211 Stack Pointer Limit register hence zero is returned always in non-secure 1212 mode. 1213 1214 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. 1215 \return PSPLIM Register value 1216 */ 1217 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 1218 { 1219 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 1220 // without main extensions, the non-secure PSPLIM is RAZ/WI 1221 return 0U; 1222 #else 1223 uint32_t result; 1224 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 1225 return result; 1226 #endif 1227 } 1228 #endif 1229 1230 1231 /** 1232 \brief Set Process Stack Pointer Limit 1233 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1234 Stack Pointer Limit register hence the write is silently ignored in non-secure 1235 mode. 1236 1237 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 1238 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 1239 */ 1240 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 1241 { 1242 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 1243 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 1244 // without main extensions, the non-secure PSPLIM is RAZ/WI 1245 (void)ProcStackPtrLimit; 1246 #else 1247 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 1248 #endif 1249 } 1250 1251 1252 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1253 /** 1254 \brief Set Process Stack Pointer (non-secure) 1255 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1256 Stack Pointer Limit register hence the write is silently ignored in non-secure 1257 mode. 1258 1259 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. 1260 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 1261 */ 1262 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 1263 { 1264 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 1265 // without main extensions, the non-secure PSPLIM is RAZ/WI 1266 (void)ProcStackPtrLimit; 1267 #else 1268 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 1269 #endif 1270 } 1271 #endif 1272 1273 1274 /** 1275 \brief Get Main Stack Pointer Limit 1276 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1277 Stack Pointer Limit register hence zero is returned always. 1278 1279 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 1280 \return MSPLIM Register value 1281 */ 1282 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 1283 { 1284 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 1285 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 1286 // without main extensions, the non-secure MSPLIM is RAZ/WI 1287 return 0U; 1288 #else 1289 uint32_t result; 1290 __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 1291 return result; 1292 #endif 1293 } 1294 1295 1296 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1297 /** 1298 \brief Get Main Stack Pointer Limit (non-secure) 1299 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1300 Stack Pointer Limit register hence zero is returned always. 1301 1302 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. 1303 \return MSPLIM Register value 1304 */ 1305 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 1306 { 1307 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 1308 // without main extensions, the non-secure MSPLIM is RAZ/WI 1309 return 0U; 1310 #else 1311 uint32_t result; 1312 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 1313 return result; 1314 #endif 1315 } 1316 #endif 1317 1318 1319 /** 1320 \brief Set Main Stack Pointer Limit 1321 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1322 Stack Pointer Limit register hence the write is silently ignored. 1323 1324 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 1325 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 1326 */ 1327 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 1328 { 1329 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 1330 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 1331 // without main extensions, the non-secure MSPLIM is RAZ/WI 1332 (void)MainStackPtrLimit; 1333 #else 1334 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 1335 #endif 1336 } 1337 1338 1339 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 1340 /** 1341 \brief Set Main Stack Pointer Limit (non-secure) 1342 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 1343 Stack Pointer Limit register hence the write is silently ignored. 1344 1345 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. 1346 \param [in] MainStackPtrLimit Main Stack Pointer value to set 1347 */ 1348 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 1349 { 1350 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 1351 // without main extensions, the non-secure MSPLIM is RAZ/WI 1352 (void)MainStackPtrLimit; 1353 #else 1354 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 1355 #endif 1356 } 1357 #endif 1358 1359 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1360 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 1361 1362 /** 1363 \brief Get FPSCR 1364 \details Returns the current value of the Floating Point Status/Control register. 1365 \return Floating Point Status/Control register value 1366 */ 1367 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 1368 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 1369 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr 1370 #else 1371 #define __get_FPSCR() ((uint32_t)0U) 1372 #endif 1373 1374 /** 1375 \brief Set FPSCR 1376 \details Assigns the given value to the Floating Point Status/Control register. 1377 \param [in] fpscr Floating Point Status/Control value to set 1378 */ 1379 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 1380 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 1381 #define __set_FPSCR __builtin_arm_set_fpscr 1382 #else 1383 #define __set_FPSCR(x) ((void)(x)) 1384 #endif 1385 1386 1387 /*@} end of CMSIS_Core_RegAccFunctions */ 1388 1389 1390 /* ################### Compiler specific Intrinsics ########################### */ 1391 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 1392 Access to dedicated SIMD instructions 1393 @{ 1394 */ 1395 1396 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) 1397 1398 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) 1399 { 1400 uint32_t result; 1401 1402 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1403 return(result); 1404 } 1405 1406 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) 1407 { 1408 uint32_t result; 1409 1410 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1411 return(result); 1412 } 1413 1414 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) 1415 { 1416 uint32_t result; 1417 1418 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1419 return(result); 1420 } 1421 1422 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) 1423 { 1424 uint32_t result; 1425 1426 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1427 return(result); 1428 } 1429 1430 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) 1431 { 1432 uint32_t result; 1433 1434 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1435 return(result); 1436 } 1437 1438 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) 1439 { 1440 uint32_t result; 1441 1442 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1443 return(result); 1444 } 1445 1446 1447 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) 1448 { 1449 uint32_t result; 1450 1451 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1452 return(result); 1453 } 1454 1455 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) 1456 { 1457 uint32_t result; 1458 1459 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1460 return(result); 1461 } 1462 1463 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) 1464 { 1465 uint32_t result; 1466 1467 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1468 return(result); 1469 } 1470 1471 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) 1472 { 1473 uint32_t result; 1474 1475 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1476 return(result); 1477 } 1478 1479 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) 1480 { 1481 uint32_t result; 1482 1483 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1484 return(result); 1485 } 1486 1487 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) 1488 { 1489 uint32_t result; 1490 1491 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1492 return(result); 1493 } 1494 1495 1496 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) 1497 { 1498 uint32_t result; 1499 1500 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1501 return(result); 1502 } 1503 1504 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) 1505 { 1506 uint32_t result; 1507 1508 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1509 return(result); 1510 } 1511 1512 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) 1513 { 1514 uint32_t result; 1515 1516 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1517 return(result); 1518 } 1519 1520 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) 1521 { 1522 uint32_t result; 1523 1524 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1525 return(result); 1526 } 1527 1528 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) 1529 { 1530 uint32_t result; 1531 1532 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1533 return(result); 1534 } 1535 1536 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) 1537 { 1538 uint32_t result; 1539 1540 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1541 return(result); 1542 } 1543 1544 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) 1545 { 1546 uint32_t result; 1547 1548 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1549 return(result); 1550 } 1551 1552 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) 1553 { 1554 uint32_t result; 1555 1556 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1557 return(result); 1558 } 1559 1560 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) 1561 { 1562 uint32_t result; 1563 1564 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1565 return(result); 1566 } 1567 1568 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) 1569 { 1570 uint32_t result; 1571 1572 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1573 return(result); 1574 } 1575 1576 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) 1577 { 1578 uint32_t result; 1579 1580 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1581 return(result); 1582 } 1583 1584 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) 1585 { 1586 uint32_t result; 1587 1588 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1589 return(result); 1590 } 1591 1592 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) 1593 { 1594 uint32_t result; 1595 1596 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1597 return(result); 1598 } 1599 1600 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) 1601 { 1602 uint32_t result; 1603 1604 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1605 return(result); 1606 } 1607 1608 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) 1609 { 1610 uint32_t result; 1611 1612 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1613 return(result); 1614 } 1615 1616 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) 1617 { 1618 uint32_t result; 1619 1620 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1621 return(result); 1622 } 1623 1624 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) 1625 { 1626 uint32_t result; 1627 1628 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1629 return(result); 1630 } 1631 1632 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) 1633 { 1634 uint32_t result; 1635 1636 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1637 return(result); 1638 } 1639 1640 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) 1641 { 1642 uint32_t result; 1643 1644 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1645 return(result); 1646 } 1647 1648 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) 1649 { 1650 uint32_t result; 1651 1652 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1653 return(result); 1654 } 1655 1656 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) 1657 { 1658 uint32_t result; 1659 1660 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1661 return(result); 1662 } 1663 1664 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) 1665 { 1666 uint32_t result; 1667 1668 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1669 return(result); 1670 } 1671 1672 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) 1673 { 1674 uint32_t result; 1675 1676 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1677 return(result); 1678 } 1679 1680 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) 1681 { 1682 uint32_t result; 1683 1684 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1685 return(result); 1686 } 1687 1688 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) 1689 { 1690 uint32_t result; 1691 1692 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1693 return(result); 1694 } 1695 1696 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) 1697 { 1698 uint32_t result; 1699 1700 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1701 return(result); 1702 } 1703 1704 #define __SSAT16(ARG1,ARG2) \ 1705 ({ \ 1706 int32_t __RES, __ARG1 = (ARG1); \ 1707 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 1708 __RES; \ 1709 }) 1710 1711 #define __USAT16(ARG1,ARG2) \ 1712 ({ \ 1713 uint32_t __RES, __ARG1 = (ARG1); \ 1714 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 1715 __RES; \ 1716 }) 1717 1718 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) 1719 { 1720 uint32_t result; 1721 1722 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); 1723 return(result); 1724 } 1725 1726 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) 1727 { 1728 uint32_t result; 1729 1730 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1731 return(result); 1732 } 1733 1734 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) 1735 { 1736 uint32_t result; 1737 1738 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); 1739 return(result); 1740 } 1741 1742 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) 1743 { 1744 uint32_t result; 1745 1746 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1747 return(result); 1748 } 1749 1750 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) 1751 { 1752 uint32_t result; 1753 1754 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1755 return(result); 1756 } 1757 1758 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) 1759 { 1760 uint32_t result; 1761 1762 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1763 return(result); 1764 } 1765 1766 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) 1767 { 1768 uint32_t result; 1769 1770 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1771 return(result); 1772 } 1773 1774 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) 1775 { 1776 uint32_t result; 1777 1778 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1779 return(result); 1780 } 1781 1782 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) 1783 { 1784 union llreg_u{ 1785 uint32_t w32[2]; 1786 uint64_t w64; 1787 } llr; 1788 llr.w64 = acc; 1789 1790 #ifndef __ARMEB__ /* Little endian */ 1791 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 1792 #else /* Big endian */ 1793 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 1794 #endif 1795 1796 return(llr.w64); 1797 } 1798 1799 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) 1800 { 1801 union llreg_u{ 1802 uint32_t w32[2]; 1803 uint64_t w64; 1804 } llr; 1805 llr.w64 = acc; 1806 1807 #ifndef __ARMEB__ /* Little endian */ 1808 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 1809 #else /* Big endian */ 1810 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 1811 #endif 1812 1813 return(llr.w64); 1814 } 1815 1816 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) 1817 { 1818 uint32_t result; 1819 1820 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1821 return(result); 1822 } 1823 1824 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) 1825 { 1826 uint32_t result; 1827 1828 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1829 return(result); 1830 } 1831 1832 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) 1833 { 1834 uint32_t result; 1835 1836 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1837 return(result); 1838 } 1839 1840 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) 1841 { 1842 uint32_t result; 1843 1844 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1845 return(result); 1846 } 1847 1848 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) 1849 { 1850 union llreg_u{ 1851 uint32_t w32[2]; 1852 uint64_t w64; 1853 } llr; 1854 llr.w64 = acc; 1855 1856 #ifndef __ARMEB__ /* Little endian */ 1857 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 1858 #else /* Big endian */ 1859 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 1860 #endif 1861 1862 return(llr.w64); 1863 } 1864 1865 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) 1866 { 1867 union llreg_u{ 1868 uint32_t w32[2]; 1869 uint64_t w64; 1870 } llr; 1871 llr.w64 = acc; 1872 1873 #ifndef __ARMEB__ /* Little endian */ 1874 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 1875 #else /* Big endian */ 1876 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 1877 #endif 1878 1879 return(llr.w64); 1880 } 1881 1882 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) 1883 { 1884 uint32_t result; 1885 1886 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1887 return(result); 1888 } 1889 1890 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) 1891 { 1892 int32_t result; 1893 1894 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1895 return(result); 1896 } 1897 1898 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) 1899 { 1900 int32_t result; 1901 1902 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1903 return(result); 1904 } 1905 1906 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ 1907 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) 1908 1909 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ 1910 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) 1911 1912 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) 1913 1914 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) 1915 1916 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) 1917 { 1918 int32_t result; 1919 1920 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); 1921 return(result); 1922 } 1923 1924 #endif /* (__ARM_FEATURE_DSP == 1) */ 1925 /*@} end of group CMSIS_SIMD_intrinsics */ 1926 1927 1928 #endif /* __CMSIS_ARMCLANG_H */