core_armv81mml.h
1 /**************************************************************************//** 2 * @file core_armv81mml.h 3 * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File 4 * @version V1.4.2 5 * @date 13. October 2021 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2018-2021 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #elif defined ( __GNUC__ ) 30 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ 31 #endif 32 33 #ifndef __CORE_ARMV81MML_H_GENERIC 34 #define __CORE_ARMV81MML_H_GENERIC 35 36 #include <stdint.h> 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /** 43 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 44 CMSIS violates the following MISRA-C:2004 rules: 45 46 \li Required Rule 8.5, object/function definition in header file.<br> 47 Function definitions in header files are used to allow 'inlining'. 48 49 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 50 Unions are used for effective representation of core registers. 51 52 \li Advisory Rule 19.7, Function-like macro defined.<br> 53 Function-like macros are used to allow more efficient code. 54 */ 55 56 57 /******************************************************************************* 58 * CMSIS definitions 59 ******************************************************************************/ 60 /** 61 \ingroup Cortex_ARMV81MML 62 @{ 63 */ 64 65 #include "cmsis_version.h" 66 67 /* CMSIS ARMV81MML definitions */ 68 #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 69 #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 70 #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ 71 __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 72 73 #define __CORTEX_M (81U) /*!< Cortex-M Core */ 74 75 #if defined ( __CC_ARM ) 76 #error Legacy Arm Compiler does not support Armv8.1-M target architecture. 77 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 78 #if defined __ARM_FP 79 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 80 #define __FPU_USED 1U 81 #else 82 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 83 #define __FPU_USED 0U 84 #endif 85 #else 86 #define __FPU_USED 0U 87 #endif 88 89 #if defined(__ARM_FEATURE_DSP) 90 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 91 #define __DSP_USED 1U 92 #else 93 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 94 #define __DSP_USED 0U 95 #endif 96 #else 97 #define __DSP_USED 0U 98 #endif 99 100 #elif defined ( __GNUC__ ) 101 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 103 #define __FPU_USED 1U 104 #else 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 106 #define __FPU_USED 0U 107 #endif 108 #else 109 #define __FPU_USED 0U 110 #endif 111 112 #if defined(__ARM_FEATURE_DSP) 113 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 114 #define __DSP_USED 1U 115 #else 116 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 117 #define __DSP_USED 0U 118 #endif 119 #else 120 #define __DSP_USED 0U 121 #endif 122 123 #elif defined ( __ICCARM__ ) 124 #if defined __ARMVFP__ 125 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 126 #define __FPU_USED 1U 127 #else 128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 129 #define __FPU_USED 0U 130 #endif 131 #else 132 #define __FPU_USED 0U 133 #endif 134 135 #if defined(__ARM_FEATURE_DSP) 136 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 137 #define __DSP_USED 1U 138 #else 139 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 140 #define __DSP_USED 0U 141 #endif 142 #else 143 #define __DSP_USED 0U 144 #endif 145 146 #elif defined ( __TI_ARM__ ) 147 #if defined __TI_VFP_SUPPORT__ 148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 149 #define __FPU_USED 1U 150 #else 151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 152 #define __FPU_USED 0U 153 #endif 154 #else 155 #define __FPU_USED 0U 156 #endif 157 158 #elif defined ( __TASKING__ ) 159 #if defined __FPU_VFP__ 160 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 161 #define __FPU_USED 1U 162 #else 163 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 164 #define __FPU_USED 0U 165 #endif 166 #else 167 #define __FPU_USED 0U 168 #endif 169 170 #elif defined ( __CSMC__ ) 171 #if ( __CSMC__ & 0x400U) 172 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 173 #define __FPU_USED 1U 174 #else 175 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 176 #define __FPU_USED 0U 177 #endif 178 #else 179 #define __FPU_USED 0U 180 #endif 181 182 #endif 183 184 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 185 186 187 #ifdef __cplusplus 188 } 189 #endif 190 191 #endif /* __CORE_ARMV81MML_H_GENERIC */ 192 193 #ifndef __CMSIS_GENERIC 194 195 #ifndef __CORE_ARMV81MML_H_DEPENDANT 196 #define __CORE_ARMV81MML_H_DEPENDANT 197 198 #ifdef __cplusplus 199 extern "C" { 200 #endif 201 202 /* check device defines and use defaults */ 203 #if defined __CHECK_DEVICE_DEFINES 204 #ifndef __ARMv81MML_REV 205 #define __ARMv81MML_REV 0x0000U 206 #warning "__ARMv81MML_REV not defined in device header file; using default!" 207 #endif 208 209 #ifndef __FPU_PRESENT 210 #define __FPU_PRESENT 0U 211 #warning "__FPU_PRESENT not defined in device header file; using default!" 212 #endif 213 214 #if __FPU_PRESENT != 0U 215 #ifndef __FPU_DP 216 #define __FPU_DP 0U 217 #warning "__FPU_DP not defined in device header file; using default!" 218 #endif 219 #endif 220 221 #ifndef __MPU_PRESENT 222 #define __MPU_PRESENT 0U 223 #warning "__MPU_PRESENT not defined in device header file; using default!" 224 #endif 225 226 #ifndef __ICACHE_PRESENT 227 #define __ICACHE_PRESENT 0U 228 #warning "__ICACHE_PRESENT not defined in device header file; using default!" 229 #endif 230 231 #ifndef __DCACHE_PRESENT 232 #define __DCACHE_PRESENT 0U 233 #warning "__DCACHE_PRESENT not defined in device header file; using default!" 234 #endif 235 236 #ifndef __PMU_PRESENT 237 #define __PMU_PRESENT 0U 238 #warning "__PMU_PRESENT not defined in device header file; using default!" 239 #endif 240 241 #if __PMU_PRESENT != 0U 242 #ifndef __PMU_NUM_EVENTCNT 243 #define __PMU_NUM_EVENTCNT 2U 244 #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" 245 #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) 246 #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ 247 #endif 248 #endif 249 250 #ifndef __SAUREGION_PRESENT 251 #define __SAUREGION_PRESENT 0U 252 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 253 #endif 254 255 #ifndef __DSP_PRESENT 256 #define __DSP_PRESENT 0U 257 #warning "__DSP_PRESENT not defined in device header file; using default!" 258 #endif 259 260 #ifndef __VTOR_PRESENT 261 #define __VTOR_PRESENT 1U 262 #warning "__VTOR_PRESENT not defined in device header file; using default!" 263 #endif 264 265 #ifndef __NVIC_PRIO_BITS 266 #define __NVIC_PRIO_BITS 3U 267 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 268 #endif 269 270 #ifndef __Vendor_SysTickConfig 271 #define __Vendor_SysTickConfig 0U 272 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 273 #endif 274 #endif 275 276 /* IO definitions (access restrictions to peripheral registers) */ 277 /** 278 \defgroup CMSIS_glob_defs CMSIS Global Defines 279 280 <strong>IO Type Qualifiers</strong> are used 281 \li to specify the access to peripheral variables. 282 \li for automatic generation of peripheral register debug information. 283 */ 284 #ifdef __cplusplus 285 #define __I volatile /*!< Defines 'read only' permissions */ 286 #else 287 #define __I volatile const /*!< Defines 'read only' permissions */ 288 #endif 289 #define __O volatile /*!< Defines 'write only' permissions */ 290 #define __IO volatile /*!< Defines 'read / write' permissions */ 291 292 /* following defines should be used for structure members */ 293 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 294 #define __OM volatile /*! Defines 'write only' structure member permissions */ 295 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 296 297 /*@} end of group ARMv81MML */ 298 299 300 301 /******************************************************************************* 302 * Register Abstraction 303 Core Register contain: 304 - Core Register 305 - Core NVIC Register 306 - Core SCB Register 307 - Core SysTick Register 308 - Core Debug Register 309 - Core MPU Register 310 - Core SAU Register 311 - Core FPU Register 312 ******************************************************************************/ 313 /** 314 \defgroup CMSIS_core_register Defines and Type Definitions 315 \brief Type definitions and defines for Cortex-M processor based devices. 316 */ 317 318 /** 319 \ingroup CMSIS_core_register 320 \defgroup CMSIS_CORE Status and Control Registers 321 \brief Core Register type definitions. 322 @{ 323 */ 324 325 /** 326 \brief Union type to access the Application Program Status Register (APSR). 327 */ 328 typedef union 329 { 330 struct 331 { 332 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 333 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 334 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 335 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 336 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 337 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 338 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 339 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 340 } b; /*!< Structure used for bit access */ 341 uint32_t w; /*!< Type used for word access */ 342 } APSR_Type; 343 344 /* APSR Register Definitions */ 345 #define APSR_N_Pos 31U /*!< APSR: N Position */ 346 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 347 348 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 349 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 350 351 #define APSR_C_Pos 29U /*!< APSR: C Position */ 352 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 353 354 #define APSR_V_Pos 28U /*!< APSR: V Position */ 355 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 356 357 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 358 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 359 360 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 361 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 362 363 364 /** 365 \brief Union type to access the Interrupt Program Status Register (IPSR). 366 */ 367 typedef union 368 { 369 struct 370 { 371 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 372 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 373 } b; /*!< Structure used for bit access */ 374 uint32_t w; /*!< Type used for word access */ 375 } IPSR_Type; 376 377 /* IPSR Register Definitions */ 378 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 379 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 380 381 382 /** 383 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 384 */ 385 typedef union 386 { 387 struct 388 { 389 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 390 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 391 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 392 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 393 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 394 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 395 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 396 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 397 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 398 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 399 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 400 } b; /*!< Structure used for bit access */ 401 uint32_t w; /*!< Type used for word access */ 402 } xPSR_Type; 403 404 /* xPSR Register Definitions */ 405 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 406 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 407 408 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 409 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 410 411 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 412 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 413 414 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 415 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 416 417 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 418 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 419 420 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ 421 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ 422 423 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 424 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 425 426 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 427 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 428 429 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 430 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 431 432 433 /** 434 \brief Union type to access the Control Registers (CONTROL). 435 */ 436 typedef union 437 { 438 struct 439 { 440 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 441 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 442 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ 443 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ 444 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ 445 } b; /*!< Structure used for bit access */ 446 uint32_t w; /*!< Type used for word access */ 447 } CONTROL_Type; 448 449 /* CONTROL Register Definitions */ 450 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ 451 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ 452 453 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 454 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 455 456 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 457 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 458 459 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 460 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 461 462 /*@} end of group CMSIS_CORE */ 463 464 465 /** 466 \ingroup CMSIS_core_register 467 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 468 \brief Type definitions for the NVIC Registers 469 @{ 470 */ 471 472 /** 473 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 474 */ 475 typedef struct 476 { 477 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 478 uint32_t RESERVED0[16U]; 479 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 480 uint32_t RSERVED1[16U]; 481 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 482 uint32_t RESERVED2[16U]; 483 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 484 uint32_t RESERVED3[16U]; 485 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 486 uint32_t RESERVED4[16U]; 487 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 488 uint32_t RESERVED5[16U]; 489 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 490 uint32_t RESERVED6[580U]; 491 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 492 } NVIC_Type; 493 494 /* Software Triggered Interrupt Register Definitions */ 495 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 496 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 497 498 /*@} end of group CMSIS_NVIC */ 499 500 501 /** 502 \ingroup CMSIS_core_register 503 \defgroup CMSIS_SCB System Control Block (SCB) 504 \brief Type definitions for the System Control Block Registers 505 @{ 506 */ 507 508 /** 509 \brief Structure type to access the System Control Block (SCB). 510 */ 511 typedef struct 512 { 513 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 514 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 515 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 516 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 517 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 518 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 519 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 520 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 521 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 522 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 523 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 524 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 525 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 526 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 527 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 528 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 529 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 530 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 531 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 532 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 533 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 534 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 535 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 536 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 537 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ 538 uint32_t RESERVED7[21U]; 539 __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ 540 __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ 541 uint32_t RESERVED3[69U]; 542 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 543 __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ 544 uint32_t RESERVED4[14U]; 545 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 546 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 547 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ 548 uint32_t RESERVED5[1U]; 549 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 550 uint32_t RESERVED6[1U]; 551 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 552 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 553 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 554 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 555 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 556 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 557 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 558 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 559 __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ 560 } SCB_Type; 561 562 /* SCB CPUID Register Definitions */ 563 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 564 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 565 566 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 567 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 568 569 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 570 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 571 572 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 573 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 574 575 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 576 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 577 578 /* SCB Interrupt Control State Register Definitions */ 579 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 580 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 581 582 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 583 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 584 585 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 586 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 587 588 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 589 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 590 591 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 592 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 593 594 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 595 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 596 597 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 598 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 599 600 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 601 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 602 603 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 604 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 605 606 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 607 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 608 609 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 610 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 611 612 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 613 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 614 615 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 616 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 617 618 /* SCB Vector Table Offset Register Definitions */ 619 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 620 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 621 622 /* SCB Application Interrupt and Reset Control Register Definitions */ 623 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 624 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 625 626 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 627 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 628 629 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 630 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 631 632 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 633 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 634 635 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 636 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 637 638 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 639 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 640 641 #define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ 642 #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ 643 644 #define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ 645 #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ 646 647 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 648 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 649 650 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 651 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 652 653 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 654 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 655 656 /* SCB System Control Register Definitions */ 657 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 658 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 659 660 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 661 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 662 663 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 664 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 665 666 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 667 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 668 669 /* SCB Configuration Control Register Definitions */ 670 #define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ 671 #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ 672 673 #define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ 674 #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ 675 676 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 677 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 678 679 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 680 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 681 682 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 683 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 684 685 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 686 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 687 688 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 689 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 690 691 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 692 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 693 694 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 695 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 696 697 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 698 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 699 700 /* SCB System Handler Control and State Register Definitions */ 701 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 702 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 703 704 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ 705 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ 706 707 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ 708 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ 709 710 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 711 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 712 713 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 714 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 715 716 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 717 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 718 719 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 720 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 721 722 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 723 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 724 725 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 726 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 727 728 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 729 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 730 731 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 732 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 733 734 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 735 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 736 737 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 738 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 739 740 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 741 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 742 743 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 744 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 745 746 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ 747 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ 748 749 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 750 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 751 752 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 753 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 754 755 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 756 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 757 758 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 759 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 760 761 /* SCB Configurable Fault Status Register Definitions */ 762 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 763 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 764 765 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 766 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 767 768 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 769 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 770 771 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 772 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 773 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 774 775 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 776 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 777 778 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 779 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 780 781 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 782 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 783 784 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 785 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 786 787 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 788 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 789 790 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 791 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 792 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 793 794 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 795 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 796 797 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 798 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 799 800 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 801 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 802 803 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 804 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 805 806 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 807 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 808 809 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 810 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 811 812 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 813 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 814 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 815 816 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 817 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 818 819 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ 820 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ 821 822 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 823 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 824 825 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 826 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 827 828 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 829 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 830 831 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 832 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 833 834 /* SCB Hard Fault Status Register Definitions */ 835 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 836 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 837 838 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 839 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 840 841 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 842 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 843 844 /* SCB Debug Fault Status Register Definitions */ 845 #define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ 846 #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ 847 848 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 849 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 850 851 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 852 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 853 854 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 855 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 856 857 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 858 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 859 860 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 861 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 862 863 /* SCB Non-Secure Access Control Register Definitions */ 864 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 865 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 866 867 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 868 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 869 870 #define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ 871 #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ 872 873 #define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ 874 #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ 875 876 #define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ 877 #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ 878 879 #define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ 880 #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ 881 882 #define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ 883 #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ 884 885 #define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ 886 #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ 887 888 #define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ 889 #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ 890 891 #define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ 892 #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ 893 894 /* SCB Debug Feature Register 0 Definitions */ 895 #define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ 896 #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ 897 898 #define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ 899 #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ 900 901 /* SCB Cache Level ID Register Definitions */ 902 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ 903 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 904 905 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ 906 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ 907 908 /* SCB Cache Type Register Definitions */ 909 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ 910 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 911 912 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ 913 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 914 915 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ 916 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 917 918 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ 919 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 920 921 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ 922 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 923 924 /* SCB Cache Size ID Register Definitions */ 925 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 926 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 927 928 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 929 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 930 931 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 932 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 933 934 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 935 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 936 937 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ 938 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 939 940 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ 941 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 942 943 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ 944 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 945 946 /* SCB Cache Size Selection Register Definitions */ 947 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ 948 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 949 950 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ 951 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 952 953 /* SCB Software Triggered Interrupt Register Definitions */ 954 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ 955 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 956 957 /* SCB RAS Fault Status Register Definitions */ 958 #define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ 959 #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ 960 961 #define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ 962 #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ 963 964 #define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ 965 #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ 966 967 /* SCB D-Cache Invalidate by Set-way Register Definitions */ 968 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ 969 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ 970 971 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ 972 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ 973 974 /* SCB D-Cache Clean by Set-way Register Definitions */ 975 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ 976 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ 977 978 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ 979 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ 980 981 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 982 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ 983 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ 984 985 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ 986 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ 987 988 /*@} end of group CMSIS_SCB */ 989 990 991 /** 992 \ingroup CMSIS_core_register 993 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 994 \brief Type definitions for the System Control and ID Register not in the SCB 995 @{ 996 */ 997 998 /** 999 \brief Structure type to access the System Control and ID Register not in the SCB. 1000 */ 1001 typedef struct 1002 { 1003 uint32_t RESERVED0[1U]; 1004 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 1005 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 1006 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ 1007 } SCnSCB_Type; 1008 1009 /* Interrupt Controller Type Register Definitions */ 1010 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 1011 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 1012 1013 /*@} end of group CMSIS_SCnotSCB */ 1014 1015 1016 /** 1017 \ingroup CMSIS_core_register 1018 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 1019 \brief Type definitions for the System Timer Registers. 1020 @{ 1021 */ 1022 1023 /** 1024 \brief Structure type to access the System Timer (SysTick). 1025 */ 1026 typedef struct 1027 { 1028 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 1029 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 1030 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 1031 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 1032 } SysTick_Type; 1033 1034 /* SysTick Control / Status Register Definitions */ 1035 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 1036 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 1037 1038 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 1039 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 1040 1041 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 1042 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 1043 1044 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 1045 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 1046 1047 /* SysTick Reload Register Definitions */ 1048 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 1049 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 1050 1051 /* SysTick Current Register Definitions */ 1052 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 1053 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 1054 1055 /* SysTick Calibration Register Definitions */ 1056 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 1057 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 1058 1059 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 1060 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 1061 1062 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 1063 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 1064 1065 /*@} end of group CMSIS_SysTick */ 1066 1067 1068 /** 1069 \ingroup CMSIS_core_register 1070 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 1071 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 1072 @{ 1073 */ 1074 1075 /** 1076 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 1077 */ 1078 typedef struct 1079 { 1080 __OM union 1081 { 1082 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 1083 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 1084 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 1085 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 1086 uint32_t RESERVED0[864U]; 1087 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 1088 uint32_t RESERVED1[15U]; 1089 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 1090 uint32_t RESERVED2[15U]; 1091 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 1092 uint32_t RESERVED3[32U]; 1093 uint32_t RESERVED4[43U]; 1094 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 1095 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 1096 uint32_t RESERVED5[1U]; 1097 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ 1098 uint32_t RESERVED6[3U]; 1099 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ 1100 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 1101 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 1102 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 1103 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 1104 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 1105 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 1106 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 1107 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 1108 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 1109 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 1110 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 1111 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 1112 } ITM_Type; 1113 1114 /* ITM Stimulus Port Register Definitions */ 1115 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ 1116 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ 1117 1118 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ 1119 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ 1120 1121 /* ITM Trace Privilege Register Definitions */ 1122 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1123 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 1124 1125 /* ITM Trace Control Register Definitions */ 1126 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 1127 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 1128 1129 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ 1130 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ 1131 1132 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 1133 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 1134 1135 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ 1136 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ 1137 1138 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ 1139 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ 1140 1141 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 1142 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 1143 1144 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 1145 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 1146 1147 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 1148 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 1149 1150 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 1151 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 1152 1153 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 1154 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 1155 1156 /* ITM Lock Status Register Definitions */ 1157 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 1158 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 1159 1160 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 1161 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 1162 1163 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 1164 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 1165 1166 /*@}*/ /* end of group CMSIS_ITM */ 1167 1168 1169 /** 1170 \ingroup CMSIS_core_register 1171 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 1172 \brief Type definitions for the Data Watchpoint and Trace (DWT) 1173 @{ 1174 */ 1175 1176 /** 1177 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 1178 */ 1179 typedef struct 1180 { 1181 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 1182 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 1183 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 1184 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 1185 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 1186 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 1187 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 1188 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 1189 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 1190 uint32_t RESERVED1[1U]; 1191 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 1192 uint32_t RESERVED2[1U]; 1193 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 1194 uint32_t RESERVED3[1U]; 1195 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 1196 uint32_t RESERVED4[1U]; 1197 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 1198 uint32_t RESERVED5[1U]; 1199 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 1200 uint32_t RESERVED6[1U]; 1201 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 1202 uint32_t RESERVED7[1U]; 1203 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 1204 uint32_t RESERVED8[1U]; 1205 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 1206 uint32_t RESERVED9[1U]; 1207 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 1208 uint32_t RESERVED10[1U]; 1209 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 1210 uint32_t RESERVED11[1U]; 1211 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 1212 uint32_t RESERVED12[1U]; 1213 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 1214 uint32_t RESERVED13[1U]; 1215 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 1216 uint32_t RESERVED14[1U]; 1217 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 1218 uint32_t RESERVED15[1U]; 1219 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 1220 uint32_t RESERVED16[1U]; 1221 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 1222 uint32_t RESERVED17[1U]; 1223 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 1224 uint32_t RESERVED18[1U]; 1225 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 1226 uint32_t RESERVED19[1U]; 1227 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 1228 uint32_t RESERVED20[1U]; 1229 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 1230 uint32_t RESERVED21[1U]; 1231 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 1232 uint32_t RESERVED22[1U]; 1233 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 1234 uint32_t RESERVED23[1U]; 1235 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 1236 uint32_t RESERVED24[1U]; 1237 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 1238 uint32_t RESERVED25[1U]; 1239 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 1240 uint32_t RESERVED26[1U]; 1241 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 1242 uint32_t RESERVED27[1U]; 1243 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 1244 uint32_t RESERVED28[1U]; 1245 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 1246 uint32_t RESERVED29[1U]; 1247 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 1248 uint32_t RESERVED30[1U]; 1249 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 1250 uint32_t RESERVED31[1U]; 1251 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 1252 uint32_t RESERVED32[934U]; 1253 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 1254 uint32_t RESERVED33[1U]; 1255 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ 1256 } DWT_Type; 1257 1258 /* DWT Control Register Definitions */ 1259 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 1260 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 1261 1262 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 1263 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 1264 1265 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 1266 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 1267 1268 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 1269 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 1270 1271 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 1272 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 1273 1274 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ 1275 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ 1276 1277 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 1278 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 1279 1280 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 1281 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 1282 1283 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 1284 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 1285 1286 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 1287 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 1288 1289 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 1290 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 1291 1292 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 1293 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 1294 1295 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 1296 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 1297 1298 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 1299 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 1300 1301 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 1302 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 1303 1304 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 1305 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 1306 1307 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 1308 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 1309 1310 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 1311 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 1312 1313 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 1314 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 1315 1316 /* DWT CPI Count Register Definitions */ 1317 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 1318 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 1319 1320 /* DWT Exception Overhead Count Register Definitions */ 1321 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 1322 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 1323 1324 /* DWT Sleep Count Register Definitions */ 1325 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 1326 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 1327 1328 /* DWT LSU Count Register Definitions */ 1329 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 1330 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 1331 1332 /* DWT Folded-instruction Count Register Definitions */ 1333 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 1334 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 1335 1336 /* DWT Comparator Function Register Definitions */ 1337 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 1338 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 1339 1340 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 1341 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 1342 1343 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 1344 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 1345 1346 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 1347 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 1348 1349 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 1350 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 1351 1352 /*@}*/ /* end of group CMSIS_DWT */ 1353 1354 1355 /** 1356 \ingroup CMSIS_core_register 1357 \defgroup CMSIS_TPI Trace Port Interface (TPI) 1358 \brief Type definitions for the Trace Port Interface (TPI) 1359 @{ 1360 */ 1361 1362 /** 1363 \brief Structure type to access the Trace Port Interface Register (TPI). 1364 */ 1365 typedef struct 1366 { 1367 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ 1368 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ 1369 uint32_t RESERVED0[2U]; 1370 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 1371 uint32_t RESERVED1[55U]; 1372 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 1373 uint32_t RESERVED2[131U]; 1374 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 1375 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 1376 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 1377 uint32_t RESERVED3[809U]; 1378 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ 1379 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ 1380 uint32_t RESERVED4[4U]; 1381 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ 1382 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ 1383 } TPI_Type; 1384 1385 /* TPI Asynchronous Clock Prescaler Register Definitions */ 1386 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ 1387 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ 1388 1389 /* TPI Selected Pin Protocol Register Definitions */ 1390 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 1391 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 1392 1393 /* TPI Formatter and Flush Status Register Definitions */ 1394 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 1395 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 1396 1397 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 1398 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 1399 1400 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 1401 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 1402 1403 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 1404 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 1405 1406 /* TPI Formatter and Flush Control Register Definitions */ 1407 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 1408 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 1409 1410 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 1411 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 1412 1413 #define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ 1414 #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ 1415 1416 /* TPI Periodic Synchronization Control Register Definitions */ 1417 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ 1418 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ 1419 1420 /* TPI Software Lock Status Register Definitions */ 1421 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ 1422 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ 1423 1424 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ 1425 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ 1426 1427 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ 1428 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ 1429 1430 /* TPI DEVID Register Definitions */ 1431 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 1432 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1433 1434 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 1435 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1436 1437 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 1438 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1439 1440 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ 1441 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ 1442 1443 /* TPI DEVTYPE Register Definitions */ 1444 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 1445 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 1446 1447 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 1448 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1449 1450 /*@}*/ /* end of group CMSIS_TPI */ 1451 1452 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) 1453 /** 1454 \ingroup CMSIS_core_register 1455 \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) 1456 \brief Type definitions for the Performance Monitoring Unit (PMU) 1457 @{ 1458 */ 1459 1460 /** 1461 \brief Structure type to access the Performance Monitoring Unit (PMU). 1462 */ 1463 typedef struct 1464 { 1465 __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ 1466 #if __PMU_NUM_EVENTCNT<31 1467 uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; 1468 #endif 1469 __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ 1470 uint32_t RESERVED1[224]; 1471 __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ 1472 #if __PMU_NUM_EVENTCNT<31 1473 uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; 1474 #endif 1475 __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ 1476 uint32_t RESERVED3[480]; 1477 __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ 1478 uint32_t RESERVED4[7]; 1479 __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ 1480 uint32_t RESERVED5[7]; 1481 __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ 1482 uint32_t RESERVED6[7]; 1483 __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ 1484 uint32_t RESERVED7[7]; 1485 __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ 1486 uint32_t RESERVED8[7]; 1487 __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ 1488 uint32_t RESERVED9[7]; 1489 __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ 1490 uint32_t RESERVED10[79]; 1491 __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ 1492 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ 1493 uint32_t RESERVED11[108]; 1494 __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ 1495 __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ 1496 uint32_t RESERVED12[3]; 1497 __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ 1498 __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ 1499 uint32_t RESERVED13[3]; 1500 __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ 1501 __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ 1502 __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ 1503 __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ 1504 __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ 1505 __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ 1506 __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ 1507 __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ 1508 } PMU_Type; 1509 1510 /** \brief PMU Event Counter Registers (0-30) Definitions */ 1511 1512 #define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ 1513 #define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ 1514 1515 /** \brief PMU Event Type and Filter Registers (0-30) Definitions */ 1516 1517 #define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ 1518 #define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ 1519 1520 /** \brief PMU Count Enable Set Register Definitions */ 1521 1522 #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ 1523 #define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ 1524 1525 #define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ 1526 #define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ 1527 1528 #define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ 1529 #define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ 1530 1531 #define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ 1532 #define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ 1533 1534 #define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ 1535 #define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ 1536 1537 #define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ 1538 #define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ 1539 1540 #define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ 1541 #define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ 1542 1543 #define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ 1544 #define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ 1545 1546 #define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ 1547 #define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ 1548 1549 #define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ 1550 #define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ 1551 1552 #define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ 1553 #define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ 1554 1555 #define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ 1556 #define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ 1557 1558 #define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ 1559 #define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ 1560 1561 #define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ 1562 #define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ 1563 1564 #define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ 1565 #define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ 1566 1567 #define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ 1568 #define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ 1569 1570 #define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ 1571 #define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ 1572 1573 #define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ 1574 #define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ 1575 1576 #define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ 1577 #define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ 1578 1579 #define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ 1580 #define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ 1581 1582 #define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ 1583 #define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ 1584 1585 #define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ 1586 #define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ 1587 1588 #define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ 1589 #define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ 1590 1591 #define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ 1592 #define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ 1593 1594 #define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ 1595 #define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ 1596 1597 #define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ 1598 #define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ 1599 1600 #define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ 1601 #define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ 1602 1603 #define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ 1604 #define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ 1605 1606 #define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ 1607 #define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ 1608 1609 #define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ 1610 #define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ 1611 1612 #define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ 1613 #define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ 1614 1615 #define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ 1616 #define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ 1617 1618 /** \brief PMU Count Enable Clear Register Definitions */ 1619 1620 #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ 1621 #define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ 1622 1623 #define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ 1624 #define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ 1625 1626 #define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ 1627 #define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ 1628 1629 #define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ 1630 #define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ 1631 1632 #define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ 1633 #define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ 1634 1635 #define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ 1636 #define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ 1637 1638 #define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ 1639 #define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ 1640 1641 #define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ 1642 #define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ 1643 1644 #define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ 1645 #define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ 1646 1647 #define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ 1648 #define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ 1649 1650 #define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ 1651 #define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ 1652 1653 #define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ 1654 #define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ 1655 1656 #define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ 1657 #define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ 1658 1659 #define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ 1660 #define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ 1661 1662 #define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ 1663 #define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ 1664 1665 #define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ 1666 #define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ 1667 1668 #define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ 1669 #define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ 1670 1671 #define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ 1672 #define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ 1673 1674 #define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ 1675 #define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ 1676 1677 #define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ 1678 #define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ 1679 1680 #define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ 1681 #define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ 1682 1683 #define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ 1684 #define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ 1685 1686 #define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ 1687 #define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ 1688 1689 #define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ 1690 #define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ 1691 1692 #define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ 1693 #define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ 1694 1695 #define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ 1696 #define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ 1697 1698 #define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ 1699 #define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ 1700 1701 #define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ 1702 #define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ 1703 1704 #define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ 1705 #define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ 1706 1707 #define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ 1708 #define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ 1709 1710 #define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ 1711 #define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ 1712 1713 #define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ 1714 #define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ 1715 1716 /** \brief PMU Interrupt Enable Set Register Definitions */ 1717 1718 #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ 1719 #define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ 1720 1721 #define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ 1722 #define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ 1723 1724 #define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ 1725 #define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ 1726 1727 #define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ 1728 #define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ 1729 1730 #define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ 1731 #define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ 1732 1733 #define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ 1734 #define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ 1735 1736 #define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ 1737 #define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ 1738 1739 #define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ 1740 #define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ 1741 1742 #define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ 1743 #define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ 1744 1745 #define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ 1746 #define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ 1747 1748 #define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ 1749 #define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ 1750 1751 #define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ 1752 #define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ 1753 1754 #define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ 1755 #define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ 1756 1757 #define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ 1758 #define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ 1759 1760 #define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ 1761 #define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ 1762 1763 #define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ 1764 #define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ 1765 1766 #define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ 1767 #define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ 1768 1769 #define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ 1770 #define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ 1771 1772 #define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ 1773 #define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ 1774 1775 #define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ 1776 #define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ 1777 1778 #define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ 1779 #define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ 1780 1781 #define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ 1782 #define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ 1783 1784 #define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ 1785 #define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ 1786 1787 #define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ 1788 #define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ 1789 1790 #define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ 1791 #define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ 1792 1793 #define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ 1794 #define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ 1795 1796 #define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ 1797 #define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ 1798 1799 #define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ 1800 #define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ 1801 1802 #define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ 1803 #define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ 1804 1805 #define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ 1806 #define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ 1807 1808 #define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ 1809 #define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ 1810 1811 #define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ 1812 #define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ 1813 1814 /** \brief PMU Interrupt Enable Clear Register Definitions */ 1815 1816 #define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ 1817 #define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ 1818 1819 #define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ 1820 #define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ 1821 1822 #define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ 1823 #define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ 1824 1825 #define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ 1826 #define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ 1827 1828 #define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ 1829 #define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ 1830 1831 #define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ 1832 #define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ 1833 1834 #define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ 1835 #define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ 1836 1837 #define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ 1838 #define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ 1839 1840 #define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ 1841 #define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ 1842 1843 #define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ 1844 #define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ 1845 1846 #define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ 1847 #define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ 1848 1849 #define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ 1850 #define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ 1851 1852 #define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ 1853 #define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ 1854 1855 #define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ 1856 #define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ 1857 1858 #define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ 1859 #define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ 1860 1861 #define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ 1862 #define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ 1863 1864 #define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ 1865 #define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ 1866 1867 #define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ 1868 #define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ 1869 1870 #define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ 1871 #define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ 1872 1873 #define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ 1874 #define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ 1875 1876 #define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ 1877 #define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ 1878 1879 #define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ 1880 #define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ 1881 1882 #define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ 1883 #define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ 1884 1885 #define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ 1886 #define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ 1887 1888 #define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ 1889 #define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ 1890 1891 #define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ 1892 #define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ 1893 1894 #define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ 1895 #define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ 1896 1897 #define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ 1898 #define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ 1899 1900 #define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ 1901 #define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ 1902 1903 #define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ 1904 #define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ 1905 1906 #define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ 1907 #define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ 1908 1909 #define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ 1910 #define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ 1911 1912 /** \brief PMU Overflow Flag Status Set Register Definitions */ 1913 1914 #define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ 1915 #define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ 1916 1917 #define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ 1918 #define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ 1919 1920 #define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ 1921 #define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ 1922 1923 #define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ 1924 #define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ 1925 1926 #define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ 1927 #define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ 1928 1929 #define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ 1930 #define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ 1931 1932 #define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ 1933 #define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ 1934 1935 #define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ 1936 #define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ 1937 1938 #define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ 1939 #define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ 1940 1941 #define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ 1942 #define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ 1943 1944 #define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ 1945 #define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ 1946 1947 #define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ 1948 #define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ 1949 1950 #define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ 1951 #define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ 1952 1953 #define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ 1954 #define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ 1955 1956 #define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ 1957 #define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ 1958 1959 #define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ 1960 #define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ 1961 1962 #define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ 1963 #define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ 1964 1965 #define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ 1966 #define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ 1967 1968 #define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ 1969 #define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ 1970 1971 #define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ 1972 #define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ 1973 1974 #define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ 1975 #define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ 1976 1977 #define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ 1978 #define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ 1979 1980 #define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ 1981 #define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ 1982 1983 #define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ 1984 #define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ 1985 1986 #define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ 1987 #define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ 1988 1989 #define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ 1990 #define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ 1991 1992 #define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ 1993 #define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ 1994 1995 #define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ 1996 #define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ 1997 1998 #define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ 1999 #define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ 2000 2001 #define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ 2002 #define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ 2003 2004 #define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ 2005 #define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ 2006 2007 #define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ 2008 #define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ 2009 2010 /** \brief PMU Overflow Flag Status Clear Register Definitions */ 2011 2012 #define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ 2013 #define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ 2014 2015 #define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ 2016 #define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ 2017 2018 #define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ 2019 #define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ 2020 2021 #define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ 2022 #define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ 2023 2024 #define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ 2025 #define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ 2026 2027 #define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ 2028 #define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ 2029 2030 #define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ 2031 #define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ 2032 2033 #define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ 2034 #define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ 2035 2036 #define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ 2037 #define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ 2038 2039 #define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ 2040 #define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ 2041 2042 #define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ 2043 #define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ 2044 2045 #define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ 2046 #define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ 2047 2048 #define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ 2049 #define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ 2050 2051 #define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ 2052 #define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ 2053 2054 #define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ 2055 #define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ 2056 2057 #define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ 2058 #define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ 2059 2060 #define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ 2061 #define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ 2062 2063 #define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ 2064 #define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ 2065 2066 #define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ 2067 #define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ 2068 2069 #define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ 2070 #define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ 2071 2072 #define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ 2073 #define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ 2074 2075 #define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ 2076 #define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ 2077 2078 #define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ 2079 #define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ 2080 2081 #define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ 2082 #define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ 2083 2084 #define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ 2085 #define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ 2086 2087 #define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ 2088 #define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ 2089 2090 #define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ 2091 #define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ 2092 2093 #define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ 2094 #define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ 2095 2096 #define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ 2097 #define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ 2098 2099 #define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ 2100 #define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ 2101 2102 #define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ 2103 #define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ 2104 2105 #define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ 2106 #define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ 2107 2108 /** \brief PMU Software Increment Counter */ 2109 2110 #define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ 2111 #define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ 2112 2113 #define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ 2114 #define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ 2115 2116 #define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ 2117 #define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ 2118 2119 #define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ 2120 #define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ 2121 2122 #define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ 2123 #define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ 2124 2125 #define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ 2126 #define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ 2127 2128 #define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ 2129 #define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ 2130 2131 #define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ 2132 #define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ 2133 2134 #define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ 2135 #define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ 2136 2137 #define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ 2138 #define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ 2139 2140 #define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ 2141 #define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ 2142 2143 #define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ 2144 #define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ 2145 2146 #define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ 2147 #define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ 2148 2149 #define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ 2150 #define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ 2151 2152 #define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ 2153 #define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ 2154 2155 #define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ 2156 #define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ 2157 2158 #define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ 2159 #define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ 2160 2161 #define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ 2162 #define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ 2163 2164 #define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ 2165 #define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ 2166 2167 #define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ 2168 #define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ 2169 2170 #define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ 2171 #define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ 2172 2173 #define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ 2174 #define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ 2175 2176 #define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ 2177 #define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ 2178 2179 #define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ 2180 #define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ 2181 2182 #define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ 2183 #define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ 2184 2185 #define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ 2186 #define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ 2187 2188 #define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ 2189 #define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ 2190 2191 #define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ 2192 #define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ 2193 2194 #define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ 2195 #define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ 2196 2197 #define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ 2198 #define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ 2199 2200 #define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ 2201 #define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ 2202 2203 /** \brief PMU Control Register Definitions */ 2204 2205 #define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ 2206 #define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ 2207 2208 #define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ 2209 #define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ 2210 2211 #define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ 2212 #define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ 2213 2214 #define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ 2215 #define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ 2216 2217 #define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ 2218 #define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ 2219 2220 #define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ 2221 #define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ 2222 2223 /** \brief PMU Type Register Definitions */ 2224 2225 #define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ 2226 #define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ 2227 2228 #define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ 2229 #define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ 2230 2231 #define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ 2232 #define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ 2233 2234 #define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ 2235 #define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ 2236 2237 #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ 2238 #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ 2239 2240 /** \brief PMU Authentication Status Register Definitions */ 2241 2242 #define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ 2243 #define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ 2244 2245 #define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ 2246 #define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ 2247 2248 #define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ 2249 #define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ 2250 2251 #define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ 2252 #define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ 2253 2254 #define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ 2255 #define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ 2256 2257 #define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ 2258 #define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ 2259 2260 #define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ 2261 #define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ 2262 2263 #define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ 2264 #define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ 2265 2266 /*@} end of group CMSIS_PMU */ 2267 #endif 2268 2269 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 2270 /** 2271 \ingroup CMSIS_core_register 2272 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 2273 \brief Type definitions for the Memory Protection Unit (MPU) 2274 @{ 2275 */ 2276 2277 /** 2278 \brief Structure type to access the Memory Protection Unit (MPU). 2279 */ 2280 typedef struct 2281 { 2282 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 2283 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 2284 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 2285 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 2286 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 2287 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ 2288 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ 2289 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ 2290 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ 2291 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ 2292 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ 2293 uint32_t RESERVED0[1]; 2294 union { 2295 __IOM uint32_t MAIR[2]; 2296 struct { 2297 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 2298 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 2299 }; 2300 }; 2301 } MPU_Type; 2302 2303 #define MPU_TYPE_RALIASES 4U 2304 2305 /* MPU Type Register Definitions */ 2306 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 2307 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 2308 2309 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 2310 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 2311 2312 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 2313 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 2314 2315 /* MPU Control Register Definitions */ 2316 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 2317 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 2318 2319 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 2320 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 2321 2322 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 2323 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 2324 2325 /* MPU Region Number Register Definitions */ 2326 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 2327 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 2328 2329 /* MPU Region Base Address Register Definitions */ 2330 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 2331 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 2332 2333 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 2334 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 2335 2336 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 2337 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 2338 2339 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 2340 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 2341 2342 /* MPU Region Limit Address Register Definitions */ 2343 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 2344 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 2345 2346 #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ 2347 #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ 2348 2349 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 2350 #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 2351 2352 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ 2353 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ 2354 2355 /* MPU Memory Attribute Indirection Register 0 Definitions */ 2356 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 2357 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 2358 2359 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 2360 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 2361 2362 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 2363 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 2364 2365 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 2366 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 2367 2368 /* MPU Memory Attribute Indirection Register 1 Definitions */ 2369 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 2370 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 2371 2372 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 2373 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 2374 2375 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 2376 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 2377 2378 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 2379 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 2380 2381 /*@} end of group CMSIS_MPU */ 2382 #endif 2383 2384 2385 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2386 /** 2387 \ingroup CMSIS_core_register 2388 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 2389 \brief Type definitions for the Security Attribution Unit (SAU) 2390 @{ 2391 */ 2392 2393 /** 2394 \brief Structure type to access the Security Attribution Unit (SAU). 2395 */ 2396 typedef struct 2397 { 2398 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 2399 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 2400 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 2401 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 2402 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 2403 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 2404 #else 2405 uint32_t RESERVED0[3]; 2406 #endif 2407 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ 2408 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ 2409 } SAU_Type; 2410 2411 /* SAU Control Register Definitions */ 2412 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 2413 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 2414 2415 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 2416 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 2417 2418 /* SAU Type Register Definitions */ 2419 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 2420 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 2421 2422 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 2423 /* SAU Region Number Register Definitions */ 2424 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 2425 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 2426 2427 /* SAU Region Base Address Register Definitions */ 2428 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 2429 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 2430 2431 /* SAU Region Limit Address Register Definitions */ 2432 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 2433 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 2434 2435 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 2436 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 2437 2438 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 2439 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 2440 2441 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 2442 2443 /* Secure Fault Status Register Definitions */ 2444 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ 2445 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ 2446 2447 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ 2448 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ 2449 2450 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ 2451 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ 2452 2453 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ 2454 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ 2455 2456 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ 2457 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ 2458 2459 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ 2460 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ 2461 2462 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ 2463 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ 2464 2465 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ 2466 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ 2467 2468 /*@} end of group CMSIS_SAU */ 2469 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 2470 2471 2472 /** 2473 \ingroup CMSIS_core_register 2474 \defgroup CMSIS_FPU Floating Point Unit (FPU) 2475 \brief Type definitions for the Floating Point Unit (FPU) 2476 @{ 2477 */ 2478 2479 /** 2480 \brief Structure type to access the Floating Point Unit (FPU). 2481 */ 2482 typedef struct 2483 { 2484 uint32_t RESERVED0[1U]; 2485 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 2486 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 2487 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 2488 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ 2489 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ 2490 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ 2491 } FPU_Type; 2492 2493 /* Floating-Point Context Control Register Definitions */ 2494 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 2495 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 2496 2497 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 2498 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 2499 2500 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 2501 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 2502 2503 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 2504 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 2505 2506 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ 2507 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ 2508 2509 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ 2510 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ 2511 2512 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ 2513 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ 2514 2515 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ 2516 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ 2517 2518 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 2519 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 2520 2521 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ 2522 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ 2523 2524 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 2525 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 2526 2527 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 2528 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 2529 2530 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 2531 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 2532 2533 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 2534 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 2535 2536 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ 2537 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ 2538 2539 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 2540 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 2541 2542 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 2543 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 2544 2545 /* Floating-Point Context Address Register Definitions */ 2546 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 2547 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 2548 2549 /* Floating-Point Default Status Control Register Definitions */ 2550 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 2551 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 2552 2553 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 2554 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 2555 2556 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 2557 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 2558 2559 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 2560 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 2561 2562 #define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ 2563 #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ 2564 2565 #define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ 2566 #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ 2567 2568 /* Media and VFP Feature Register 0 Definitions */ 2569 #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ 2570 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ 2571 2572 #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ 2573 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ 2574 2575 #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ 2576 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ 2577 2578 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ 2579 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ 2580 2581 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ 2582 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ 2583 2584 #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ 2585 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ 2586 2587 /* Media and VFP Feature Register 1 Definitions */ 2588 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ 2589 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ 2590 2591 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ 2592 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ 2593 2594 #define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ 2595 #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ 2596 2597 #define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ 2598 #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ 2599 2600 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ 2601 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ 2602 2603 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ 2604 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ 2605 2606 /* Media and VFP Feature Register 2 Definitions */ 2607 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ 2608 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ 2609 2610 /*@} end of group CMSIS_FPU */ 2611 2612 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ 2613 /** 2614 \ingroup CMSIS_core_register 2615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 2616 \brief Type definitions for the Core Debug Registers 2617 @{ 2618 */ 2619 2620 /** 2621 \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). 2622 */ 2623 typedef struct 2624 { 2625 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 2626 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 2627 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 2628 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 2629 __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ 2630 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 2631 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 2632 } CoreDebug_Type; 2633 2634 /* Debug Halting Control and Status Register Definitions */ 2635 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ 2636 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ 2637 2638 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ 2639 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ 2640 2641 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ 2642 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ 2643 2644 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ 2645 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ 2646 2647 #define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ 2648 #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ 2649 2650 #define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ 2651 #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ 2652 2653 #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ 2654 #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ 2655 2656 #define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ 2657 #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ 2658 2659 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ 2660 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ 2661 2662 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ 2663 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ 2664 2665 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ 2666 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ 2667 2668 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ 2669 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ 2670 2671 #define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ 2672 #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ 2673 2674 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ 2675 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ 2676 2677 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ 2678 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ 2679 2680 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ 2681 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ 2682 2683 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ 2684 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ 2685 2686 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ 2687 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ 2688 2689 /* Debug Core Register Selector Register Definitions */ 2690 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ 2691 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ 2692 2693 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ 2694 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ 2695 2696 /* Debug Exception and Monitor Control Register Definitions */ 2697 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ 2698 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ 2699 2700 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ 2701 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ 2702 2703 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ 2704 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ 2705 2706 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ 2707 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ 2708 2709 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ 2710 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ 2711 2712 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ 2713 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ 2714 2715 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ 2716 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ 2717 2718 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ 2719 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ 2720 2721 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ 2722 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ 2723 2724 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ 2725 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ 2726 2727 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ 2728 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ 2729 2730 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ 2731 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ 2732 2733 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ 2734 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ 2735 2736 /* Debug Set Clear Exception and Monitor Control Register Definitions */ 2737 #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ 2738 #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ 2739 2740 #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ 2741 #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ 2742 2743 #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ 2744 #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ 2745 2746 #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ 2747 #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ 2748 2749 /* Debug Authentication Control Register Definitions */ 2750 #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ 2751 #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ 2752 2753 #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ 2754 #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ 2755 2756 #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ 2757 #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ 2758 2759 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 2760 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 2761 2762 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 2763 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 2764 2765 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ 2766 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 2767 2768 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ 2769 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 2770 2771 /* Debug Security Control and Status Register Definitions */ 2772 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ 2773 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ 2774 2775 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ 2776 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ 2777 2778 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ 2779 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ 2780 2781 /*@} end of group CMSIS_CoreDebug */ 2782 2783 2784 /** 2785 \ingroup CMSIS_core_register 2786 \defgroup CMSIS_DCB Debug Control Block 2787 \brief Type definitions for the Debug Control Block Registers 2788 @{ 2789 */ 2790 2791 /** 2792 \brief Structure type to access the Debug Control Block Registers (DCB). 2793 */ 2794 typedef struct 2795 { 2796 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 2797 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 2798 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 2799 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 2800 __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ 2801 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 2802 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 2803 } DCB_Type; 2804 2805 /* DHCSR, Debug Halting Control and Status Register Definitions */ 2806 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ 2807 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ 2808 2809 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ 2810 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ 2811 2812 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ 2813 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ 2814 2815 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ 2816 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ 2817 2818 #define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ 2819 #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ 2820 2821 #define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ 2822 #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ 2823 2824 #define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ 2825 #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ 2826 2827 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ 2828 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ 2829 2830 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ 2831 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ 2832 2833 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ 2834 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ 2835 2836 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ 2837 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ 2838 2839 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ 2840 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ 2841 2842 #define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ 2843 #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ 2844 2845 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ 2846 #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ 2847 2848 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ 2849 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ 2850 2851 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ 2852 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ 2853 2854 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ 2855 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ 2856 2857 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ 2858 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ 2859 2860 /* DCRSR, Debug Core Register Select Register Definitions */ 2861 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ 2862 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ 2863 2864 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ 2865 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ 2866 2867 /* DCRDR, Debug Core Register Data Register Definitions */ 2868 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ 2869 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ 2870 2871 /* DEMCR, Debug Exception and Monitor Control Register Definitions */ 2872 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ 2873 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ 2874 2875 #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ 2876 #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ 2877 2878 #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ 2879 #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ 2880 2881 #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ 2882 #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ 2883 2884 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ 2885 #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ 2886 2887 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ 2888 #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ 2889 2890 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ 2891 #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ 2892 2893 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ 2894 #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ 2895 2896 #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ 2897 #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ 2898 2899 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ 2900 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ 2901 2902 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ 2903 #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ 2904 2905 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ 2906 #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ 2907 2908 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ 2909 #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ 2910 2911 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ 2912 #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ 2913 2914 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ 2915 #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ 2916 2917 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ 2918 #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ 2919 2920 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ 2921 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ 2922 2923 /* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ 2924 #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ 2925 #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ 2926 2927 #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ 2928 #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ 2929 2930 #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ 2931 #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ 2932 2933 #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ 2934 #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ 2935 2936 /* DAUTHCTRL, Debug Authentication Control Register Definitions */ 2937 #define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ 2938 #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ 2939 2940 #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ 2941 #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ 2942 2943 #define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ 2944 #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ 2945 2946 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ 2947 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ 2948 2949 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ 2950 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ 2951 2952 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ 2953 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ 2954 2955 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ 2956 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ 2957 2958 /* DSCSR, Debug Security Control and Status Register Definitions */ 2959 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ 2960 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ 2961 2962 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ 2963 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ 2964 2965 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ 2966 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ 2967 2968 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ 2969 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ 2970 2971 /*@} end of group CMSIS_DCB */ 2972 2973 2974 2975 /** 2976 \ingroup CMSIS_core_register 2977 \defgroup CMSIS_DIB Debug Identification Block 2978 \brief Type definitions for the Debug Identification Block Registers 2979 @{ 2980 */ 2981 2982 /** 2983 \brief Structure type to access the Debug Identification Block Registers (DIB). 2984 */ 2985 typedef struct 2986 { 2987 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ 2988 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ 2989 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ 2990 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ 2991 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ 2992 } DIB_Type; 2993 2994 /* DLAR, SCS Software Lock Access Register Definitions */ 2995 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ 2996 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ 2997 2998 /* DLSR, SCS Software Lock Status Register Definitions */ 2999 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ 3000 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ 3001 3002 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ 3003 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ 3004 3005 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ 3006 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ 3007 3008 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ 3009 #define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ 3010 #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ 3011 3012 #define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ 3013 #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ 3014 3015 #define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ 3016 #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ 3017 3018 #define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ 3019 #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ 3020 3021 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ 3022 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ 3023 3024 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ 3025 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ 3026 3027 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ 3028 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ 3029 3030 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ 3031 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ 3032 3033 /* DDEVARCH, SCS Device Architecture Register Definitions */ 3034 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ 3035 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ 3036 3037 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ 3038 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ 3039 3040 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ 3041 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ 3042 3043 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ 3044 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ 3045 3046 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ 3047 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ 3048 3049 /* DDEVTYPE, SCS Device Type Register Definitions */ 3050 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ 3051 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ 3052 3053 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ 3054 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ 3055 3056 3057 /*@} end of group CMSIS_DIB */ 3058 3059 3060 /** 3061 \ingroup CMSIS_core_register 3062 \defgroup CMSIS_core_bitfield Core register bit field macros 3063 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 3064 @{ 3065 */ 3066 3067 /** 3068 \brief Mask and shift a bit field value for use in a register bit range. 3069 \param[in] field Name of the register bit field. 3070 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 3071 \return Masked and shifted value. 3072 */ 3073 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 3074 3075 /** 3076 \brief Mask and shift a register value to extract a bit filed value. 3077 \param[in] field Name of the register bit field. 3078 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 3079 \return Masked and shifted bit field value. 3080 */ 3081 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 3082 3083 /*@} end of group CMSIS_core_bitfield */ 3084 3085 3086 /** 3087 \ingroup CMSIS_core_register 3088 \defgroup CMSIS_core_base Core Definitions 3089 \brief Definitions for base addresses, unions, and structures. 3090 @{ 3091 */ 3092 3093 /* Memory mapping of Core Hardware */ 3094 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 3095 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 3096 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 3097 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 3098 #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ 3099 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ 3100 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ 3101 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 3102 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 3103 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 3104 3105 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 3106 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 3107 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 3108 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 3109 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 3110 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 3111 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 3112 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ 3113 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ 3114 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ 3115 3116 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 3117 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 3118 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 3119 #endif 3120 3121 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) 3122 #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ 3123 #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ 3124 #endif 3125 3126 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 3127 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 3128 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 3129 #endif 3130 3131 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 3132 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 3133 3134 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 3135 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 3136 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ 3137 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ 3138 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ 3139 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 3140 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 3141 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 3142 3143 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ 3144 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 3145 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 3146 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 3147 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ 3148 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ 3149 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ 3150 3151 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 3152 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 3153 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 3154 #endif 3155 3156 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ 3157 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ 3158 3159 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 3160 /*@} */ 3161 3162 3163 /** 3164 \ingroup CMSIS_core_register 3165 \defgroup CMSIS_register_aliases Backwards Compatibility Aliases 3166 \brief Register alias definitions for backwards compatibility. 3167 @{ 3168 */ 3169 #define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ 3170 /*@} */ 3171 3172 3173 /******************************************************************************* 3174 * Hardware Abstraction Layer 3175 Core Function Interface contains: 3176 - Core NVIC Functions 3177 - Core SysTick Functions 3178 - Core Debug Functions 3179 - Core Register Access Functions 3180 ******************************************************************************/ 3181 /** 3182 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 3183 */ 3184 3185 3186 3187 /* ########################## NVIC functions #################################### */ 3188 /** 3189 \ingroup CMSIS_Core_FunctionInterface 3190 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 3191 \brief Functions that manage interrupts and exceptions via the NVIC. 3192 @{ 3193 */ 3194 3195 #ifdef CMSIS_NVIC_VIRTUAL 3196 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 3197 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 3198 #endif 3199 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 3200 #else 3201 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 3202 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 3203 #define NVIC_EnableIRQ __NVIC_EnableIRQ 3204 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 3205 #define NVIC_DisableIRQ __NVIC_DisableIRQ 3206 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 3207 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 3208 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 3209 #define NVIC_GetActive __NVIC_GetActive 3210 #define NVIC_SetPriority __NVIC_SetPriority 3211 #define NVIC_GetPriority __NVIC_GetPriority 3212 #define NVIC_SystemReset __NVIC_SystemReset 3213 #endif /* CMSIS_NVIC_VIRTUAL */ 3214 3215 #ifdef CMSIS_VECTAB_VIRTUAL 3216 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 3217 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 3218 #endif 3219 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 3220 #else 3221 #define NVIC_SetVector __NVIC_SetVector 3222 #define NVIC_GetVector __NVIC_GetVector 3223 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 3224 3225 #define NVIC_USER_IRQ_OFFSET 16 3226 3227 3228 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 3229 3230 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 3231 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 3232 3233 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 3234 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 3235 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 3236 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 3237 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 3238 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 3239 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ 3240 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 3241 3242 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 3243 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 3244 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 3245 #else 3246 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 3247 #endif 3248 3249 3250 /** 3251 \brief Set Priority Grouping 3252 \details Sets the priority grouping field using the required unlock sequence. 3253 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 3254 Only values from 0..7 are used. 3255 In case of a conflict between priority grouping and available 3256 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 3257 \param [in] PriorityGroup Priority grouping field. 3258 */ 3259 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 3260 { 3261 uint32_t reg_value; 3262 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 3263 3264 reg_value = SCB->AIRCR; /* read old register configuration */ 3265 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 3266 reg_value = (reg_value | 3267 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 3268 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 3269 SCB->AIRCR = reg_value; 3270 } 3271 3272 3273 /** 3274 \brief Get Priority Grouping 3275 \details Reads the priority grouping field from the NVIC Interrupt Controller. 3276 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 3277 */ 3278 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 3279 { 3280 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 3281 } 3282 3283 3284 /** 3285 \brief Enable Interrupt 3286 \details Enables a device specific interrupt in the NVIC interrupt controller. 3287 \param [in] IRQn Device specific interrupt number. 3288 \note IRQn must not be negative. 3289 */ 3290 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 3291 { 3292 if ((int32_t)(IRQn) >= 0) 3293 { 3294 __COMPILER_BARRIER(); 3295 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 3296 __COMPILER_BARRIER(); 3297 } 3298 } 3299 3300 3301 /** 3302 \brief Get Interrupt Enable status 3303 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 3304 \param [in] IRQn Device specific interrupt number. 3305 \return 0 Interrupt is not enabled. 3306 \return 1 Interrupt is enabled. 3307 \note IRQn must not be negative. 3308 */ 3309 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 3310 { 3311 if ((int32_t)(IRQn) >= 0) 3312 { 3313 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3314 } 3315 else 3316 { 3317 return(0U); 3318 } 3319 } 3320 3321 3322 /** 3323 \brief Disable Interrupt 3324 \details Disables a device specific interrupt in the NVIC interrupt controller. 3325 \param [in] IRQn Device specific interrupt number. 3326 \note IRQn must not be negative. 3327 */ 3328 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 3329 { 3330 if ((int32_t)(IRQn) >= 0) 3331 { 3332 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 3333 __DSB(); 3334 __ISB(); 3335 } 3336 } 3337 3338 3339 /** 3340 \brief Get Pending Interrupt 3341 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 3342 \param [in] IRQn Device specific interrupt number. 3343 \return 0 Interrupt status is not pending. 3344 \return 1 Interrupt status is pending. 3345 \note IRQn must not be negative. 3346 */ 3347 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 3348 { 3349 if ((int32_t)(IRQn) >= 0) 3350 { 3351 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3352 } 3353 else 3354 { 3355 return(0U); 3356 } 3357 } 3358 3359 3360 /** 3361 \brief Set Pending Interrupt 3362 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 3363 \param [in] IRQn Device specific interrupt number. 3364 \note IRQn must not be negative. 3365 */ 3366 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 3367 { 3368 if ((int32_t)(IRQn) >= 0) 3369 { 3370 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 3371 } 3372 } 3373 3374 3375 /** 3376 \brief Clear Pending Interrupt 3377 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 3378 \param [in] IRQn Device specific interrupt number. 3379 \note IRQn must not be negative. 3380 */ 3381 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 3382 { 3383 if ((int32_t)(IRQn) >= 0) 3384 { 3385 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 3386 } 3387 } 3388 3389 3390 /** 3391 \brief Get Active Interrupt 3392 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 3393 \param [in] IRQn Device specific interrupt number. 3394 \return 0 Interrupt status is not active. 3395 \return 1 Interrupt status is active. 3396 \note IRQn must not be negative. 3397 */ 3398 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 3399 { 3400 if ((int32_t)(IRQn) >= 0) 3401 { 3402 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3403 } 3404 else 3405 { 3406 return(0U); 3407 } 3408 } 3409 3410 3411 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 3412 /** 3413 \brief Get Interrupt Target State 3414 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 3415 \param [in] IRQn Device specific interrupt number. 3416 \return 0 if interrupt is assigned to Secure 3417 \return 1 if interrupt is assigned to Non Secure 3418 \note IRQn must not be negative. 3419 */ 3420 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 3421 { 3422 if ((int32_t)(IRQn) >= 0) 3423 { 3424 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3425 } 3426 else 3427 { 3428 return(0U); 3429 } 3430 } 3431 3432 3433 /** 3434 \brief Set Interrupt Target State 3435 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 3436 \param [in] IRQn Device specific interrupt number. 3437 \return 0 if interrupt is assigned to Secure 3438 1 if interrupt is assigned to Non Secure 3439 \note IRQn must not be negative. 3440 */ 3441 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 3442 { 3443 if ((int32_t)(IRQn) >= 0) 3444 { 3445 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 3446 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3447 } 3448 else 3449 { 3450 return(0U); 3451 } 3452 } 3453 3454 3455 /** 3456 \brief Clear Interrupt Target State 3457 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 3458 \param [in] IRQn Device specific interrupt number. 3459 \return 0 if interrupt is assigned to Secure 3460 1 if interrupt is assigned to Non Secure 3461 \note IRQn must not be negative. 3462 */ 3463 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 3464 { 3465 if ((int32_t)(IRQn) >= 0) 3466 { 3467 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 3468 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3469 } 3470 else 3471 { 3472 return(0U); 3473 } 3474 } 3475 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 3476 3477 3478 /** 3479 \brief Set Interrupt Priority 3480 \details Sets the priority of a device specific interrupt or a processor exception. 3481 The interrupt number can be positive to specify a device specific interrupt, 3482 or negative to specify a processor exception. 3483 \param [in] IRQn Interrupt number. 3484 \param [in] priority Priority to set. 3485 \note The priority cannot be set for every processor exception. 3486 */ 3487 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 3488 { 3489 if ((int32_t)(IRQn) >= 0) 3490 { 3491 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 3492 } 3493 else 3494 { 3495 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 3496 } 3497 } 3498 3499 3500 /** 3501 \brief Get Interrupt Priority 3502 \details Reads the priority of a device specific interrupt or a processor exception. 3503 The interrupt number can be positive to specify a device specific interrupt, 3504 or negative to specify a processor exception. 3505 \param [in] IRQn Interrupt number. 3506 \return Interrupt Priority. 3507 Value is aligned automatically to the implemented priority bits of the microcontroller. 3508 */ 3509 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 3510 { 3511 3512 if ((int32_t)(IRQn) >= 0) 3513 { 3514 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 3515 } 3516 else 3517 { 3518 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 3519 } 3520 } 3521 3522 3523 /** 3524 \brief Encode Priority 3525 \details Encodes the priority for an interrupt with the given priority group, 3526 preemptive priority value, and subpriority value. 3527 In case of a conflict between priority grouping and available 3528 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 3529 \param [in] PriorityGroup Used priority group. 3530 \param [in] PreemptPriority Preemptive priority value (starting from 0). 3531 \param [in] SubPriority Subpriority value (starting from 0). 3532 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 3533 */ 3534 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 3535 { 3536 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 3537 uint32_t PreemptPriorityBits; 3538 uint32_t SubPriorityBits; 3539 3540 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 3541 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 3542 3543 return ( 3544 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 3545 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 3546 ); 3547 } 3548 3549 3550 /** 3551 \brief Decode Priority 3552 \details Decodes an interrupt priority value with a given priority group to 3553 preemptive priority value and subpriority value. 3554 In case of a conflict between priority grouping and available 3555 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 3556 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 3557 \param [in] PriorityGroup Used priority group. 3558 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 3559 \param [out] pSubPriority Subpriority value (starting from 0). 3560 */ 3561 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 3562 { 3563 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 3564 uint32_t PreemptPriorityBits; 3565 uint32_t SubPriorityBits; 3566 3567 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 3568 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 3569 3570 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 3571 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 3572 } 3573 3574 3575 /** 3576 \brief Set Interrupt Vector 3577 \details Sets an interrupt vector in SRAM based interrupt vector table. 3578 The interrupt number can be positive to specify a device specific interrupt, 3579 or negative to specify a processor exception. 3580 VTOR must been relocated to SRAM before. 3581 \param [in] IRQn Interrupt number 3582 \param [in] vector Address of interrupt handler function 3583 */ 3584 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 3585 { 3586 uint32_t *vectors = (uint32_t *)SCB->VTOR; 3587 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 3588 __DSB(); 3589 } 3590 3591 3592 /** 3593 \brief Get Interrupt Vector 3594 \details Reads an interrupt vector from interrupt vector table. 3595 The interrupt number can be positive to specify a device specific interrupt, 3596 or negative to specify a processor exception. 3597 \param [in] IRQn Interrupt number. 3598 \return Address of interrupt handler function 3599 */ 3600 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 3601 { 3602 uint32_t *vectors = (uint32_t *)SCB->VTOR; 3603 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 3604 } 3605 3606 3607 /** 3608 \brief System Reset 3609 \details Initiates a system reset request to reset the MCU. 3610 */ 3611 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 3612 { 3613 __DSB(); /* Ensure all outstanding memory accesses included 3614 buffered write are completed before reset */ 3615 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 3616 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 3617 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 3618 __DSB(); /* Ensure completion of memory access */ 3619 3620 for(;;) /* wait until reset */ 3621 { 3622 __NOP(); 3623 } 3624 } 3625 3626 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 3627 /** 3628 \brief Set Priority Grouping (non-secure) 3629 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. 3630 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 3631 Only values from 0..7 are used. 3632 In case of a conflict between priority grouping and available 3633 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 3634 \param [in] PriorityGroup Priority grouping field. 3635 */ 3636 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) 3637 { 3638 uint32_t reg_value; 3639 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 3640 3641 reg_value = SCB_NS->AIRCR; /* read old register configuration */ 3642 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 3643 reg_value = (reg_value | 3644 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 3645 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 3646 SCB_NS->AIRCR = reg_value; 3647 } 3648 3649 3650 /** 3651 \brief Get Priority Grouping (non-secure) 3652 \details Reads the priority grouping field from the non-secure NVIC when in secure state. 3653 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 3654 */ 3655 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) 3656 { 3657 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 3658 } 3659 3660 3661 /** 3662 \brief Enable Interrupt (non-secure) 3663 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 3664 \param [in] IRQn Device specific interrupt number. 3665 \note IRQn must not be negative. 3666 */ 3667 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 3668 { 3669 if ((int32_t)(IRQn) >= 0) 3670 { 3671 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 3672 } 3673 } 3674 3675 3676 /** 3677 \brief Get Interrupt Enable status (non-secure) 3678 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 3679 \param [in] IRQn Device specific interrupt number. 3680 \return 0 Interrupt is not enabled. 3681 \return 1 Interrupt is enabled. 3682 \note IRQn must not be negative. 3683 */ 3684 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 3685 { 3686 if ((int32_t)(IRQn) >= 0) 3687 { 3688 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3689 } 3690 else 3691 { 3692 return(0U); 3693 } 3694 } 3695 3696 3697 /** 3698 \brief Disable Interrupt (non-secure) 3699 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 3700 \param [in] IRQn Device specific interrupt number. 3701 \note IRQn must not be negative. 3702 */ 3703 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 3704 { 3705 if ((int32_t)(IRQn) >= 0) 3706 { 3707 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 3708 } 3709 } 3710 3711 3712 /** 3713 \brief Get Pending Interrupt (non-secure) 3714 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 3715 \param [in] IRQn Device specific interrupt number. 3716 \return 0 Interrupt status is not pending. 3717 \return 1 Interrupt status is pending. 3718 \note IRQn must not be negative. 3719 */ 3720 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 3721 { 3722 if ((int32_t)(IRQn) >= 0) 3723 { 3724 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3725 } 3726 else 3727 { 3728 return(0U); 3729 } 3730 } 3731 3732 3733 /** 3734 \brief Set Pending Interrupt (non-secure) 3735 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 3736 \param [in] IRQn Device specific interrupt number. 3737 \note IRQn must not be negative. 3738 */ 3739 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 3740 { 3741 if ((int32_t)(IRQn) >= 0) 3742 { 3743 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 3744 } 3745 } 3746 3747 3748 /** 3749 \brief Clear Pending Interrupt (non-secure) 3750 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 3751 \param [in] IRQn Device specific interrupt number. 3752 \note IRQn must not be negative. 3753 */ 3754 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 3755 { 3756 if ((int32_t)(IRQn) >= 0) 3757 { 3758 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 3759 } 3760 } 3761 3762 3763 /** 3764 \brief Get Active Interrupt (non-secure) 3765 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 3766 \param [in] IRQn Device specific interrupt number. 3767 \return 0 Interrupt status is not active. 3768 \return 1 Interrupt status is active. 3769 \note IRQn must not be negative. 3770 */ 3771 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 3772 { 3773 if ((int32_t)(IRQn) >= 0) 3774 { 3775 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 3776 } 3777 else 3778 { 3779 return(0U); 3780 } 3781 } 3782 3783 3784 /** 3785 \brief Set Interrupt Priority (non-secure) 3786 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 3787 The interrupt number can be positive to specify a device specific interrupt, 3788 or negative to specify a processor exception. 3789 \param [in] IRQn Interrupt number. 3790 \param [in] priority Priority to set. 3791 \note The priority cannot be set for every non-secure processor exception. 3792 */ 3793 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 3794 { 3795 if ((int32_t)(IRQn) >= 0) 3796 { 3797 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 3798 } 3799 else 3800 { 3801 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 3802 } 3803 } 3804 3805 3806 /** 3807 \brief Get Interrupt Priority (non-secure) 3808 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 3809 The interrupt number can be positive to specify a device specific interrupt, 3810 or negative to specify a processor exception. 3811 \param [in] IRQn Interrupt number. 3812 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 3813 */ 3814 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 3815 { 3816 3817 if ((int32_t)(IRQn) >= 0) 3818 { 3819 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 3820 } 3821 else 3822 { 3823 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 3824 } 3825 } 3826 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 3827 3828 /*@} end of CMSIS_Core_NVICFunctions */ 3829 3830 /* ########################## MPU functions #################################### */ 3831 3832 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 3833 3834 #include "mpu_armv8.h" 3835 3836 #endif 3837 3838 /* ########################## PMU functions and events #################################### */ 3839 3840 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) 3841 3842 #include "pmu_armv8.h" 3843 3844 #endif 3845 3846 /* ########################## FPU functions #################################### */ 3847 /** 3848 \ingroup CMSIS_Core_FunctionInterface 3849 \defgroup CMSIS_Core_FpuFunctions FPU Functions 3850 \brief Function that provides FPU type. 3851 @{ 3852 */ 3853 3854 /** 3855 \brief get FPU type 3856 \details returns the FPU type 3857 \returns 3858 - \b 0: No FPU 3859 - \b 1: Single precision FPU 3860 - \b 2: Double + Single precision FPU 3861 */ 3862 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 3863 { 3864 uint32_t mvfr0; 3865 3866 mvfr0 = FPU->MVFR0; 3867 if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) 3868 { 3869 return 2U; /* Double + Single precision FPU */ 3870 } 3871 else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) 3872 { 3873 return 1U; /* Single precision FPU */ 3874 } 3875 else 3876 { 3877 return 0U; /* No FPU */ 3878 } 3879 } 3880 3881 3882 /*@} end of CMSIS_Core_FpuFunctions */ 3883 3884 /* ########################## MVE functions #################################### */ 3885 /** 3886 \ingroup CMSIS_Core_FunctionInterface 3887 \defgroup CMSIS_Core_MveFunctions MVE Functions 3888 \brief Function that provides MVE type. 3889 @{ 3890 */ 3891 3892 /** 3893 \brief get MVE type 3894 \details returns the MVE type 3895 \returns 3896 - \b 0: No Vector Extension (MVE) 3897 - \b 1: Integer Vector Extension (MVE-I) 3898 - \b 2: Floating-point Vector Extension (MVE-F) 3899 */ 3900 __STATIC_INLINE uint32_t SCB_GetMVEType(void) 3901 { 3902 const uint32_t mvfr1 = FPU->MVFR1; 3903 if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) 3904 { 3905 return 2U; 3906 } 3907 else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) 3908 { 3909 return 1U; 3910 } 3911 else 3912 { 3913 return 0U; 3914 } 3915 } 3916 3917 3918 /*@} end of CMSIS_Core_MveFunctions */ 3919 3920 3921 /* ########################## Cache functions #################################### */ 3922 3923 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ 3924 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) 3925 #include "cachel1_armv7.h" 3926 #endif 3927 3928 3929 /* ########################## SAU functions #################################### */ 3930 /** 3931 \ingroup CMSIS_Core_FunctionInterface 3932 \defgroup CMSIS_Core_SAUFunctions SAU Functions 3933 \brief Functions that configure the SAU. 3934 @{ 3935 */ 3936 3937 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 3938 3939 /** 3940 \brief Enable SAU 3941 \details Enables the Security Attribution Unit (SAU). 3942 */ 3943 __STATIC_INLINE void TZ_SAU_Enable(void) 3944 { 3945 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 3946 } 3947 3948 3949 3950 /** 3951 \brief Disable SAU 3952 \details Disables the Security Attribution Unit (SAU). 3953 */ 3954 __STATIC_INLINE void TZ_SAU_Disable(void) 3955 { 3956 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 3957 } 3958 3959 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 3960 3961 /*@} end of CMSIS_Core_SAUFunctions */ 3962 3963 3964 3965 3966 /* ################################## Debug Control function ############################################ */ 3967 /** 3968 \ingroup CMSIS_Core_FunctionInterface 3969 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions 3970 \brief Functions that access the Debug Control Block. 3971 @{ 3972 */ 3973 3974 3975 /** 3976 \brief Set Debug Authentication Control Register 3977 \details writes to Debug Authentication Control register. 3978 \param [in] value value to be writen. 3979 */ 3980 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) 3981 { 3982 __DSB(); 3983 __ISB(); 3984 DCB->DAUTHCTRL = value; 3985 __DSB(); 3986 __ISB(); 3987 } 3988 3989 3990 /** 3991 \brief Get Debug Authentication Control Register 3992 \details Reads Debug Authentication Control register. 3993 \return Debug Authentication Control Register. 3994 */ 3995 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) 3996 { 3997 return (DCB->DAUTHCTRL); 3998 } 3999 4000 4001 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 4002 /** 4003 \brief Set Debug Authentication Control Register (non-secure) 4004 \details writes to non-secure Debug Authentication Control register when in secure state. 4005 \param [in] value value to be writen 4006 */ 4007 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) 4008 { 4009 __DSB(); 4010 __ISB(); 4011 DCB_NS->DAUTHCTRL = value; 4012 __DSB(); 4013 __ISB(); 4014 } 4015 4016 4017 /** 4018 \brief Get Debug Authentication Control Register (non-secure) 4019 \details Reads non-secure Debug Authentication Control register when in secure state. 4020 \return Debug Authentication Control Register. 4021 */ 4022 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) 4023 { 4024 return (DCB_NS->DAUTHCTRL); 4025 } 4026 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 4027 4028 /*@} end of CMSIS_Core_DCBFunctions */ 4029 4030 4031 4032 4033 /* ################################## Debug Identification function ############################################ */ 4034 /** 4035 \ingroup CMSIS_Core_FunctionInterface 4036 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions 4037 \brief Functions that access the Debug Identification Block. 4038 @{ 4039 */ 4040 4041 4042 /** 4043 \brief Get Debug Authentication Status Register 4044 \details Reads Debug Authentication Status register. 4045 \return Debug Authentication Status Register. 4046 */ 4047 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) 4048 { 4049 return (DIB->DAUTHSTATUS); 4050 } 4051 4052 4053 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 4054 /** 4055 \brief Get Debug Authentication Status Register (non-secure) 4056 \details Reads non-secure Debug Authentication Status register when in secure state. 4057 \return Debug Authentication Status Register. 4058 */ 4059 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) 4060 { 4061 return (DIB_NS->DAUTHSTATUS); 4062 } 4063 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 4064 4065 /*@} end of CMSIS_Core_DCBFunctions */ 4066 4067 4068 4069 4070 /* ################################## SysTick function ############################################ */ 4071 /** 4072 \ingroup CMSIS_Core_FunctionInterface 4073 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 4074 \brief Functions that configure the System. 4075 @{ 4076 */ 4077 4078 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 4079 4080 /** 4081 \brief System Tick Configuration 4082 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 4083 Counter is in free running mode to generate periodic interrupts. 4084 \param [in] ticks Number of ticks between two interrupts. 4085 \return 0 Function succeeded. 4086 \return 1 Function failed. 4087 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 4088 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 4089 must contain a vendor-specific implementation of this function. 4090 */ 4091 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 4092 { 4093 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 4094 { 4095 return (1UL); /* Reload value impossible */ 4096 } 4097 4098 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 4099 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 4100 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 4101 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 4102 SysTick_CTRL_TICKINT_Msk | 4103 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 4104 return (0UL); /* Function successful */ 4105 } 4106 4107 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 4108 /** 4109 \brief System Tick Configuration (non-secure) 4110 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 4111 Counter is in free running mode to generate periodic interrupts. 4112 \param [in] ticks Number of ticks between two interrupts. 4113 \return 0 Function succeeded. 4114 \return 1 Function failed. 4115 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 4116 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 4117 must contain a vendor-specific implementation of this function. 4118 4119 */ 4120 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 4121 { 4122 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 4123 { 4124 return (1UL); /* Reload value impossible */ 4125 } 4126 4127 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 4128 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 4129 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 4130 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 4131 SysTick_CTRL_TICKINT_Msk | 4132 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 4133 return (0UL); /* Function successful */ 4134 } 4135 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 4136 4137 #endif 4138 4139 /*@} end of CMSIS_Core_SysTickFunctions */ 4140 4141 4142 4143 /* ##################################### Debug In/Output function ########################################### */ 4144 /** 4145 \ingroup CMSIS_Core_FunctionInterface 4146 \defgroup CMSIS_core_DebugFunctions ITM Functions 4147 \brief Functions that access the ITM debug interface. 4148 @{ 4149 */ 4150 4151 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 4152 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 4153 4154 4155 /** 4156 \brief ITM Send Character 4157 \details Transmits a character via the ITM channel 0, and 4158 \li Just returns when no debugger is connected that has booked the output. 4159 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 4160 \param [in] ch Character to transmit. 4161 \returns Character to transmit. 4162 */ 4163 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 4164 { 4165 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 4166 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 4167 { 4168 while (ITM->PORT[0U].u32 == 0UL) 4169 { 4170 __NOP(); 4171 } 4172 ITM->PORT[0U].u8 = (uint8_t)ch; 4173 } 4174 return (ch); 4175 } 4176 4177 4178 /** 4179 \brief ITM Receive Character 4180 \details Inputs a character via the external variable \ref ITM_RxBuffer. 4181 \return Received character. 4182 \return -1 No character pending. 4183 */ 4184 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 4185 { 4186 int32_t ch = -1; /* no character available */ 4187 4188 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 4189 { 4190 ch = ITM_RxBuffer; 4191 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 4192 } 4193 4194 return (ch); 4195 } 4196 4197 4198 /** 4199 \brief ITM Check Character 4200 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 4201 \return 0 No character available. 4202 \return 1 Character available. 4203 */ 4204 __STATIC_INLINE int32_t ITM_CheckChar (void) 4205 { 4206 4207 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 4208 { 4209 return (0); /* no character available */ 4210 } 4211 else 4212 { 4213 return (1); /* character available */ 4214 } 4215 } 4216 4217 /*@} end of CMSIS_core_DebugFunctions */ 4218 4219 4220 4221 4222 #ifdef __cplusplus 4223 } 4224 #endif 4225 4226 #endif /* __CORE_ARMV81MML_H_DEPENDANT */ 4227 4228 #endif /* __CMSIS_GENERIC */