core_armv8mbl.h
1 /**************************************************************************//** 2 * @file core_armv8mbl.h 3 * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File 4 * @version V5.1.0 5 * @date 27. March 2020 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2020 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #elif defined ( __GNUC__ ) 30 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ 31 #endif 32 33 #ifndef __CORE_ARMV8MBL_H_GENERIC 34 #define __CORE_ARMV8MBL_H_GENERIC 35 36 #include <stdint.h> 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /** 43 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 44 CMSIS violates the following MISRA-C:2004 rules: 45 46 \li Required Rule 8.5, object/function definition in header file.<br> 47 Function definitions in header files are used to allow 'inlining'. 48 49 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 50 Unions are used for effective representation of core registers. 51 52 \li Advisory Rule 19.7, Function-like macro defined.<br> 53 Function-like macros are used to allow more efficient code. 54 */ 55 56 57 /******************************************************************************* 58 * CMSIS definitions 59 ******************************************************************************/ 60 /** 61 \ingroup Cortex_ARMv8MBL 62 @{ 63 */ 64 65 #include "cmsis_version.h" 66 67 /* CMSIS definitions */ 68 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 69 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 70 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ 71 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 72 73 #define __CORTEX_M (2U) /*!< Cortex-M Core */ 74 75 /** __FPU_USED indicates whether an FPU is used or not. 76 This core does not support an FPU at all 77 */ 78 #define __FPU_USED 0U 79 80 #if defined ( __CC_ARM ) 81 #if defined __TARGET_FPU_VFP 82 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 83 #endif 84 85 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 86 #if defined __ARM_FP 87 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 88 #endif 89 90 #elif defined ( __GNUC__ ) 91 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 92 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 93 #endif 94 95 #elif defined ( __ICCARM__ ) 96 #if defined __ARMVFP__ 97 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 98 #endif 99 100 #elif defined ( __TI_ARM__ ) 101 #if defined __TI_VFP_SUPPORT__ 102 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 103 #endif 104 105 #elif defined ( __TASKING__ ) 106 #if defined __FPU_VFP__ 107 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 108 #endif 109 110 #elif defined ( __CSMC__ ) 111 #if ( __CSMC__ & 0x400U) 112 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 113 #endif 114 115 #endif 116 117 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 118 119 120 #ifdef __cplusplus 121 } 122 #endif 123 124 #endif /* __CORE_ARMV8MBL_H_GENERIC */ 125 126 #ifndef __CMSIS_GENERIC 127 128 #ifndef __CORE_ARMV8MBL_H_DEPENDANT 129 #define __CORE_ARMV8MBL_H_DEPENDANT 130 131 #ifdef __cplusplus 132 extern "C" { 133 #endif 134 135 /* check device defines and use defaults */ 136 #if defined __CHECK_DEVICE_DEFINES 137 #ifndef __ARMv8MBL_REV 138 #define __ARMv8MBL_REV 0x0000U 139 #warning "__ARMv8MBL_REV not defined in device header file; using default!" 140 #endif 141 142 #ifndef __FPU_PRESENT 143 #define __FPU_PRESENT 0U 144 #warning "__FPU_PRESENT not defined in device header file; using default!" 145 #endif 146 147 #ifndef __MPU_PRESENT 148 #define __MPU_PRESENT 0U 149 #warning "__MPU_PRESENT not defined in device header file; using default!" 150 #endif 151 152 #ifndef __SAUREGION_PRESENT 153 #define __SAUREGION_PRESENT 0U 154 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 155 #endif 156 157 #ifndef __VTOR_PRESENT 158 #define __VTOR_PRESENT 0U 159 #warning "__VTOR_PRESENT not defined in device header file; using default!" 160 #endif 161 162 #ifndef __NVIC_PRIO_BITS 163 #define __NVIC_PRIO_BITS 2U 164 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 165 #endif 166 167 #ifndef __Vendor_SysTickConfig 168 #define __Vendor_SysTickConfig 0U 169 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 170 #endif 171 172 #ifndef __ETM_PRESENT 173 #define __ETM_PRESENT 0U 174 #warning "__ETM_PRESENT not defined in device header file; using default!" 175 #endif 176 177 #ifndef __MTB_PRESENT 178 #define __MTB_PRESENT 0U 179 #warning "__MTB_PRESENT not defined in device header file; using default!" 180 #endif 181 182 #endif 183 184 /* IO definitions (access restrictions to peripheral registers) */ 185 /** 186 \defgroup CMSIS_glob_defs CMSIS Global Defines 187 188 <strong>IO Type Qualifiers</strong> are used 189 \li to specify the access to peripheral variables. 190 \li for automatic generation of peripheral register debug information. 191 */ 192 #ifdef __cplusplus 193 #define __I volatile /*!< Defines 'read only' permissions */ 194 #else 195 #define __I volatile const /*!< Defines 'read only' permissions */ 196 #endif 197 #define __O volatile /*!< Defines 'write only' permissions */ 198 #define __IO volatile /*!< Defines 'read / write' permissions */ 199 200 /* following defines should be used for structure members */ 201 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 202 #define __OM volatile /*! Defines 'write only' structure member permissions */ 203 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 204 205 /*@} end of group ARMv8MBL */ 206 207 208 209 /******************************************************************************* 210 * Register Abstraction 211 Core Register contain: 212 - Core Register 213 - Core NVIC Register 214 - Core SCB Register 215 - Core SysTick Register 216 - Core Debug Register 217 - Core MPU Register 218 - Core SAU Register 219 ******************************************************************************/ 220 /** 221 \defgroup CMSIS_core_register Defines and Type Definitions 222 \brief Type definitions and defines for Cortex-M processor based devices. 223 */ 224 225 /** 226 \ingroup CMSIS_core_register 227 \defgroup CMSIS_CORE Status and Control Registers 228 \brief Core Register type definitions. 229 @{ 230 */ 231 232 /** 233 \brief Union type to access the Application Program Status Register (APSR). 234 */ 235 typedef union 236 { 237 struct 238 { 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 244 } b; /*!< Structure used for bit access */ 245 uint32_t w; /*!< Type used for word access */ 246 } APSR_Type; 247 248 /* APSR Register Definitions */ 249 #define APSR_N_Pos 31U /*!< APSR: N Position */ 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 251 252 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 254 255 #define APSR_C_Pos 29U /*!< APSR: C Position */ 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 257 258 #define APSR_V_Pos 28U /*!< APSR: V Position */ 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 260 261 262 /** 263 \brief Union type to access the Interrupt Program Status Register (IPSR). 264 */ 265 typedef union 266 { 267 struct 268 { 269 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 270 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 271 } b; /*!< Structure used for bit access */ 272 uint32_t w; /*!< Type used for word access */ 273 } IPSR_Type; 274 275 /* IPSR Register Definitions */ 276 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 277 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 278 279 280 /** 281 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 282 */ 283 typedef union 284 { 285 struct 286 { 287 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 288 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 289 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 290 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 291 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 292 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 293 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 294 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 295 } b; /*!< Structure used for bit access */ 296 uint32_t w; /*!< Type used for word access */ 297 } xPSR_Type; 298 299 /* xPSR Register Definitions */ 300 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 301 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 302 303 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 304 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 305 306 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 307 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 308 309 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 310 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 311 312 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 313 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 314 315 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 316 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 317 318 319 /** 320 \brief Union type to access the Control Registers (CONTROL). 321 */ 322 typedef union 323 { 324 struct 325 { 326 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 327 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 328 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 329 } b; /*!< Structure used for bit access */ 330 uint32_t w; /*!< Type used for word access */ 331 } CONTROL_Type; 332 333 /* CONTROL Register Definitions */ 334 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 335 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 336 337 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 338 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 339 340 /*@} end of group CMSIS_CORE */ 341 342 343 /** 344 \ingroup CMSIS_core_register 345 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 346 \brief Type definitions for the NVIC Registers 347 @{ 348 */ 349 350 /** 351 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 352 */ 353 typedef struct 354 { 355 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 356 uint32_t RESERVED0[16U]; 357 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 358 uint32_t RSERVED1[16U]; 359 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 360 uint32_t RESERVED2[16U]; 361 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 362 uint32_t RESERVED3[16U]; 363 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 364 uint32_t RESERVED4[16U]; 365 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 366 uint32_t RESERVED5[16U]; 367 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 368 } NVIC_Type; 369 370 /*@} end of group CMSIS_NVIC */ 371 372 373 /** 374 \ingroup CMSIS_core_register 375 \defgroup CMSIS_SCB System Control Block (SCB) 376 \brief Type definitions for the System Control Block Registers 377 @{ 378 */ 379 380 /** 381 \brief Structure type to access the System Control Block (SCB). 382 */ 383 typedef struct 384 { 385 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 386 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 387 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 388 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 389 #else 390 uint32_t RESERVED0; 391 #endif 392 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 393 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 394 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 395 uint32_t RESERVED1; 396 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 397 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 398 } SCB_Type; 399 400 /* SCB CPUID Register Definitions */ 401 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 402 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 403 404 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 405 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 406 407 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 408 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 409 410 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 411 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 412 413 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 414 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 415 416 /* SCB Interrupt Control State Register Definitions */ 417 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 418 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 419 420 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 421 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 422 423 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 424 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 425 426 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 427 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 428 429 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 430 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 431 432 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 433 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 434 435 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 436 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 437 438 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 439 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 440 441 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 442 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 443 444 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 445 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 446 447 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 448 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 449 450 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 451 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 452 453 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 454 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 455 456 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 457 /* SCB Vector Table Offset Register Definitions */ 458 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 459 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 460 #endif 461 462 /* SCB Application Interrupt and Reset Control Register Definitions */ 463 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 464 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 465 466 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 467 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 468 469 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 470 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 471 472 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 473 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 474 475 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 476 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 477 478 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 479 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 480 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 483 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 486 487 /* SCB System Control Register Definitions */ 488 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 489 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 490 491 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 492 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 493 494 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 496 497 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 499 500 /* SCB Configuration Control Register Definitions */ 501 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 502 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 503 504 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 505 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 506 507 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 508 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 509 510 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 511 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 512 513 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 514 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 515 516 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 517 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 518 519 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 520 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 521 522 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 523 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 524 525 /* SCB System Handler Control and State Register Definitions */ 526 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 527 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 528 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 531 532 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 533 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 534 535 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 536 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 537 538 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 539 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 540 541 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 542 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 543 544 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 545 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 546 547 /*@} end of group CMSIS_SCB */ 548 549 550 /** 551 \ingroup CMSIS_core_register 552 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 553 \brief Type definitions for the System Timer Registers. 554 @{ 555 */ 556 557 /** 558 \brief Structure type to access the System Timer (SysTick). 559 */ 560 typedef struct 561 { 562 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 563 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 564 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 565 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 566 } SysTick_Type; 567 568 /* SysTick Control / Status Register Definitions */ 569 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 570 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 571 572 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 573 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 574 575 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 576 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 577 578 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 579 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 580 581 /* SysTick Reload Register Definitions */ 582 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 583 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 584 585 /* SysTick Current Register Definitions */ 586 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 587 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 588 589 /* SysTick Calibration Register Definitions */ 590 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 591 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 592 593 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 594 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 595 596 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 597 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 598 599 /*@} end of group CMSIS_SysTick */ 600 601 602 /** 603 \ingroup CMSIS_core_register 604 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 605 \brief Type definitions for the Data Watchpoint and Trace (DWT) 606 @{ 607 */ 608 609 /** 610 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 611 */ 612 typedef struct 613 { 614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 615 uint32_t RESERVED0[6U]; 616 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 617 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 618 uint32_t RESERVED1[1U]; 619 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 620 uint32_t RESERVED2[1U]; 621 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 622 uint32_t RESERVED3[1U]; 623 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 624 uint32_t RESERVED4[1U]; 625 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 626 uint32_t RESERVED5[1U]; 627 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 628 uint32_t RESERVED6[1U]; 629 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 630 uint32_t RESERVED7[1U]; 631 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 632 uint32_t RESERVED8[1U]; 633 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 634 uint32_t RESERVED9[1U]; 635 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 636 uint32_t RESERVED10[1U]; 637 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 638 uint32_t RESERVED11[1U]; 639 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 640 uint32_t RESERVED12[1U]; 641 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 642 uint32_t RESERVED13[1U]; 643 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 644 uint32_t RESERVED14[1U]; 645 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 646 uint32_t RESERVED15[1U]; 647 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 648 uint32_t RESERVED16[1U]; 649 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 650 uint32_t RESERVED17[1U]; 651 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 652 uint32_t RESERVED18[1U]; 653 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 654 uint32_t RESERVED19[1U]; 655 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 656 uint32_t RESERVED20[1U]; 657 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 658 uint32_t RESERVED21[1U]; 659 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 660 uint32_t RESERVED22[1U]; 661 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 662 uint32_t RESERVED23[1U]; 663 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 664 uint32_t RESERVED24[1U]; 665 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 666 uint32_t RESERVED25[1U]; 667 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 668 uint32_t RESERVED26[1U]; 669 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 670 uint32_t RESERVED27[1U]; 671 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 672 uint32_t RESERVED28[1U]; 673 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 674 uint32_t RESERVED29[1U]; 675 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 676 uint32_t RESERVED30[1U]; 677 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 678 uint32_t RESERVED31[1U]; 679 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 680 } DWT_Type; 681 682 /* DWT Control Register Definitions */ 683 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 684 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 685 686 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 687 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 688 689 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 690 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 691 692 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 693 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 694 695 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 696 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 697 698 /* DWT Comparator Function Register Definitions */ 699 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 700 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 701 702 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 703 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 704 705 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 706 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 707 708 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 709 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 710 711 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 712 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 713 714 /*@}*/ /* end of group CMSIS_DWT */ 715 716 717 /** 718 \ingroup CMSIS_core_register 719 \defgroup CMSIS_TPI Trace Port Interface (TPI) 720 \brief Type definitions for the Trace Port Interface (TPI) 721 @{ 722 */ 723 724 /** 725 \brief Structure type to access the Trace Port Interface Register (TPI). 726 */ 727 typedef struct 728 { 729 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ 730 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ 731 uint32_t RESERVED0[2U]; 732 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 733 uint32_t RESERVED1[55U]; 734 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 735 uint32_t RESERVED2[131U]; 736 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 737 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 738 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 739 uint32_t RESERVED3[809U]; 740 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ 741 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ 742 uint32_t RESERVED4[4U]; 743 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ 744 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ 745 } TPI_Type; 746 747 /* TPI Asynchronous Clock Prescaler Register Definitions */ 748 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ 749 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ 750 751 /* TPI Selected Pin Protocol Register Definitions */ 752 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 753 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 754 755 /* TPI Formatter and Flush Status Register Definitions */ 756 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 757 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 758 759 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 760 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 761 762 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 763 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 764 765 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 766 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 767 768 /* TPI Formatter and Flush Control Register Definitions */ 769 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 770 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 771 772 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 773 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 774 775 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 776 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 777 778 /* TPI Periodic Synchronization Control Register Definitions */ 779 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ 780 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ 781 782 /* TPI Software Lock Status Register Definitions */ 783 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ 784 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ 785 786 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ 787 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ 788 789 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ 790 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ 791 792 /* TPI DEVID Register Definitions */ 793 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 794 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 795 796 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 797 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 798 799 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 800 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 801 802 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ 803 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ 804 805 /* TPI DEVTYPE Register Definitions */ 806 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 807 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 808 809 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 810 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 811 812 /*@}*/ /* end of group CMSIS_TPI */ 813 814 815 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 816 /** 817 \ingroup CMSIS_core_register 818 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 819 \brief Type definitions for the Memory Protection Unit (MPU) 820 @{ 821 */ 822 823 /** 824 \brief Structure type to access the Memory Protection Unit (MPU). 825 */ 826 typedef struct 827 { 828 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 829 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 830 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 831 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 832 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 833 uint32_t RESERVED0[7U]; 834 union { 835 __IOM uint32_t MAIR[2]; 836 struct { 837 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 838 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 839 }; 840 }; 841 } MPU_Type; 842 843 #define MPU_TYPE_RALIASES 1U 844 845 /* MPU Type Register Definitions */ 846 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 847 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 848 849 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 850 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 851 852 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 853 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 854 855 /* MPU Control Register Definitions */ 856 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 857 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 858 859 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 860 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 861 862 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 863 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 864 865 /* MPU Region Number Register Definitions */ 866 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 867 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 868 869 /* MPU Region Base Address Register Definitions */ 870 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 871 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 872 873 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 874 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 875 876 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 877 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 878 879 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 880 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 881 882 /* MPU Region Limit Address Register Definitions */ 883 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 884 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 885 886 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 887 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 888 889 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ 890 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ 891 892 /* MPU Memory Attribute Indirection Register 0 Definitions */ 893 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 894 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 895 896 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 897 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 898 899 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 900 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 901 902 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 903 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 904 905 /* MPU Memory Attribute Indirection Register 1 Definitions */ 906 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 907 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 908 909 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 910 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 911 912 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 913 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 914 915 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 916 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 917 918 /*@} end of group CMSIS_MPU */ 919 #endif 920 921 922 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 923 /** 924 \ingroup CMSIS_core_register 925 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 926 \brief Type definitions for the Security Attribution Unit (SAU) 927 @{ 928 */ 929 930 /** 931 \brief Structure type to access the Security Attribution Unit (SAU). 932 */ 933 typedef struct 934 { 935 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 936 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 937 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 938 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 939 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 940 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 941 #endif 942 } SAU_Type; 943 944 /* SAU Control Register Definitions */ 945 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 946 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 947 948 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 949 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 950 951 /* SAU Type Register Definitions */ 952 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 953 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 954 955 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 956 /* SAU Region Number Register Definitions */ 957 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 958 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 959 960 /* SAU Region Base Address Register Definitions */ 961 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 962 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 963 964 /* SAU Region Limit Address Register Definitions */ 965 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 966 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 967 968 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 969 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 970 971 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 972 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 973 974 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 975 976 /*@} end of group CMSIS_SAU */ 977 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 978 979 980 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ 981 /** 982 \ingroup CMSIS_core_register 983 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 984 \brief Type definitions for the Core Debug Registers 985 @{ 986 */ 987 988 /** 989 \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). 990 */ 991 typedef struct 992 { 993 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 994 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 995 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 996 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 997 uint32_t RESERVED0[1U]; 998 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 999 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 1000 } CoreDebug_Type; 1001 1002 /* Debug Halting Control and Status Register Definitions */ 1003 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ 1004 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ 1005 1006 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ 1007 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ 1008 1009 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ 1010 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ 1011 1012 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ 1013 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ 1014 1015 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ 1016 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ 1017 1018 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ 1019 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ 1020 1021 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ 1022 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ 1023 1024 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ 1025 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ 1026 1027 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ 1028 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ 1029 1030 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ 1031 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ 1032 1033 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ 1034 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ 1035 1036 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ 1037 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ 1038 1039 /* Debug Core Register Selector Register Definitions */ 1040 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ 1041 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ 1042 1043 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ 1044 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ 1045 1046 /* Debug Exception and Monitor Control Register Definitions */ 1047 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ 1048 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ 1049 1050 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ 1051 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ 1052 1053 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ 1054 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ 1055 1056 /* Debug Authentication Control Register Definitions */ 1057 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 1058 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 1059 1060 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 1061 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 1062 1063 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ 1064 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 1065 1066 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ 1067 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 1068 1069 /* Debug Security Control and Status Register Definitions */ 1070 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ 1071 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ 1072 1073 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ 1074 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ 1075 1076 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ 1077 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ 1078 1079 /*@} end of group CMSIS_CoreDebug */ 1080 1081 1082 /** 1083 \ingroup CMSIS_core_register 1084 \defgroup CMSIS_DCB Debug Control Block 1085 \brief Type definitions for the Debug Control Block Registers 1086 @{ 1087 */ 1088 1089 /** 1090 \brief Structure type to access the Debug Control Block Registers (DCB). 1091 */ 1092 typedef struct 1093 { 1094 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1095 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1096 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1097 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1098 uint32_t RESERVED0[1U]; 1099 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 1100 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 1101 } DCB_Type; 1102 1103 /* DHCSR, Debug Halting Control and Status Register Definitions */ 1104 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ 1105 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ 1106 1107 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ 1108 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ 1109 1110 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ 1111 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ 1112 1113 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ 1114 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ 1115 1116 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ 1117 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ 1118 1119 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ 1120 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ 1121 1122 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ 1123 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ 1124 1125 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ 1126 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ 1127 1128 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ 1129 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ 1130 1131 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ 1132 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ 1133 1134 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ 1135 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ 1136 1137 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ 1138 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ 1139 1140 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ 1141 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ 1142 1143 /* DCRSR, Debug Core Register Select Register Definitions */ 1144 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ 1145 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ 1146 1147 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ 1148 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ 1149 1150 /* DCRDR, Debug Core Register Data Register Definitions */ 1151 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ 1152 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ 1153 1154 /* DEMCR, Debug Exception and Monitor Control Register Definitions */ 1155 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ 1156 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ 1157 1158 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ 1159 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ 1160 1161 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ 1162 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ 1163 1164 /* DAUTHCTRL, Debug Authentication Control Register Definitions */ 1165 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ 1166 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ 1167 1168 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ 1169 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ 1170 1171 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ 1172 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ 1173 1174 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ 1175 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ 1176 1177 /* DSCSR, Debug Security Control and Status Register Definitions */ 1178 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ 1179 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ 1180 1181 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ 1182 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ 1183 1184 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ 1185 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ 1186 1187 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ 1188 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ 1189 1190 /*@} end of group CMSIS_DCB */ 1191 1192 1193 1194 /** 1195 \ingroup CMSIS_core_register 1196 \defgroup CMSIS_DIB Debug Identification Block 1197 \brief Type definitions for the Debug Identification Block Registers 1198 @{ 1199 */ 1200 1201 /** 1202 \brief Structure type to access the Debug Identification Block Registers (DIB). 1203 */ 1204 typedef struct 1205 { 1206 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ 1207 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ 1208 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ 1209 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ 1210 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ 1211 } DIB_Type; 1212 1213 /* DLAR, SCS Software Lock Access Register Definitions */ 1214 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ 1215 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ 1216 1217 /* DLSR, SCS Software Lock Status Register Definitions */ 1218 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ 1219 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ 1220 1221 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ 1222 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ 1223 1224 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ 1225 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ 1226 1227 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */ 1228 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ 1229 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ 1230 1231 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ 1232 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ 1233 1234 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ 1235 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ 1236 1237 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ 1238 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ 1239 1240 /* DDEVARCH, SCS Device Architecture Register Definitions */ 1241 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ 1242 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ 1243 1244 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ 1245 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ 1246 1247 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ 1248 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ 1249 1250 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ 1251 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ 1252 1253 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ 1254 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ 1255 1256 /* DDEVTYPE, SCS Device Type Register Definitions */ 1257 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ 1258 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ 1259 1260 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ 1261 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ 1262 1263 1264 /*@} end of group CMSIS_DIB */ 1265 1266 1267 /** 1268 \ingroup CMSIS_core_register 1269 \defgroup CMSIS_core_bitfield Core register bit field macros 1270 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1271 @{ 1272 */ 1273 1274 /** 1275 \brief Mask and shift a bit field value for use in a register bit range. 1276 \param[in] field Name of the register bit field. 1277 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1278 \return Masked and shifted value. 1279 */ 1280 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1281 1282 /** 1283 \brief Mask and shift a register value to extract a bit filed value. 1284 \param[in] field Name of the register bit field. 1285 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1286 \return Masked and shifted bit field value. 1287 */ 1288 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1289 1290 /*@} end of group CMSIS_core_bitfield */ 1291 1292 1293 /** 1294 \ingroup CMSIS_core_register 1295 \defgroup CMSIS_core_base Core Definitions 1296 \brief Definitions for base addresses, unions, and structures. 1297 @{ 1298 */ 1299 1300 /* Memory mapping of Core Hardware */ 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1302 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1303 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1304 #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ 1305 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ 1306 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ 1307 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1308 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1309 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1310 1311 1312 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1313 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1314 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ 1318 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ 1319 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ 1320 1321 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1322 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1323 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1324 #endif 1325 1326 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1327 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 1328 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 1329 #endif 1330 1331 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1332 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 1333 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ 1334 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ 1335 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ 1336 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 1337 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 1338 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 1339 1340 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 1341 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 1342 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 1343 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ 1344 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ 1345 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ 1346 1347 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1348 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 1349 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 1350 #endif 1351 1352 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1353 /*@} */ 1354 1355 1356 1357 /******************************************************************************* 1358 * Hardware Abstraction Layer 1359 Core Function Interface contains: 1360 - Core NVIC Functions 1361 - Core SysTick Functions 1362 - Core Debug Functions 1363 - Core Register Access Functions 1364 ******************************************************************************/ 1365 /** 1366 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1367 */ 1368 1369 1370 1371 /* ########################## NVIC functions #################################### */ 1372 /** 1373 \ingroup CMSIS_Core_FunctionInterface 1374 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1375 \brief Functions that manage interrupts and exceptions via the NVIC. 1376 @{ 1377 */ 1378 1379 #ifdef CMSIS_NVIC_VIRTUAL 1380 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1381 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1382 #endif 1383 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1384 #else 1385 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1386 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1387 #define NVIC_EnableIRQ __NVIC_EnableIRQ 1388 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1389 #define NVIC_DisableIRQ __NVIC_DisableIRQ 1390 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1391 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1392 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1393 #define NVIC_GetActive __NVIC_GetActive 1394 #define NVIC_SetPriority __NVIC_SetPriority 1395 #define NVIC_GetPriority __NVIC_GetPriority 1396 #define NVIC_SystemReset __NVIC_SystemReset 1397 #endif /* CMSIS_NVIC_VIRTUAL */ 1398 1399 #ifdef CMSIS_VECTAB_VIRTUAL 1400 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1401 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1402 #endif 1403 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1404 #else 1405 #define NVIC_SetVector __NVIC_SetVector 1406 #define NVIC_GetVector __NVIC_GetVector 1407 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1408 1409 #define NVIC_USER_IRQ_OFFSET 16 1410 1411 1412 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 1413 1414 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 1415 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 1416 1417 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 1418 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 1419 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 1420 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 1421 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 1422 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 1423 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ 1424 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 1425 1426 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 1427 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 1428 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 1429 #else 1430 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 1431 #endif 1432 1433 1434 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 1435 /* The following MACROS handle generation of the register offset and byte masks */ 1436 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 1437 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 1438 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 1439 1440 #define __NVIC_SetPriorityGrouping(X) (void)(X) 1441 #define __NVIC_GetPriorityGrouping() (0U) 1442 1443 /** 1444 \brief Enable Interrupt 1445 \details Enables a device specific interrupt in the NVIC interrupt controller. 1446 \param [in] IRQn Device specific interrupt number. 1447 \note IRQn must not be negative. 1448 */ 1449 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1450 { 1451 if ((int32_t)(IRQn) >= 0) 1452 { 1453 __COMPILER_BARRIER(); 1454 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1455 __COMPILER_BARRIER(); 1456 } 1457 } 1458 1459 1460 /** 1461 \brief Get Interrupt Enable status 1462 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1463 \param [in] IRQn Device specific interrupt number. 1464 \return 0 Interrupt is not enabled. 1465 \return 1 Interrupt is enabled. 1466 \note IRQn must not be negative. 1467 */ 1468 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1469 { 1470 if ((int32_t)(IRQn) >= 0) 1471 { 1472 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1473 } 1474 else 1475 { 1476 return(0U); 1477 } 1478 } 1479 1480 1481 /** 1482 \brief Disable Interrupt 1483 \details Disables a device specific interrupt in the NVIC interrupt controller. 1484 \param [in] IRQn Device specific interrupt number. 1485 \note IRQn must not be negative. 1486 */ 1487 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1488 { 1489 if ((int32_t)(IRQn) >= 0) 1490 { 1491 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1492 __DSB(); 1493 __ISB(); 1494 } 1495 } 1496 1497 1498 /** 1499 \brief Get Pending Interrupt 1500 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 1501 \param [in] IRQn Device specific interrupt number. 1502 \return 0 Interrupt status is not pending. 1503 \return 1 Interrupt status is pending. 1504 \note IRQn must not be negative. 1505 */ 1506 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1507 { 1508 if ((int32_t)(IRQn) >= 0) 1509 { 1510 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1511 } 1512 else 1513 { 1514 return(0U); 1515 } 1516 } 1517 1518 1519 /** 1520 \brief Set Pending Interrupt 1521 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1522 \param [in] IRQn Device specific interrupt number. 1523 \note IRQn must not be negative. 1524 */ 1525 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1526 { 1527 if ((int32_t)(IRQn) >= 0) 1528 { 1529 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1530 } 1531 } 1532 1533 1534 /** 1535 \brief Clear Pending Interrupt 1536 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1537 \param [in] IRQn Device specific interrupt number. 1538 \note IRQn must not be negative. 1539 */ 1540 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1541 { 1542 if ((int32_t)(IRQn) >= 0) 1543 { 1544 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1545 } 1546 } 1547 1548 1549 /** 1550 \brief Get Active Interrupt 1551 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 1552 \param [in] IRQn Device specific interrupt number. 1553 \return 0 Interrupt status is not active. 1554 \return 1 Interrupt status is active. 1555 \note IRQn must not be negative. 1556 */ 1557 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1558 { 1559 if ((int32_t)(IRQn) >= 0) 1560 { 1561 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1562 } 1563 else 1564 { 1565 return(0U); 1566 } 1567 } 1568 1569 1570 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1571 /** 1572 \brief Get Interrupt Target State 1573 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1574 \param [in] IRQn Device specific interrupt number. 1575 \return 0 if interrupt is assigned to Secure 1576 \return 1 if interrupt is assigned to Non Secure 1577 \note IRQn must not be negative. 1578 */ 1579 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 1580 { 1581 if ((int32_t)(IRQn) >= 0) 1582 { 1583 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1584 } 1585 else 1586 { 1587 return(0U); 1588 } 1589 } 1590 1591 1592 /** 1593 \brief Set Interrupt Target State 1594 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1595 \param [in] IRQn Device specific interrupt number. 1596 \return 0 if interrupt is assigned to Secure 1597 1 if interrupt is assigned to Non Secure 1598 \note IRQn must not be negative. 1599 */ 1600 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 1601 { 1602 if ((int32_t)(IRQn) >= 0) 1603 { 1604 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 1605 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1606 } 1607 else 1608 { 1609 return(0U); 1610 } 1611 } 1612 1613 1614 /** 1615 \brief Clear Interrupt Target State 1616 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1617 \param [in] IRQn Device specific interrupt number. 1618 \return 0 if interrupt is assigned to Secure 1619 1 if interrupt is assigned to Non Secure 1620 \note IRQn must not be negative. 1621 */ 1622 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 1623 { 1624 if ((int32_t)(IRQn) >= 0) 1625 { 1626 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 1627 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1628 } 1629 else 1630 { 1631 return(0U); 1632 } 1633 } 1634 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1635 1636 1637 /** 1638 \brief Set Interrupt Priority 1639 \details Sets the priority of a device specific interrupt or a processor exception. 1640 The interrupt number can be positive to specify a device specific interrupt, 1641 or negative to specify a processor exception. 1642 \param [in] IRQn Interrupt number. 1643 \param [in] priority Priority to set. 1644 \note The priority cannot be set for every processor exception. 1645 */ 1646 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1647 { 1648 if ((int32_t)(IRQn) >= 0) 1649 { 1650 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1651 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1652 } 1653 else 1654 { 1655 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1656 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1657 } 1658 } 1659 1660 1661 /** 1662 \brief Get Interrupt Priority 1663 \details Reads the priority of a device specific interrupt or a processor exception. 1664 The interrupt number can be positive to specify a device specific interrupt, 1665 or negative to specify a processor exception. 1666 \param [in] IRQn Interrupt number. 1667 \return Interrupt Priority. 1668 Value is aligned automatically to the implemented priority bits of the microcontroller. 1669 */ 1670 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1671 { 1672 1673 if ((int32_t)(IRQn) >= 0) 1674 { 1675 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1676 } 1677 else 1678 { 1679 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1680 } 1681 } 1682 1683 1684 /** 1685 \brief Encode Priority 1686 \details Encodes the priority for an interrupt with the given priority group, 1687 preemptive priority value, and subpriority value. 1688 In case of a conflict between priority grouping and available 1689 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1690 \param [in] PriorityGroup Used priority group. 1691 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1692 \param [in] SubPriority Subpriority value (starting from 0). 1693 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1694 */ 1695 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 1696 { 1697 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1698 uint32_t PreemptPriorityBits; 1699 uint32_t SubPriorityBits; 1700 1701 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 1702 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1703 1704 return ( 1705 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 1706 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 1707 ); 1708 } 1709 1710 1711 /** 1712 \brief Decode Priority 1713 \details Decodes an interrupt priority value with a given priority group to 1714 preemptive priority value and subpriority value. 1715 In case of a conflict between priority grouping and available 1716 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1717 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1718 \param [in] PriorityGroup Used priority group. 1719 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1720 \param [out] pSubPriority Subpriority value (starting from 0). 1721 */ 1722 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 1723 { 1724 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1725 uint32_t PreemptPriorityBits; 1726 uint32_t SubPriorityBits; 1727 1728 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 1729 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1730 1731 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 1732 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 1733 } 1734 1735 1736 /** 1737 \brief Set Interrupt Vector 1738 \details Sets an interrupt vector in SRAM based interrupt vector table. 1739 The interrupt number can be positive to specify a device specific interrupt, 1740 or negative to specify a processor exception. 1741 VTOR must been relocated to SRAM before. 1742 If VTOR is not present address 0 must be mapped to SRAM. 1743 \param [in] IRQn Interrupt number 1744 \param [in] vector Address of interrupt handler function 1745 */ 1746 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 1747 { 1748 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 1749 uint32_t *vectors = (uint32_t *)SCB->VTOR; 1750 #else 1751 uint32_t *vectors = (uint32_t *)0x0U; 1752 #endif 1753 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 1754 __DSB(); 1755 } 1756 1757 1758 /** 1759 \brief Get Interrupt Vector 1760 \details Reads an interrupt vector from interrupt vector table. 1761 The interrupt number can be positive to specify a device specific interrupt, 1762 or negative to specify a processor exception. 1763 \param [in] IRQn Interrupt number. 1764 \return Address of interrupt handler function 1765 */ 1766 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 1767 { 1768 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 1769 uint32_t *vectors = (uint32_t *)SCB->VTOR; 1770 #else 1771 uint32_t *vectors = (uint32_t *)0x0U; 1772 #endif 1773 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 1774 } 1775 1776 1777 /** 1778 \brief System Reset 1779 \details Initiates a system reset request to reset the MCU. 1780 */ 1781 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 1782 { 1783 __DSB(); /* Ensure all outstanding memory accesses included 1784 buffered write are completed before reset */ 1785 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1786 SCB_AIRCR_SYSRESETREQ_Msk); 1787 __DSB(); /* Ensure completion of memory access */ 1788 1789 for(;;) /* wait until reset */ 1790 { 1791 __NOP(); 1792 } 1793 } 1794 1795 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1796 /** 1797 \brief Enable Interrupt (non-secure) 1798 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 1799 \param [in] IRQn Device specific interrupt number. 1800 \note IRQn must not be negative. 1801 */ 1802 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 1803 { 1804 if ((int32_t)(IRQn) >= 0) 1805 { 1806 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1807 } 1808 } 1809 1810 1811 /** 1812 \brief Get Interrupt Enable status (non-secure) 1813 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 1814 \param [in] IRQn Device specific interrupt number. 1815 \return 0 Interrupt is not enabled. 1816 \return 1 Interrupt is enabled. 1817 \note IRQn must not be negative. 1818 */ 1819 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 1820 { 1821 if ((int32_t)(IRQn) >= 0) 1822 { 1823 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1824 } 1825 else 1826 { 1827 return(0U); 1828 } 1829 } 1830 1831 1832 /** 1833 \brief Disable Interrupt (non-secure) 1834 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 1835 \param [in] IRQn Device specific interrupt number. 1836 \note IRQn must not be negative. 1837 */ 1838 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 1839 { 1840 if ((int32_t)(IRQn) >= 0) 1841 { 1842 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1843 } 1844 } 1845 1846 1847 /** 1848 \brief Get Pending Interrupt (non-secure) 1849 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 1850 \param [in] IRQn Device specific interrupt number. 1851 \return 0 Interrupt status is not pending. 1852 \return 1 Interrupt status is pending. 1853 \note IRQn must not be negative. 1854 */ 1855 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 1856 { 1857 if ((int32_t)(IRQn) >= 0) 1858 { 1859 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1860 } 1861 else 1862 { 1863 return(0U); 1864 } 1865 } 1866 1867 1868 /** 1869 \brief Set Pending Interrupt (non-secure) 1870 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 1871 \param [in] IRQn Device specific interrupt number. 1872 \note IRQn must not be negative. 1873 */ 1874 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 1875 { 1876 if ((int32_t)(IRQn) >= 0) 1877 { 1878 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1879 } 1880 } 1881 1882 1883 /** 1884 \brief Clear Pending Interrupt (non-secure) 1885 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 1886 \param [in] IRQn Device specific interrupt number. 1887 \note IRQn must not be negative. 1888 */ 1889 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 1890 { 1891 if ((int32_t)(IRQn) >= 0) 1892 { 1893 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1894 } 1895 } 1896 1897 1898 /** 1899 \brief Get Active Interrupt (non-secure) 1900 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 1901 \param [in] IRQn Device specific interrupt number. 1902 \return 0 Interrupt status is not active. 1903 \return 1 Interrupt status is active. 1904 \note IRQn must not be negative. 1905 */ 1906 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 1907 { 1908 if ((int32_t)(IRQn) >= 0) 1909 { 1910 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1911 } 1912 else 1913 { 1914 return(0U); 1915 } 1916 } 1917 1918 1919 /** 1920 \brief Set Interrupt Priority (non-secure) 1921 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 1922 The interrupt number can be positive to specify a device specific interrupt, 1923 or negative to specify a processor exception. 1924 \param [in] IRQn Interrupt number. 1925 \param [in] priority Priority to set. 1926 \note The priority cannot be set for every non-secure processor exception. 1927 */ 1928 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 1929 { 1930 if ((int32_t)(IRQn) >= 0) 1931 { 1932 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1933 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1934 } 1935 else 1936 { 1937 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1938 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1939 } 1940 } 1941 1942 1943 /** 1944 \brief Get Interrupt Priority (non-secure) 1945 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 1946 The interrupt number can be positive to specify a device specific interrupt, 1947 or negative to specify a processor exception. 1948 \param [in] IRQn Interrupt number. 1949 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 1950 */ 1951 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 1952 { 1953 1954 if ((int32_t)(IRQn) >= 0) 1955 { 1956 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1957 } 1958 else 1959 { 1960 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1961 } 1962 } 1963 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 1964 1965 /*@} end of CMSIS_Core_NVICFunctions */ 1966 1967 /* ########################## MPU functions #################################### */ 1968 1969 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1970 1971 #include "mpu_armv8.h" 1972 1973 #endif 1974 1975 /* ########################## FPU functions #################################### */ 1976 /** 1977 \ingroup CMSIS_Core_FunctionInterface 1978 \defgroup CMSIS_Core_FpuFunctions FPU Functions 1979 \brief Function that provides FPU type. 1980 @{ 1981 */ 1982 1983 /** 1984 \brief get FPU type 1985 \details returns the FPU type 1986 \returns 1987 - \b 0: No FPU 1988 - \b 1: Single precision FPU 1989 - \b 2: Double + Single precision FPU 1990 */ 1991 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 1992 { 1993 return 0U; /* No FPU */ 1994 } 1995 1996 1997 /*@} end of CMSIS_Core_FpuFunctions */ 1998 1999 2000 2001 /* ########################## SAU functions #################################### */ 2002 /** 2003 \ingroup CMSIS_Core_FunctionInterface 2004 \defgroup CMSIS_Core_SAUFunctions SAU Functions 2005 \brief Functions that configure the SAU. 2006 @{ 2007 */ 2008 2009 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2010 2011 /** 2012 \brief Enable SAU 2013 \details Enables the Security Attribution Unit (SAU). 2014 */ 2015 __STATIC_INLINE void TZ_SAU_Enable(void) 2016 { 2017 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 2018 } 2019 2020 2021 2022 /** 2023 \brief Disable SAU 2024 \details Disables the Security Attribution Unit (SAU). 2025 */ 2026 __STATIC_INLINE void TZ_SAU_Disable(void) 2027 { 2028 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 2029 } 2030 2031 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 2032 2033 /*@} end of CMSIS_Core_SAUFunctions */ 2034 2035 2036 2037 2038 /* ################################## Debug Control function ############################################ */ 2039 /** 2040 \ingroup CMSIS_Core_FunctionInterface 2041 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions 2042 \brief Functions that access the Debug Control Block. 2043 @{ 2044 */ 2045 2046 2047 /** 2048 \brief Set Debug Authentication Control Register 2049 \details writes to Debug Authentication Control register. 2050 \param [in] value value to be writen. 2051 */ 2052 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) 2053 { 2054 __DSB(); 2055 __ISB(); 2056 DCB->DAUTHCTRL = value; 2057 __DSB(); 2058 __ISB(); 2059 } 2060 2061 2062 /** 2063 \brief Get Debug Authentication Control Register 2064 \details Reads Debug Authentication Control register. 2065 \return Debug Authentication Control Register. 2066 */ 2067 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) 2068 { 2069 return (DCB->DAUTHCTRL); 2070 } 2071 2072 2073 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2074 /** 2075 \brief Set Debug Authentication Control Register (non-secure) 2076 \details writes to non-secure Debug Authentication Control register when in secure state. 2077 \param [in] value value to be writen 2078 */ 2079 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) 2080 { 2081 __DSB(); 2082 __ISB(); 2083 DCB_NS->DAUTHCTRL = value; 2084 __DSB(); 2085 __ISB(); 2086 } 2087 2088 2089 /** 2090 \brief Get Debug Authentication Control Register (non-secure) 2091 \details Reads non-secure Debug Authentication Control register when in secure state. 2092 \return Debug Authentication Control Register. 2093 */ 2094 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) 2095 { 2096 return (DCB_NS->DAUTHCTRL); 2097 } 2098 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 2099 2100 /*@} end of CMSIS_Core_DCBFunctions */ 2101 2102 2103 2104 2105 /* ################################## Debug Identification function ############################################ */ 2106 /** 2107 \ingroup CMSIS_Core_FunctionInterface 2108 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions 2109 \brief Functions that access the Debug Identification Block. 2110 @{ 2111 */ 2112 2113 2114 /** 2115 \brief Get Debug Authentication Status Register 2116 \details Reads Debug Authentication Status register. 2117 \return Debug Authentication Status Register. 2118 */ 2119 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void) 2120 { 2121 return (DIB->DAUTHSTATUS); 2122 } 2123 2124 2125 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2126 /** 2127 \brief Get Debug Authentication Status Register (non-secure) 2128 \details Reads non-secure Debug Authentication Status register when in secure state. 2129 \return Debug Authentication Status Register. 2130 */ 2131 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) 2132 { 2133 return (DIB_NS->DAUTHSTATUS); 2134 } 2135 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 2136 2137 /*@} end of CMSIS_Core_DCBFunctions */ 2138 2139 2140 2141 2142 /* ################################## SysTick function ############################################ */ 2143 /** 2144 \ingroup CMSIS_Core_FunctionInterface 2145 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 2146 \brief Functions that configure the System. 2147 @{ 2148 */ 2149 2150 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 2151 2152 /** 2153 \brief System Tick Configuration 2154 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 2155 Counter is in free running mode to generate periodic interrupts. 2156 \param [in] ticks Number of ticks between two interrupts. 2157 \return 0 Function succeeded. 2158 \return 1 Function failed. 2159 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 2160 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 2161 must contain a vendor-specific implementation of this function. 2162 */ 2163 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 2164 { 2165 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 2166 { 2167 return (1UL); /* Reload value impossible */ 2168 } 2169 2170 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 2171 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 2172 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 2173 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 2174 SysTick_CTRL_TICKINT_Msk | 2175 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 2176 return (0UL); /* Function successful */ 2177 } 2178 2179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2180 /** 2181 \brief System Tick Configuration (non-secure) 2182 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 2183 Counter is in free running mode to generate periodic interrupts. 2184 \param [in] ticks Number of ticks between two interrupts. 2185 \return 0 Function succeeded. 2186 \return 1 Function failed. 2187 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 2188 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 2189 must contain a vendor-specific implementation of this function. 2190 2191 */ 2192 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 2193 { 2194 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 2195 { 2196 return (1UL); /* Reload value impossible */ 2197 } 2198 2199 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 2200 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 2201 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 2202 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 2203 SysTick_CTRL_TICKINT_Msk | 2204 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 2205 return (0UL); /* Function successful */ 2206 } 2207 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 2208 2209 #endif 2210 2211 /*@} end of CMSIS_Core_SysTickFunctions */ 2212 2213 2214 2215 2216 #ifdef __cplusplus 2217 } 2218 #endif 2219 2220 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ 2221 2222 #endif /* __CMSIS_GENERIC */