core_cm3.h
1 /**************************************************************************//** 2 * @file core_cm3.h 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File 4 * @version V5.1.2 5 * @date 04. June 2021 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2021 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_CM3_H_GENERIC 32 #define __CORE_CM3_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 55 /******************************************************************************* 56 * CMSIS definitions 57 ******************************************************************************/ 58 /** 59 \ingroup Cortex_M3 60 @{ 61 */ 62 63 #include "cmsis_version.h" 64 65 /* CMSIS CM3 definitions */ 66 #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 67 #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 68 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ 69 __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 70 71 #define __CORTEX_M (3U) /*!< Cortex-M Core */ 72 73 /** __FPU_USED indicates whether an FPU is used or not. 74 This core does not support an FPU at all 75 */ 76 #define __FPU_USED 0U 77 78 #if defined ( __CC_ARM ) 79 #if defined __TARGET_FPU_VFP 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 81 #endif 82 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 84 #if defined __ARM_FP 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 86 #endif 87 88 #elif defined ( __GNUC__ ) 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 91 #endif 92 93 #elif defined ( __ICCARM__ ) 94 #if defined __ARMVFP__ 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 96 #endif 97 98 #elif defined ( __TI_ARM__ ) 99 #if defined __TI_VFP_SUPPORT__ 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 101 #endif 102 103 #elif defined ( __TASKING__ ) 104 #if defined __FPU_VFP__ 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 106 #endif 107 108 #elif defined ( __CSMC__ ) 109 #if ( __CSMC__ & 0x400U) 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 111 #endif 112 113 #endif 114 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 116 117 118 #ifdef __cplusplus 119 } 120 #endif 121 122 #endif /* __CORE_CM3_H_GENERIC */ 123 124 #ifndef __CMSIS_GENERIC 125 126 #ifndef __CORE_CM3_H_DEPENDANT 127 #define __CORE_CM3_H_DEPENDANT 128 129 #ifdef __cplusplus 130 extern "C" { 131 #endif 132 133 /* check device defines and use defaults */ 134 #if defined __CHECK_DEVICE_DEFINES 135 #ifndef __CM3_REV 136 #define __CM3_REV 0x0200U 137 #warning "__CM3_REV not defined in device header file; using default!" 138 #endif 139 140 #ifndef __MPU_PRESENT 141 #define __MPU_PRESENT 0U 142 #warning "__MPU_PRESENT not defined in device header file; using default!" 143 #endif 144 145 #ifndef __VTOR_PRESENT 146 #define __VTOR_PRESENT 1U 147 #warning "__VTOR_PRESENT not defined in device header file; using default!" 148 #endif 149 150 #ifndef __NVIC_PRIO_BITS 151 #define __NVIC_PRIO_BITS 3U 152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 153 #endif 154 155 #ifndef __Vendor_SysTickConfig 156 #define __Vendor_SysTickConfig 0U 157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 158 #endif 159 #endif 160 161 /* IO definitions (access restrictions to peripheral registers) */ 162 /** 163 \defgroup CMSIS_glob_defs CMSIS Global Defines 164 165 <strong>IO Type Qualifiers</strong> are used 166 \li to specify the access to peripheral variables. 167 \li for automatic generation of peripheral register debug information. 168 */ 169 #ifdef __cplusplus 170 #define __I volatile /*!< Defines 'read only' permissions */ 171 #else 172 #define __I volatile const /*!< Defines 'read only' permissions */ 173 #endif 174 #define __O volatile /*!< Defines 'write only' permissions */ 175 #define __IO volatile /*!< Defines 'read / write' permissions */ 176 177 /* following defines should be used for structure members */ 178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 179 #define __OM volatile /*! Defines 'write only' structure member permissions */ 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 181 182 /*@} end of group Cortex_M3 */ 183 184 185 186 /******************************************************************************* 187 * Register Abstraction 188 Core Register contain: 189 - Core Register 190 - Core NVIC Register 191 - Core SCB Register 192 - Core SysTick Register 193 - Core Debug Register 194 - Core MPU Register 195 ******************************************************************************/ 196 /** 197 \defgroup CMSIS_core_register Defines and Type Definitions 198 \brief Type definitions and defines for Cortex-M processor based devices. 199 */ 200 201 /** 202 \ingroup CMSIS_core_register 203 \defgroup CMSIS_CORE Status and Control Registers 204 \brief Core Register type definitions. 205 @{ 206 */ 207 208 /** 209 \brief Union type to access the Application Program Status Register (APSR). 210 */ 211 typedef union 212 { 213 struct 214 { 215 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 216 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 217 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 218 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 219 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 220 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 221 } b; /*!< Structure used for bit access */ 222 uint32_t w; /*!< Type used for word access */ 223 } APSR_Type; 224 225 /* APSR Register Definitions */ 226 #define APSR_N_Pos 31U /*!< APSR: N Position */ 227 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 228 229 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 230 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 231 232 #define APSR_C_Pos 29U /*!< APSR: C Position */ 233 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 234 235 #define APSR_V_Pos 28U /*!< APSR: V Position */ 236 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 237 238 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 239 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 240 241 242 /** 243 \brief Union type to access the Interrupt Program Status Register (IPSR). 244 */ 245 typedef union 246 { 247 struct 248 { 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 250 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 251 } b; /*!< Structure used for bit access */ 252 uint32_t w; /*!< Type used for word access */ 253 } IPSR_Type; 254 255 /* IPSR Register Definitions */ 256 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 257 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 258 259 260 /** 261 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 262 */ 263 typedef union 264 { 265 struct 266 { 267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 268 uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 269 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 270 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ 271 uint32_t T:1; /*!< bit: 24 Thumb bit */ 272 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 273 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 274 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 275 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 276 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 277 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 278 } b; /*!< Structure used for bit access */ 279 uint32_t w; /*!< Type used for word access */ 280 } xPSR_Type; 281 282 /* xPSR Register Definitions */ 283 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 284 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 285 286 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 287 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 288 289 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 290 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 291 292 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 293 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 294 295 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 296 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 297 298 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 299 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 300 301 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 302 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 303 304 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 305 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 306 307 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 308 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 309 310 311 /** 312 \brief Union type to access the Control Registers (CONTROL). 313 */ 314 typedef union 315 { 316 struct 317 { 318 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 321 } b; /*!< Structure used for bit access */ 322 uint32_t w; /*!< Type used for word access */ 323 } CONTROL_Type; 324 325 /* CONTROL Register Definitions */ 326 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 328 329 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 330 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 331 332 /*@} end of group CMSIS_CORE */ 333 334 335 /** 336 \ingroup CMSIS_core_register 337 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 338 \brief Type definitions for the NVIC Registers 339 @{ 340 */ 341 342 /** 343 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 344 */ 345 typedef struct 346 { 347 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 348 uint32_t RESERVED0[24U]; 349 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 350 uint32_t RESERVED1[24U]; 351 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 352 uint32_t RESERVED2[24U]; 353 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 354 uint32_t RESERVED3[24U]; 355 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 356 uint32_t RESERVED4[56U]; 357 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 358 uint32_t RESERVED5[644U]; 359 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 360 } NVIC_Type; 361 362 /* Software Triggered Interrupt Register Definitions */ 363 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 364 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 365 366 /*@} end of group CMSIS_NVIC */ 367 368 369 /** 370 \ingroup CMSIS_core_register 371 \defgroup CMSIS_SCB System Control Block (SCB) 372 \brief Type definitions for the System Control Block Registers 373 @{ 374 */ 375 376 /** 377 \brief Structure type to access the System Control Block (SCB). 378 */ 379 typedef struct 380 { 381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 383 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 384 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 385 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 386 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 387 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 388 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 389 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 390 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 391 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 392 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 393 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 394 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 395 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 397 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 398 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 399 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 400 uint32_t RESERVED0[5U]; 401 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 402 } SCB_Type; 403 404 /* SCB CPUID Register Definitions */ 405 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 406 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 407 408 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 409 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 410 411 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 412 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 413 414 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 415 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 416 417 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 418 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 419 420 /* SCB Interrupt Control State Register Definitions */ 421 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 422 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 423 424 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 426 427 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 429 430 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 432 433 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 435 436 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 437 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 438 439 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 440 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 441 442 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 443 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 444 445 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 446 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 447 448 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 449 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 450 451 /* SCB Vector Table Offset Register Definitions */ 452 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ 453 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ 454 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ 455 456 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 457 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 458 #else 459 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 460 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 461 #endif 462 463 /* SCB Application Interrupt and Reset Control Register Definitions */ 464 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 465 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 466 467 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 468 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 469 470 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 471 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 472 473 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 474 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 475 476 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 477 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 478 479 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 480 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 481 482 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 483 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 484 485 /* SCB System Control Register Definitions */ 486 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 488 489 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 490 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 491 492 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 493 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 494 495 /* SCB Configuration Control Register Definitions */ 496 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 497 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 498 499 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 500 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 501 502 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 503 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 504 505 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 506 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 507 508 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 509 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 510 511 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 512 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 513 514 /* SCB System Handler Control and State Register Definitions */ 515 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 516 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 517 518 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 519 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 520 521 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 522 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 523 524 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 525 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 526 527 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 528 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 529 530 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 531 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 532 533 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 534 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 535 536 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 537 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 538 539 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 540 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 541 542 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 543 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 544 545 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 546 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 547 548 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 549 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 550 551 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 552 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 553 554 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 555 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 556 557 /* SCB Configurable Fault Status Register Definitions */ 558 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 559 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 560 561 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 562 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 563 564 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 565 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 566 567 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 568 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 569 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 570 571 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 572 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 573 574 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 575 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 576 577 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 578 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 579 580 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 581 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 582 583 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 584 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 585 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 586 587 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 588 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 589 590 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 591 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 592 593 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 594 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 595 596 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 597 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 598 599 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 600 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 601 602 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 603 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 604 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 605 606 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 607 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 608 609 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 610 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 611 612 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 613 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 614 615 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 616 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 617 618 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 619 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 620 621 /* SCB Hard Fault Status Register Definitions */ 622 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 623 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 624 625 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 626 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 627 628 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 629 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 630 631 /* SCB Debug Fault Status Register Definitions */ 632 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 633 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 634 635 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 636 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 637 638 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 639 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 640 641 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 642 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 643 644 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 645 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 646 647 /*@} end of group CMSIS_SCB */ 648 649 650 /** 651 \ingroup CMSIS_core_register 652 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 653 \brief Type definitions for the System Control and ID Register not in the SCB 654 @{ 655 */ 656 657 /** 658 \brief Structure type to access the System Control and ID Register not in the SCB. 659 */ 660 typedef struct 661 { 662 uint32_t RESERVED0[1U]; 663 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 664 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) 665 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 666 #else 667 uint32_t RESERVED1[1U]; 668 #endif 669 } SCnSCB_Type; 670 671 /* Interrupt Controller Type Register Definitions */ 672 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 673 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 674 675 /* Auxiliary Control Register Definitions */ 676 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) 677 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ 678 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ 679 680 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ 681 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ 682 683 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 684 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 685 686 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ 687 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 688 689 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 690 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 691 #endif 692 693 /*@} end of group CMSIS_SCnotSCB */ 694 695 696 /** 697 \ingroup CMSIS_core_register 698 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 699 \brief Type definitions for the System Timer Registers. 700 @{ 701 */ 702 703 /** 704 \brief Structure type to access the System Timer (SysTick). 705 */ 706 typedef struct 707 { 708 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 709 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 710 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 711 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 712 } SysTick_Type; 713 714 /* SysTick Control / Status Register Definitions */ 715 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 716 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 717 718 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 719 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 720 721 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 722 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 723 724 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 725 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 726 727 /* SysTick Reload Register Definitions */ 728 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 729 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 730 731 /* SysTick Current Register Definitions */ 732 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 733 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 734 735 /* SysTick Calibration Register Definitions */ 736 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 737 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 738 739 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 740 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 741 742 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 743 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 744 745 /*@} end of group CMSIS_SysTick */ 746 747 748 /** 749 \ingroup CMSIS_core_register 750 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 751 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 752 @{ 753 */ 754 755 /** 756 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 757 */ 758 typedef struct 759 { 760 __OM union 761 { 762 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 763 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 764 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 765 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 766 uint32_t RESERVED0[864U]; 767 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 768 uint32_t RESERVED1[15U]; 769 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 770 uint32_t RESERVED2[15U]; 771 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 772 uint32_t RESERVED3[32U]; 773 uint32_t RESERVED4[43U]; 774 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 775 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 776 uint32_t RESERVED5[6U]; 777 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 778 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 779 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 780 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 781 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 782 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 783 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 784 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 785 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 786 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 787 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 788 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 789 } ITM_Type; 790 791 /* ITM Trace Privilege Register Definitions */ 792 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 793 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 794 795 /* ITM Trace Control Register Definitions */ 796 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 797 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 798 799 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 800 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 801 802 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 803 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 804 805 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 806 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 807 808 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 809 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 810 811 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 812 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 813 814 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 815 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 816 817 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 818 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 819 820 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 821 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 822 823 /* ITM Lock Status Register Definitions */ 824 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 825 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 826 827 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 828 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 829 830 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 831 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 832 833 /*@}*/ /* end of group CMSIS_ITM */ 834 835 836 /** 837 \ingroup CMSIS_core_register 838 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 839 \brief Type definitions for the Data Watchpoint and Trace (DWT) 840 @{ 841 */ 842 843 /** 844 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 845 */ 846 typedef struct 847 { 848 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 849 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 850 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 851 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 852 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 853 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 854 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 855 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 856 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 857 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 858 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 859 uint32_t RESERVED0[1U]; 860 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 861 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 862 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 863 uint32_t RESERVED1[1U]; 864 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 865 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 866 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 867 uint32_t RESERVED2[1U]; 868 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 869 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 870 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 871 } DWT_Type; 872 873 /* DWT Control Register Definitions */ 874 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 875 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 876 877 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 878 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 879 880 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 881 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 882 883 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 884 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 885 886 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 887 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 888 889 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 890 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 891 892 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 893 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 894 895 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 896 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 897 898 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 899 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 900 901 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 902 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 903 904 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 905 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 906 907 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 908 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 909 910 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 911 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 912 913 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 914 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 915 916 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 917 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 918 919 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 920 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 921 922 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 923 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 924 925 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 926 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 927 928 /* DWT CPI Count Register Definitions */ 929 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 930 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 931 932 /* DWT Exception Overhead Count Register Definitions */ 933 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 934 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 935 936 /* DWT Sleep Count Register Definitions */ 937 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 938 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 939 940 /* DWT LSU Count Register Definitions */ 941 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 942 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 943 944 /* DWT Folded-instruction Count Register Definitions */ 945 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 946 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 947 948 /* DWT Comparator Mask Register Definitions */ 949 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 950 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 951 952 /* DWT Comparator Function Register Definitions */ 953 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 954 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 955 956 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 957 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 958 959 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 960 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 961 962 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 963 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 964 965 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 966 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 967 968 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 969 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 970 971 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 972 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 973 974 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 975 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 976 977 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 978 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 979 980 /*@}*/ /* end of group CMSIS_DWT */ 981 982 983 /** 984 \ingroup CMSIS_core_register 985 \defgroup CMSIS_TPI Trace Port Interface (TPI) 986 \brief Type definitions for the Trace Port Interface (TPI) 987 @{ 988 */ 989 990 /** 991 \brief Structure type to access the Trace Port Interface Register (TPI). 992 */ 993 typedef struct 994 { 995 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 996 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 997 uint32_t RESERVED0[2U]; 998 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 999 uint32_t RESERVED1[55U]; 1000 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 1001 uint32_t RESERVED2[131U]; 1002 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 1003 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 1004 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 1005 uint32_t RESERVED3[759U]; 1006 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1007 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1008 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1009 uint32_t RESERVED4[1U]; 1010 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1011 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1012 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1013 uint32_t RESERVED5[39U]; 1014 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1015 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1016 uint32_t RESERVED7[8U]; 1017 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1018 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1019 } TPI_Type; 1020 1021 /* TPI Asynchronous Clock Prescaler Register Definitions */ 1022 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 1023 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 1024 1025 /* TPI Selected Pin Protocol Register Definitions */ 1026 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 1027 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 1028 1029 /* TPI Formatter and Flush Status Register Definitions */ 1030 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 1031 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 1032 1033 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 1034 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 1035 1036 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 1037 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 1038 1039 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 1040 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 1041 1042 /* TPI Formatter and Flush Control Register Definitions */ 1043 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 1044 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 1045 1046 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 1047 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 1048 1049 /* TPI TRIGGER Register Definitions */ 1050 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 1051 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 1052 1053 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1054 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 1055 #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 1056 1057 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 1058 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 1059 1060 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 1061 #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 1062 1063 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 1064 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 1065 1066 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 1067 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 1068 1069 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 1070 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 1071 1072 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 1073 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 1074 1075 /* TPI ITATBCTR2 Register Definitions */ 1076 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ 1077 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ 1078 1079 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ 1080 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ 1081 1082 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1083 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 1084 #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 1085 1086 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 1087 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 1088 1089 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 1090 #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 1091 1092 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 1093 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 1094 1095 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 1096 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 1097 1098 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 1099 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 1100 1101 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 1102 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 1103 1104 /* TPI ITATBCTR0 Register Definitions */ 1105 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ 1106 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ 1107 1108 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ 1109 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ 1110 1111 /* TPI Integration Mode Control Register Definitions */ 1112 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 1113 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 1114 1115 /* TPI DEVID Register Definitions */ 1116 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 1117 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1118 1119 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 1120 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1121 1122 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 1123 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1124 1125 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 1126 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 1127 1128 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 1129 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 1130 1131 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 1132 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 1133 1134 /* TPI DEVTYPE Register Definitions */ 1135 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 1136 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 1137 1138 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 1139 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1140 1141 /*@}*/ /* end of group CMSIS_TPI */ 1142 1143 1144 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1145 /** 1146 \ingroup CMSIS_core_register 1147 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1148 \brief Type definitions for the Memory Protection Unit (MPU) 1149 @{ 1150 */ 1151 1152 /** 1153 \brief Structure type to access the Memory Protection Unit (MPU). 1154 */ 1155 typedef struct 1156 { 1157 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1158 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1159 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1160 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 1161 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 1162 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 1163 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 1164 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 1165 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 1166 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 1167 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 1168 } MPU_Type; 1169 1170 #define MPU_TYPE_RALIASES 4U 1171 1172 /* MPU Type Register Definitions */ 1173 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 1174 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 1175 1176 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 1177 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 1178 1179 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 1180 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 1181 1182 /* MPU Control Register Definitions */ 1183 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 1184 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 1185 1186 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 1187 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 1188 1189 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 1190 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 1191 1192 /* MPU Region Number Register Definitions */ 1193 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 1194 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 1195 1196 /* MPU Region Base Address Register Definitions */ 1197 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1198 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1199 1200 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1201 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1202 1203 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1204 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 1205 1206 /* MPU Region Attribute and Size Register Definitions */ 1207 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1208 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1209 1210 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1211 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1212 1213 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1214 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1215 1216 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1217 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1218 1219 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 1220 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 1221 1222 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 1223 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 1224 1225 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 1226 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 1227 1228 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 1229 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 1230 1231 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 1232 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 1233 1234 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 1235 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 1236 1237 /*@} end of group CMSIS_MPU */ 1238 #endif 1239 1240 1241 /** 1242 \ingroup CMSIS_core_register 1243 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1244 \brief Type definitions for the Core Debug Registers 1245 @{ 1246 */ 1247 1248 /** 1249 \brief Structure type to access the Core Debug Register (CoreDebug). 1250 */ 1251 typedef struct 1252 { 1253 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1254 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1255 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1256 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1257 } CoreDebug_Type; 1258 1259 /* Debug Halting Control and Status Register Definitions */ 1260 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 1261 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1262 1263 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1264 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1265 1266 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1267 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1268 1269 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1270 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1271 1272 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 1273 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1274 1275 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 1276 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1277 1278 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 1279 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1280 1281 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 1282 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 1283 1284 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1285 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1286 1287 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 1288 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1289 1290 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 1291 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1292 1293 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1294 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1295 1296 /* Debug Core Register Selector Register Definitions */ 1297 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 1298 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1299 1300 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 1301 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 1302 1303 /* Debug Exception and Monitor Control Register Definitions */ 1304 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 1305 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 1306 1307 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 1308 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 1309 1310 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 1311 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 1312 1313 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 1314 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 1315 1316 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 1317 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 1318 1319 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1320 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1321 1322 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 1323 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 1324 1325 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 1326 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 1327 1328 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 1329 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 1330 1331 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 1332 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 1333 1334 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 1335 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 1336 1337 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 1338 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 1339 1340 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1341 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1342 1343 /*@} end of group CMSIS_CoreDebug */ 1344 1345 1346 /** 1347 \ingroup CMSIS_core_register 1348 \defgroup CMSIS_core_bitfield Core register bit field macros 1349 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1350 @{ 1351 */ 1352 1353 /** 1354 \brief Mask and shift a bit field value for use in a register bit range. 1355 \param[in] field Name of the register bit field. 1356 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1357 \return Masked and shifted value. 1358 */ 1359 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1360 1361 /** 1362 \brief Mask and shift a register value to extract a bit filed value. 1363 \param[in] field Name of the register bit field. 1364 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1365 \return Masked and shifted bit field value. 1366 */ 1367 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1368 1369 /*@} end of group CMSIS_core_bitfield */ 1370 1371 1372 /** 1373 \ingroup CMSIS_core_register 1374 \defgroup CMSIS_core_base Core Definitions 1375 \brief Definitions for base addresses, unions, and structures. 1376 @{ 1377 */ 1378 1379 /* Memory mapping of Core Hardware */ 1380 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1381 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1382 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1383 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1384 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1385 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1386 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1387 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1388 1389 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 1390 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1391 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1392 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1393 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 1394 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1395 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1396 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 1397 1398 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1399 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1400 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1401 #endif 1402 1403 /*@} */ 1404 1405 1406 1407 /******************************************************************************* 1408 * Hardware Abstraction Layer 1409 Core Function Interface contains: 1410 - Core NVIC Functions 1411 - Core SysTick Functions 1412 - Core Debug Functions 1413 - Core Register Access Functions 1414 ******************************************************************************/ 1415 /** 1416 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1417 */ 1418 1419 1420 1421 /* ########################## NVIC functions #################################### */ 1422 /** 1423 \ingroup CMSIS_Core_FunctionInterface 1424 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1425 \brief Functions that manage interrupts and exceptions via the NVIC. 1426 @{ 1427 */ 1428 1429 #ifdef CMSIS_NVIC_VIRTUAL 1430 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1431 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1432 #endif 1433 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1434 #else 1435 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1436 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1437 #define NVIC_EnableIRQ __NVIC_EnableIRQ 1438 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1439 #define NVIC_DisableIRQ __NVIC_DisableIRQ 1440 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1441 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1442 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1443 #define NVIC_GetActive __NVIC_GetActive 1444 #define NVIC_SetPriority __NVIC_SetPriority 1445 #define NVIC_GetPriority __NVIC_GetPriority 1446 #define NVIC_SystemReset __NVIC_SystemReset 1447 #endif /* CMSIS_NVIC_VIRTUAL */ 1448 1449 #ifdef CMSIS_VECTAB_VIRTUAL 1450 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1451 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1452 #endif 1453 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1454 #else 1455 #define NVIC_SetVector __NVIC_SetVector 1456 #define NVIC_GetVector __NVIC_GetVector 1457 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1458 1459 #define NVIC_USER_IRQ_OFFSET 16 1460 1461 1462 /* The following EXC_RETURN values are saved the LR on exception entry */ 1463 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 1464 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 1465 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 1466 1467 1468 /** 1469 \brief Set Priority Grouping 1470 \details Sets the priority grouping field using the required unlock sequence. 1471 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1472 Only values from 0..7 are used. 1473 In case of a conflict between priority grouping and available 1474 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1475 \param [in] PriorityGroup Priority grouping field. 1476 */ 1477 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1478 { 1479 uint32_t reg_value; 1480 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1481 1482 reg_value = SCB->AIRCR; /* read old register configuration */ 1483 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 1484 reg_value = (reg_value | 1485 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1486 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 1487 SCB->AIRCR = reg_value; 1488 } 1489 1490 1491 /** 1492 \brief Get Priority Grouping 1493 \details Reads the priority grouping field from the NVIC Interrupt Controller. 1494 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1495 */ 1496 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1497 { 1498 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 1499 } 1500 1501 1502 /** 1503 \brief Enable Interrupt 1504 \details Enables a device specific interrupt in the NVIC interrupt controller. 1505 \param [in] IRQn Device specific interrupt number. 1506 \note IRQn must not be negative. 1507 */ 1508 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1509 { 1510 if ((int32_t)(IRQn) >= 0) 1511 { 1512 __COMPILER_BARRIER(); 1513 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1514 __COMPILER_BARRIER(); 1515 } 1516 } 1517 1518 1519 /** 1520 \brief Get Interrupt Enable status 1521 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1522 \param [in] IRQn Device specific interrupt number. 1523 \return 0 Interrupt is not enabled. 1524 \return 1 Interrupt is enabled. 1525 \note IRQn must not be negative. 1526 */ 1527 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1528 { 1529 if ((int32_t)(IRQn) >= 0) 1530 { 1531 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1532 } 1533 else 1534 { 1535 return(0U); 1536 } 1537 } 1538 1539 1540 /** 1541 \brief Disable Interrupt 1542 \details Disables a device specific interrupt in the NVIC interrupt controller. 1543 \param [in] IRQn Device specific interrupt number. 1544 \note IRQn must not be negative. 1545 */ 1546 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1547 { 1548 if ((int32_t)(IRQn) >= 0) 1549 { 1550 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1551 __DSB(); 1552 __ISB(); 1553 } 1554 } 1555 1556 1557 /** 1558 \brief Get Pending Interrupt 1559 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 1560 \param [in] IRQn Device specific interrupt number. 1561 \return 0 Interrupt status is not pending. 1562 \return 1 Interrupt status is pending. 1563 \note IRQn must not be negative. 1564 */ 1565 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1566 { 1567 if ((int32_t)(IRQn) >= 0) 1568 { 1569 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1570 } 1571 else 1572 { 1573 return(0U); 1574 } 1575 } 1576 1577 1578 /** 1579 \brief Set Pending Interrupt 1580 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1581 \param [in] IRQn Device specific interrupt number. 1582 \note IRQn must not be negative. 1583 */ 1584 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1585 { 1586 if ((int32_t)(IRQn) >= 0) 1587 { 1588 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1589 } 1590 } 1591 1592 1593 /** 1594 \brief Clear Pending Interrupt 1595 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1596 \param [in] IRQn Device specific interrupt number. 1597 \note IRQn must not be negative. 1598 */ 1599 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1600 { 1601 if ((int32_t)(IRQn) >= 0) 1602 { 1603 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1604 } 1605 } 1606 1607 1608 /** 1609 \brief Get Active Interrupt 1610 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 1611 \param [in] IRQn Device specific interrupt number. 1612 \return 0 Interrupt status is not active. 1613 \return 1 Interrupt status is active. 1614 \note IRQn must not be negative. 1615 */ 1616 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1617 { 1618 if ((int32_t)(IRQn) >= 0) 1619 { 1620 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1621 } 1622 else 1623 { 1624 return(0U); 1625 } 1626 } 1627 1628 1629 /** 1630 \brief Set Interrupt Priority 1631 \details Sets the priority of a device specific interrupt or a processor exception. 1632 The interrupt number can be positive to specify a device specific interrupt, 1633 or negative to specify a processor exception. 1634 \param [in] IRQn Interrupt number. 1635 \param [in] priority Priority to set. 1636 \note The priority cannot be set for every processor exception. 1637 */ 1638 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1639 { 1640 if ((int32_t)(IRQn) >= 0) 1641 { 1642 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 1643 } 1644 else 1645 { 1646 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 1647 } 1648 } 1649 1650 1651 /** 1652 \brief Get Interrupt Priority 1653 \details Reads the priority of a device specific interrupt or a processor exception. 1654 The interrupt number can be positive to specify a device specific interrupt, 1655 or negative to specify a processor exception. 1656 \param [in] IRQn Interrupt number. 1657 \return Interrupt Priority. 1658 Value is aligned automatically to the implemented priority bits of the microcontroller. 1659 */ 1660 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1661 { 1662 1663 if ((int32_t)(IRQn) >= 0) 1664 { 1665 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 1666 } 1667 else 1668 { 1669 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 1670 } 1671 } 1672 1673 1674 /** 1675 \brief Encode Priority 1676 \details Encodes the priority for an interrupt with the given priority group, 1677 preemptive priority value, and subpriority value. 1678 In case of a conflict between priority grouping and available 1679 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1680 \param [in] PriorityGroup Used priority group. 1681 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1682 \param [in] SubPriority Subpriority value (starting from 0). 1683 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1684 */ 1685 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 1686 { 1687 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1688 uint32_t PreemptPriorityBits; 1689 uint32_t SubPriorityBits; 1690 1691 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 1692 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1693 1694 return ( 1695 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 1696 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 1697 ); 1698 } 1699 1700 1701 /** 1702 \brief Decode Priority 1703 \details Decodes an interrupt priority value with a given priority group to 1704 preemptive priority value and subpriority value. 1705 In case of a conflict between priority grouping and available 1706 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1707 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1708 \param [in] PriorityGroup Used priority group. 1709 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1710 \param [out] pSubPriority Subpriority value (starting from 0). 1711 */ 1712 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 1713 { 1714 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1715 uint32_t PreemptPriorityBits; 1716 uint32_t SubPriorityBits; 1717 1718 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 1719 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1720 1721 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 1722 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 1723 } 1724 1725 1726 /** 1727 \brief Set Interrupt Vector 1728 \details Sets an interrupt vector in SRAM based interrupt vector table. 1729 The interrupt number can be positive to specify a device specific interrupt, 1730 or negative to specify a processor exception. 1731 VTOR must been relocated to SRAM before. 1732 \param [in] IRQn Interrupt number 1733 \param [in] vector Address of interrupt handler function 1734 */ 1735 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 1736 { 1737 uint32_t *vectors = (uint32_t *)SCB->VTOR; 1738 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 1739 /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ 1740 } 1741 1742 1743 /** 1744 \brief Get Interrupt Vector 1745 \details Reads an interrupt vector from interrupt vector table. 1746 The interrupt number can be positive to specify a device specific interrupt, 1747 or negative to specify a processor exception. 1748 \param [in] IRQn Interrupt number. 1749 \return Address of interrupt handler function 1750 */ 1751 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 1752 { 1753 uint32_t *vectors = (uint32_t *)SCB->VTOR; 1754 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 1755 } 1756 1757 1758 /** 1759 \brief System Reset 1760 \details Initiates a system reset request to reset the MCU. 1761 */ 1762 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 1763 { 1764 __DSB(); /* Ensure all outstanding memory accesses included 1765 buffered write are completed before reset */ 1766 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1767 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 1768 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 1769 __DSB(); /* Ensure completion of memory access */ 1770 1771 for(;;) /* wait until reset */ 1772 { 1773 __NOP(); 1774 } 1775 } 1776 1777 /*@} end of CMSIS_Core_NVICFunctions */ 1778 1779 1780 /* ########################## MPU functions #################################### */ 1781 1782 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1783 1784 #include "mpu_armv7.h" 1785 1786 #endif 1787 1788 1789 /* ########################## FPU functions #################################### */ 1790 /** 1791 \ingroup CMSIS_Core_FunctionInterface 1792 \defgroup CMSIS_Core_FpuFunctions FPU Functions 1793 \brief Function that provides FPU type. 1794 @{ 1795 */ 1796 1797 /** 1798 \brief get FPU type 1799 \details returns the FPU type 1800 \returns 1801 - \b 0: No FPU 1802 - \b 1: Single precision FPU 1803 - \b 2: Double + Single precision FPU 1804 */ 1805 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 1806 { 1807 return 0U; /* No FPU */ 1808 } 1809 1810 1811 /*@} end of CMSIS_Core_FpuFunctions */ 1812 1813 1814 1815 /* ################################## SysTick function ############################################ */ 1816 /** 1817 \ingroup CMSIS_Core_FunctionInterface 1818 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 1819 \brief Functions that configure the System. 1820 @{ 1821 */ 1822 1823 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 1824 1825 /** 1826 \brief System Tick Configuration 1827 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 1828 Counter is in free running mode to generate periodic interrupts. 1829 \param [in] ticks Number of ticks between two interrupts. 1830 \return 0 Function succeeded. 1831 \return 1 Function failed. 1832 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1833 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 1834 must contain a vendor-specific implementation of this function. 1835 */ 1836 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 1837 { 1838 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1839 { 1840 return (1UL); /* Reload value impossible */ 1841 } 1842 1843 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1844 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1845 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 1846 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1847 SysTick_CTRL_TICKINT_Msk | 1848 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1849 return (0UL); /* Function successful */ 1850 } 1851 1852 #endif 1853 1854 /*@} end of CMSIS_Core_SysTickFunctions */ 1855 1856 1857 1858 /* ##################################### Debug In/Output function ########################################### */ 1859 /** 1860 \ingroup CMSIS_Core_FunctionInterface 1861 \defgroup CMSIS_core_DebugFunctions ITM Functions 1862 \brief Functions that access the ITM debug interface. 1863 @{ 1864 */ 1865 1866 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 1867 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 1868 1869 1870 /** 1871 \brief ITM Send Character 1872 \details Transmits a character via the ITM channel 0, and 1873 \li Just returns when no debugger is connected that has booked the output. 1874 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 1875 \param [in] ch Character to transmit. 1876 \returns Character to transmit. 1877 */ 1878 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 1879 { 1880 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 1881 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 1882 { 1883 while (ITM->PORT[0U].u32 == 0UL) 1884 { 1885 __NOP(); 1886 } 1887 ITM->PORT[0U].u8 = (uint8_t)ch; 1888 } 1889 return (ch); 1890 } 1891 1892 1893 /** 1894 \brief ITM Receive Character 1895 \details Inputs a character via the external variable \ref ITM_RxBuffer. 1896 \return Received character. 1897 \return -1 No character pending. 1898 */ 1899 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 1900 { 1901 int32_t ch = -1; /* no character available */ 1902 1903 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 1904 { 1905 ch = ITM_RxBuffer; 1906 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 1907 } 1908 1909 return (ch); 1910 } 1911 1912 1913 /** 1914 \brief ITM Check Character 1915 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 1916 \return 0 No character available. 1917 \return 1 Character available. 1918 */ 1919 __STATIC_INLINE int32_t ITM_CheckChar (void) 1920 { 1921 1922 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 1923 { 1924 return (0); /* no character available */ 1925 } 1926 else 1927 { 1928 return (1); /* character available */ 1929 } 1930 } 1931 1932 /*@} end of CMSIS_core_DebugFunctions */ 1933 1934 1935 1936 1937 #ifdef __cplusplus 1938 } 1939 #endif 1940 1941 #endif /* __CORE_CM3_H_DEPENDANT */ 1942 1943 #endif /* __CMSIS_GENERIC */