pmu_armv8.h
1 /****************************************************************************** 2 * @file pmu_armv8.h 3 * @brief CMSIS PMU API for Armv8.1-M PMU 4 * @version V1.0.1 5 * @date 15. April 2020 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2020 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef ARM_PMU_ARMV8_H 32 #define ARM_PMU_ARMV8_H 33 34 /** 35 * \brief PMU Events 36 * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. 37 * */ 38 39 #define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ 40 #define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ 41 #define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ 42 #define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ 43 #define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ 44 #define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ 45 #define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ 46 #define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ 47 #define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ 48 #define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ 49 #define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ 50 #define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ 51 #define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ 52 #define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ 53 #define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ 54 #define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ 55 #define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ 56 #define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ 57 #define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ 58 #define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ 59 #define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ 60 #define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ 61 #define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ 62 #define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ 63 #define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ 64 #define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ 65 #define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ 66 #define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ 67 #define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ 68 #define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ 69 #define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ 70 #define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ 71 #define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ 72 #define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ 73 #define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ 74 #define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ 75 #define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ 76 #define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ 77 #define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ 78 #define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ 79 #define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ 80 #define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ 81 #define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ 82 #define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ 83 #define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ 84 #define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ 85 #define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ 86 #define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ 87 #define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ 88 #define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ 89 #define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ 90 #define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ 91 #define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ 92 #define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ 93 #define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ 94 #define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ 95 #define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ 96 #define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ 97 #define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ 98 #define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ 99 #define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ 100 #define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ 101 #define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ 102 #define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ 103 #define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ 104 #define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ 105 #define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ 106 #define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ 107 #define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ 108 #define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ 109 #define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ 110 #define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ 111 #define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ 112 #define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ 113 #define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ 114 #define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ 115 #define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ 116 #define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ 117 #define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ 118 #define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ 119 #define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ 120 #define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ 121 #define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ 122 #define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ 123 #define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ 124 #define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ 125 #define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ 126 #define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ 127 #define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ 128 #define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ 129 #define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ 130 #define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ 131 #define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ 132 #define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ 133 #define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ 134 #define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ 135 #define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ 136 #define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ 137 #define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ 138 #define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ 139 #define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ 140 #define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ 141 #define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ 142 #define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ 143 #define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ 144 #define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ 145 #define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ 146 #define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ 147 #define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ 148 #define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ 149 #define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ 150 #define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ 151 #define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ 152 #define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ 153 #define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ 154 #define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ 155 #define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ 156 #define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ 157 #define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ 158 #define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ 159 #define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ 160 #define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ 161 #define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ 162 #define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ 163 #define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ 164 #define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ 165 #define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ 166 #define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ 167 #define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ 168 #define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ 169 #define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ 170 171 /** \brief PMU Functions */ 172 173 __STATIC_INLINE void ARM_PMU_Enable(void); 174 __STATIC_INLINE void ARM_PMU_Disable(void); 175 176 __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); 177 178 __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); 179 __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); 180 181 __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); 182 __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); 183 184 __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); 185 __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); 186 187 __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); 188 __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); 189 190 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); 191 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); 192 193 __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); 194 195 /** 196 \brief Enable the PMU 197 */ 198 __STATIC_INLINE void ARM_PMU_Enable(void) 199 { 200 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; 201 } 202 203 /** 204 \brief Disable the PMU 205 */ 206 __STATIC_INLINE void ARM_PMU_Disable(void) 207 { 208 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; 209 } 210 211 /** 212 \brief Set event to count for PMU eventer counter 213 \param [in] num Event counter (0-30) to configure 214 \param [in] type Event to count 215 */ 216 __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) 217 { 218 PMU->EVTYPER[num] = type; 219 } 220 221 /** 222 \brief Reset cycle counter 223 */ 224 __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) 225 { 226 PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; 227 } 228 229 /** 230 \brief Reset all event counters 231 */ 232 __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) 233 { 234 PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; 235 } 236 237 /** 238 \brief Enable counters 239 \param [in] mask Counters to enable 240 \note Enables one or more of the following: 241 - event counters (0-30) 242 - cycle counter 243 */ 244 __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) 245 { 246 PMU->CNTENSET = mask; 247 } 248 249 /** 250 \brief Disable counters 251 \param [in] mask Counters to enable 252 \note Disables one or more of the following: 253 - event counters (0-30) 254 - cycle counter 255 */ 256 __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) 257 { 258 PMU->CNTENCLR = mask; 259 } 260 261 /** 262 \brief Read cycle counter 263 \return Cycle count 264 */ 265 __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) 266 { 267 return PMU->CCNTR; 268 } 269 270 /** 271 \brief Read event counter 272 \param [in] num Event counter (0-30) to read 273 \return Event count 274 */ 275 __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) 276 { 277 return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; 278 } 279 280 /** 281 \brief Read counter overflow status 282 \return Counter overflow status bits for the following: 283 - event counters (0-30) 284 - cycle counter 285 */ 286 __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) 287 { 288 return PMU->OVSSET; 289 } 290 291 /** 292 \brief Clear counter overflow status 293 \param [in] mask Counter overflow status bits to clear 294 \note Clears overflow status bits for one or more of the following: 295 - event counters (0-30) 296 - cycle counter 297 */ 298 __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) 299 { 300 PMU->OVSCLR = mask; 301 } 302 303 /** 304 \brief Enable counter overflow interrupt request 305 \param [in] mask Counter overflow interrupt request bits to set 306 \note Sets overflow interrupt request bits for one or more of the following: 307 - event counters (0-30) 308 - cycle counter 309 */ 310 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) 311 { 312 PMU->INTENSET = mask; 313 } 314 315 /** 316 \brief Disable counter overflow interrupt request 317 \param [in] mask Counter overflow interrupt request bits to clear 318 \note Clears overflow interrupt request bits for one or more of the following: 319 - event counters (0-30) 320 - cycle counter 321 */ 322 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) 323 { 324 PMU->INTENCLR = mask; 325 } 326 327 /** 328 \brief Software increment event counter 329 \param [in] mask Counters to increment 330 \note Software increment bits for one or more event counters (0-30) 331 */ 332 __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) 333 { 334 PMU->SWINC = mask; 335 } 336 337 #endif