stm32f4xx_ll_cortex.h
1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_ll_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX LL module. 6 @verbatim 7 ============================================================================== 8 ##### How to use this driver ##### 9 ============================================================================== 10 [..] 11 The LL CORTEX driver contains a set of generic APIs that can be 12 used by user: 13 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick 14 functions 15 (+) Low power mode configuration (SCB register of Cortex-MCU) 16 (+) MPU API to configure and enable regions 17 (MPU services provided only on some devices) 18 (+) API to access to MCU info (CPUID register) 19 (+) API to enable fault handler (SHCSR accesses) 20 21 @endverbatim 22 ****************************************************************************** 23 * @attention 24 * 25 * Copyright (c) 2017 STMicroelectronics. 26 * All rights reserved. 27 * 28 * This software is licensed under terms that can be found in the LICENSE file in 29 * the root directory of this software component. 30 * If no LICENSE file comes with this software, it is provided AS-IS. 31 ****************************************************************************** 32 */ 33 34 /* Define to prevent recursive inclusion -------------------------------------*/ 35 #ifndef __STM32F4xx_LL_CORTEX_H 36 #define __STM32F4xx_LL_CORTEX_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* Includes ------------------------------------------------------------------*/ 43 #include "stm32f4xx.h" 44 45 /** @addtogroup STM32F4xx_LL_Driver 46 * @{ 47 */ 48 49 /** @defgroup CORTEX_LL CORTEX 50 * @{ 51 */ 52 53 /* Private types -------------------------------------------------------------*/ 54 /* Private variables ---------------------------------------------------------*/ 55 56 /* Private constants ---------------------------------------------------------*/ 57 58 /* Private macros ------------------------------------------------------------*/ 59 60 /* Exported types ------------------------------------------------------------*/ 61 /* Exported constants --------------------------------------------------------*/ 62 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants 63 * @{ 64 */ 65 66 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source 67 * @{ 68 */ 69 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ 70 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ 71 /** 72 * @} 73 */ 74 75 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type 76 * @{ 77 */ 78 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ 79 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ 80 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ 81 /** 82 * @} 83 */ 84 85 #if __MPU_PRESENT 86 87 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control 88 * @{ 89 */ 90 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ 91 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ 92 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ 93 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ 94 /** 95 * @} 96 */ 97 98 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number 99 * @{ 100 */ 101 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ 102 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ 103 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ 104 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ 105 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ 106 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ 107 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ 108 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ 109 /** 110 * @} 111 */ 112 113 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size 114 * @{ 115 */ 116 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ 117 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ 118 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ 119 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ 120 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ 121 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ 122 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ 123 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ 124 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ 125 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ 126 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ 127 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ 128 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ 129 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ 130 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ 131 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ 132 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ 133 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ 134 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ 135 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ 136 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ 137 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ 138 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ 139 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ 140 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ 141 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ 142 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ 143 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ 144 /** 145 * @} 146 */ 147 148 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges 149 * @{ 150 */ 151 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ 152 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ 153 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ 154 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ 155 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ 156 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ 157 /** 158 * @} 159 */ 160 161 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level 162 * @{ 163 */ 164 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ 165 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ 166 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ 167 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ 168 /** 169 * @} 170 */ 171 172 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access 173 * @{ 174 */ 175 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ 176 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ 177 /** 178 * @} 179 */ 180 181 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access 182 * @{ 183 */ 184 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ 185 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ 186 /** 187 * @} 188 */ 189 190 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access 191 * @{ 192 */ 193 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ 194 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ 195 /** 196 * @} 197 */ 198 199 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access 200 * @{ 201 */ 202 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ 203 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ 204 /** 205 * @} 206 */ 207 #endif /* __MPU_PRESENT */ 208 /** 209 * @} 210 */ 211 212 /* Exported macro ------------------------------------------------------------*/ 213 214 /* Exported functions --------------------------------------------------------*/ 215 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions 216 * @{ 217 */ 218 219 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK 220 * @{ 221 */ 222 223 /** 224 * @brief This function checks if the Systick counter flag is active or not. 225 * @note It can be used in timeout function on application side. 226 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag 227 * @retval State of bit (1 or 0). 228 */ 229 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) 230 { 231 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); 232 } 233 234 /** 235 * @brief Configures the SysTick clock source 236 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource 237 * @param Source This parameter can be one of the following values: 238 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 239 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 240 * @retval None 241 */ 242 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) 243 { 244 if (Source == LL_SYSTICK_CLKSOURCE_HCLK) 245 { 246 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 247 } 248 else 249 { 250 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 251 } 252 } 253 254 /** 255 * @brief Get the SysTick clock source 256 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource 257 * @retval Returned value can be one of the following values: 258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 259 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 260 */ 261 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) 262 { 263 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 264 } 265 266 /** 267 * @brief Enable SysTick exception request 268 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT 269 * @retval None 270 */ 271 __STATIC_INLINE void LL_SYSTICK_EnableIT(void) 272 { 273 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 274 } 275 276 /** 277 * @brief Disable SysTick exception request 278 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT 279 * @retval None 280 */ 281 __STATIC_INLINE void LL_SYSTICK_DisableIT(void) 282 { 283 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 284 } 285 286 /** 287 * @brief Checks if the SYSTICK interrupt is enabled or disabled. 288 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT 289 * @retval State of bit (1 or 0). 290 */ 291 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) 292 { 293 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); 294 } 295 296 /** 297 * @} 298 */ 299 300 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE 301 * @{ 302 */ 303 304 /** 305 * @brief Processor uses sleep as its low power mode 306 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep 307 * @retval None 308 */ 309 __STATIC_INLINE void LL_LPM_EnableSleep(void) 310 { 311 /* Clear SLEEPDEEP bit of Cortex System Control Register */ 312 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 313 } 314 315 /** 316 * @brief Processor uses deep sleep as its low power mode 317 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep 318 * @retval None 319 */ 320 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) 321 { 322 /* Set SLEEPDEEP bit of Cortex System Control Register */ 323 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 324 } 325 326 /** 327 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. 328 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an 329 * empty main application. 330 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit 331 * @retval None 332 */ 333 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) 334 { 335 /* Set SLEEPONEXIT bit of Cortex System Control Register */ 336 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 337 } 338 339 /** 340 * @brief Do not sleep when returning to Thread mode. 341 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit 342 * @retval None 343 */ 344 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) 345 { 346 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 347 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 348 } 349 350 /** 351 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the 352 * processor. 353 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend 354 * @retval None 355 */ 356 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) 357 { 358 /* Set SEVEONPEND bit of Cortex System Control Register */ 359 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 360 } 361 362 /** 363 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are 364 * excluded 365 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend 366 * @retval None 367 */ 368 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) 369 { 370 /* Clear SEVEONPEND bit of Cortex System Control Register */ 371 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 372 } 373 374 /** 375 * @brief Clear pending events. 376 * @retval None 377 */ 378 __STATIC_INLINE void LL_LPM_ClearEvent(void) 379 { 380 __SEV(); 381 __WFE(); 382 } 383 384 /** 385 * @} 386 */ 387 388 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER 389 * @{ 390 */ 391 392 /** 393 * @brief Enable a fault in System handler control register (SHCSR) 394 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault 395 * @param Fault This parameter can be a combination of the following values: 396 * @arg @ref LL_HANDLER_FAULT_USG 397 * @arg @ref LL_HANDLER_FAULT_BUS 398 * @arg @ref LL_HANDLER_FAULT_MEM 399 * @retval None 400 */ 401 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) 402 { 403 /* Enable the system handler fault */ 404 SET_BIT(SCB->SHCSR, Fault); 405 } 406 407 /** 408 * @brief Disable a fault in System handler control register (SHCSR) 409 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault 410 * @param Fault This parameter can be a combination of the following values: 411 * @arg @ref LL_HANDLER_FAULT_USG 412 * @arg @ref LL_HANDLER_FAULT_BUS 413 * @arg @ref LL_HANDLER_FAULT_MEM 414 * @retval None 415 */ 416 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) 417 { 418 /* Disable the system handler fault */ 419 CLEAR_BIT(SCB->SHCSR, Fault); 420 } 421 422 /** 423 * @} 424 */ 425 426 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO 427 * @{ 428 */ 429 430 /** 431 * @brief Get Implementer code 432 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer 433 * @retval Value should be equal to 0x41 for ARM 434 */ 435 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) 436 { 437 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); 438 } 439 440 /** 441 * @brief Get Variant number (The r value in the rnpn product revision identifier) 442 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant 443 * @retval Value between 0 and 255 (0x0: revision 0) 444 */ 445 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) 446 { 447 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); 448 } 449 450 /** 451 * @brief Get Constant number 452 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant 453 * @retval Value should be equal to 0xF for Cortex-M4 devices 454 */ 455 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) 456 { 457 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); 458 } 459 460 /** 461 * @brief Get Part number 462 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo 463 * @retval Value should be equal to 0xC24 for Cortex-M4 464 */ 465 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) 466 { 467 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); 468 } 469 470 /** 471 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) 472 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision 473 * @retval Value between 0 and 255 (0x1: patch 1) 474 */ 475 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) 476 { 477 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); 478 } 479 480 /** 481 * @} 482 */ 483 484 #if __MPU_PRESENT 485 /** @defgroup CORTEX_LL_EF_MPU MPU 486 * @{ 487 */ 488 489 /** 490 * @brief Enable MPU with input options 491 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable 492 * @param Options This parameter can be one of the following values: 493 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 494 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI 495 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT 496 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF 497 * @retval None 498 */ 499 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) 500 { 501 /* Enable the MPU*/ 502 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); 503 /* Ensure MPU settings take effects */ 504 __DSB(); 505 /* Sequence instruction fetches using update settings */ 506 __ISB(); 507 } 508 509 /** 510 * @brief Disable MPU 511 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable 512 * @retval None 513 */ 514 __STATIC_INLINE void LL_MPU_Disable(void) 515 { 516 /* Make sure outstanding transfers are done */ 517 __DMB(); 518 /* Disable MPU*/ 519 WRITE_REG(MPU->CTRL, 0U); 520 } 521 522 /** 523 * @brief Check if MPU is enabled or not 524 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled 525 * @retval State of bit (1 or 0). 526 */ 527 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) 528 { 529 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); 530 } 531 532 /** 533 * @brief Enable a MPU region 534 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion 535 * @param Region This parameter can be one of the following values: 536 * @arg @ref LL_MPU_REGION_NUMBER0 537 * @arg @ref LL_MPU_REGION_NUMBER1 538 * @arg @ref LL_MPU_REGION_NUMBER2 539 * @arg @ref LL_MPU_REGION_NUMBER3 540 * @arg @ref LL_MPU_REGION_NUMBER4 541 * @arg @ref LL_MPU_REGION_NUMBER5 542 * @arg @ref LL_MPU_REGION_NUMBER6 543 * @arg @ref LL_MPU_REGION_NUMBER7 544 * @retval None 545 */ 546 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) 547 { 548 /* Set Region number */ 549 WRITE_REG(MPU->RNR, Region); 550 /* Enable the MPU region */ 551 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 552 } 553 554 /** 555 * @brief Configure and enable a region 556 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n 557 * MPU_RBAR REGION LL_MPU_ConfigRegion\n 558 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n 559 * MPU_RASR XN LL_MPU_ConfigRegion\n 560 * MPU_RASR AP LL_MPU_ConfigRegion\n 561 * MPU_RASR S LL_MPU_ConfigRegion\n 562 * MPU_RASR C LL_MPU_ConfigRegion\n 563 * MPU_RASR B LL_MPU_ConfigRegion\n 564 * MPU_RASR SIZE LL_MPU_ConfigRegion 565 * @param Region This parameter can be one of the following values: 566 * @arg @ref LL_MPU_REGION_NUMBER0 567 * @arg @ref LL_MPU_REGION_NUMBER1 568 * @arg @ref LL_MPU_REGION_NUMBER2 569 * @arg @ref LL_MPU_REGION_NUMBER3 570 * @arg @ref LL_MPU_REGION_NUMBER4 571 * @arg @ref LL_MPU_REGION_NUMBER5 572 * @arg @ref LL_MPU_REGION_NUMBER6 573 * @arg @ref LL_MPU_REGION_NUMBER7 574 * @param Address Value of region base address 575 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF 576 * @param Attributes This parameter can be a combination of the following values: 577 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B 578 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB 579 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB 580 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB 581 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB 582 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB 583 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS 584 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO 585 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 586 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE 587 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE 588 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE 589 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE 590 * @retval None 591 */ 592 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) 593 { 594 /* Set Region number */ 595 WRITE_REG(MPU->RNR, Region); 596 /* Set base address */ 597 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); 598 /* Configure MPU */ 599 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); 600 } 601 602 /** 603 * @brief Disable a region 604 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n 605 * MPU_RASR ENABLE LL_MPU_DisableRegion 606 * @param Region This parameter can be one of the following values: 607 * @arg @ref LL_MPU_REGION_NUMBER0 608 * @arg @ref LL_MPU_REGION_NUMBER1 609 * @arg @ref LL_MPU_REGION_NUMBER2 610 * @arg @ref LL_MPU_REGION_NUMBER3 611 * @arg @ref LL_MPU_REGION_NUMBER4 612 * @arg @ref LL_MPU_REGION_NUMBER5 613 * @arg @ref LL_MPU_REGION_NUMBER6 614 * @arg @ref LL_MPU_REGION_NUMBER7 615 * @retval None 616 */ 617 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) 618 { 619 /* Set Region number */ 620 WRITE_REG(MPU->RNR, Region); 621 /* Disable the MPU region */ 622 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 623 } 624 625 /** 626 * @} 627 */ 628 629 #endif /* __MPU_PRESENT */ 630 /** 631 * @} 632 */ 633 634 /** 635 * @} 636 */ 637 638 /** 639 * @} 640 */ 641 642 #ifdef __cplusplus 643 } 644 #endif 645 646 #endif /* __STM32F4xx_LL_CORTEX_H */ 647