stm32f4xx_ll_utils.h
1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_ll_utils.h 4 * @author MCD Application Team 5 * @brief Header file of UTILS LL module. 6 @verbatim 7 ============================================================================== 8 ##### How to use this driver ##### 9 ============================================================================== 10 [..] 11 The LL UTILS driver contains a set of generic APIs that can be 12 used by user: 13 (+) Device electronic signature 14 (+) Timing functions 15 (+) PLL configuration functions 16 17 @endverbatim 18 ****************************************************************************** 19 * @attention 20 * 21 * Copyright (c) 2017 STMicroelectronics. 22 * All rights reserved. 23 * 24 * This software is licensed under terms that can be found in the LICENSE file 25 * in the root directory of this software component. 26 * If no LICENSE file comes with this software, it is provided AS-IS. 27 * 28 ****************************************************************************** 29 */ 30 31 /* Define to prevent recursive inclusion -------------------------------------*/ 32 #ifndef __STM32F4xx_LL_UTILS_H 33 #define __STM32F4xx_LL_UTILS_H 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /* Includes ------------------------------------------------------------------*/ 40 #include "stm32f4xx.h" 41 42 /** @addtogroup STM32F4xx_LL_Driver 43 * @{ 44 */ 45 46 /** @defgroup UTILS_LL UTILS 47 * @{ 48 */ 49 50 /* Private types -------------------------------------------------------------*/ 51 /* Private variables ---------------------------------------------------------*/ 52 53 /* Private constants ---------------------------------------------------------*/ 54 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants 55 * @{ 56 */ 57 58 /* Max delay can be used in LL_mDelay */ 59 #define LL_MAX_DELAY 0xFFFFFFFFU 60 61 /** 62 * @brief Unique device ID register base address 63 */ 64 #define UID_BASE_ADDRESS UID_BASE 65 66 /** 67 * @brief Flash size data register base address 68 */ 69 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE 70 71 /** 72 * @brief Package data register base address 73 */ 74 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE 75 76 /** 77 * @} 78 */ 79 80 /* Private macros ------------------------------------------------------------*/ 81 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros 82 * @{ 83 */ 84 /** 85 * @} 86 */ 87 /* Exported types ------------------------------------------------------------*/ 88 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures 89 * @{ 90 */ 91 /** 92 * @brief UTILS PLL structure definition 93 */ 94 typedef struct 95 { 96 uint32_t PLLM; /*!< Division factor for PLL VCO input clock. 97 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV 98 99 This feature can be modified afterwards using unitary function 100 @ref LL_RCC_PLL_ConfigDomain_SYS(). */ 101 102 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. 103 This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE 104 and Max_Data = @ref RCC_PLLN_MIN_VALUE 105 106 This feature can be modified afterwards using unitary function 107 @ref LL_RCC_PLL_ConfigDomain_SYS(). */ 108 109 uint32_t PLLP; /*!< Division for the main system clock. 110 This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV 111 112 This feature can be modified afterwards using unitary function 113 @ref LL_RCC_PLL_ConfigDomain_SYS(). */ 114 } LL_UTILS_PLLInitTypeDef; 115 116 /** 117 * @brief UTILS System, AHB and APB buses clock configuration structure definition 118 */ 119 typedef struct 120 { 121 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 122 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV 123 124 This feature can be modified afterwards using unitary function 125 @ref LL_RCC_SetAHBPrescaler(). */ 126 127 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 128 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV 129 130 This feature can be modified afterwards using unitary function 131 @ref LL_RCC_SetAPB1Prescaler(). */ 132 133 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 134 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV 135 136 This feature can be modified afterwards using unitary function 137 @ref LL_RCC_SetAPB2Prescaler(). */ 138 139 } LL_UTILS_ClkInitTypeDef; 140 141 /** 142 * @} 143 */ 144 145 /* Exported constants --------------------------------------------------------*/ 146 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants 147 * @{ 148 */ 149 150 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation 151 * @{ 152 */ 153 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ 154 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ 155 /** 156 * @} 157 */ 158 159 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE 160 * @{ 161 */ 162 #define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type */ 163 #define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type */ 164 #define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type */ 165 #define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type */ 166 #define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type */ 167 #define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U /*!< LQFP208 or TFBGA216 package type */ 168 #define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type */ 169 /** 170 * @} 171 */ 172 173 /** 174 * @} 175 */ 176 177 /* Exported macro ------------------------------------------------------------*/ 178 179 /* Exported functions --------------------------------------------------------*/ 180 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions 181 * @{ 182 */ 183 184 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE 185 * @{ 186 */ 187 188 /** 189 * @brief Get Word0 of the unique device identifier (UID based on 96 bits) 190 * @retval UID[31:0] 191 */ 192 __STATIC_INLINE uint32_t LL_GetUID_Word0(void) 193 { 194 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); 195 } 196 197 /** 198 * @brief Get Word1 of the unique device identifier (UID based on 96 bits) 199 * @retval UID[63:32] 200 */ 201 __STATIC_INLINE uint32_t LL_GetUID_Word1(void) 202 { 203 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); 204 } 205 206 /** 207 * @brief Get Word2 of the unique device identifier (UID based on 96 bits) 208 * @retval UID[95:64] 209 */ 210 __STATIC_INLINE uint32_t LL_GetUID_Word2(void) 211 { 212 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); 213 } 214 215 /** 216 * @brief Get Flash memory size 217 * @note This bitfield indicates the size of the device Flash memory expressed in 218 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. 219 * @retval FLASH_SIZE[15:0]: Flash memory size 220 */ 221 __STATIC_INLINE uint32_t LL_GetFlashSize(void) 222 { 223 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF); 224 } 225 226 /** 227 * @brief Get Package type 228 * @retval Returned value can be one of the following values: 229 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*) 230 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*) 231 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*) 232 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*) 233 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*) 234 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*) 235 * @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*) 236 * 237 * (*) value not defined in all devices. 238 */ 239 __STATIC_INLINE uint32_t LL_GetPackageType(void) 240 { 241 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); 242 } 243 244 /** 245 * @} 246 */ 247 248 /** @defgroup UTILS_LL_EF_DELAY DELAY 249 * @{ 250 */ 251 252 /** 253 * @brief This function configures the Cortex-M SysTick source of the time base. 254 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) 255 * @note When a RTOS is used, it is recommended to avoid changing the SysTick 256 * configuration by calling this function, for a delay use rather osDelay RTOS service. 257 * @param Ticks Number of ticks 258 * @retval None 259 */ 260 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) 261 { 262 /* Configure the SysTick to have interrupt in 1ms time base */ 263 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ 264 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 265 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 266 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ 267 } 268 269 void LL_Init1msTick(uint32_t HCLKFrequency); 270 void LL_mDelay(uint32_t Delay); 271 272 /** 273 * @} 274 */ 275 276 /** @defgroup UTILS_EF_SYSTEM SYSTEM 277 * @{ 278 */ 279 280 void LL_SetSystemCoreClock(uint32_t HCLKFrequency); 281 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); 282 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, 283 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 284 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, 285 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); 286 287 /** 288 * @} 289 */ 290 291 /** 292 * @} 293 */ 294 295 /** 296 * @} 297 */ 298 299 /** 300 * @} 301 */ 302 303 #ifdef __cplusplus 304 } 305 #endif 306 307 #endif /* __STM32F4xx_LL_UTILS_H */