stm32f4xx_ll_adc.c
1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_ll_adc.c 4 * @author MCD Application Team 5 * @brief ADC LL module driver 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 #if defined(USE_FULL_LL_DRIVER) 19 20 /* Includes ------------------------------------------------------------------*/ 21 #include "stm32f4xx_ll_adc.h" 22 #include "stm32f4xx_ll_bus.h" 23 24 #ifdef USE_FULL_ASSERT 25 #include "stm32_assert.h" 26 #else 27 #define assert_param(expr) ((void)0U) 28 #endif 29 30 /** @addtogroup STM32F4xx_LL_Driver 31 * @{ 32 */ 33 34 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 35 36 /** @addtogroup ADC_LL ADC 37 * @{ 38 */ 39 40 /* Private types -------------------------------------------------------------*/ 41 /* Private variables ---------------------------------------------------------*/ 42 /* Private constants ---------------------------------------------------------*/ 43 /* Private macros ------------------------------------------------------------*/ 44 45 /** @addtogroup ADC_LL_Private_Macros 46 * @{ 47 */ 48 49 /* Check of parameters for configuration of ADC hierarchical scope: */ 50 /* common to several ADC instances. */ 51 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ 52 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ 53 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ 54 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ 55 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ 56 ) 57 58 /* Check of parameters for configuration of ADC hierarchical scope: */ 59 /* ADC instance. */ 60 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ 61 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ 62 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ 63 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ 64 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ 65 ) 66 67 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ 68 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ 69 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ 70 ) 71 72 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ 73 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ 74 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ 75 ) 76 77 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ 78 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ 79 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ 80 ) 81 82 /* Check of parameters for configuration of ADC hierarchical scope: */ 83 /* ADC group regular */ 84 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ 85 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ 86 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ 87 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ 88 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ 89 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ 90 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ 91 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ 92 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ 93 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ 94 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ 95 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ 96 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ 97 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \ 98 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ 99 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ 100 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ 101 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ 102 ) 103 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ 104 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ 105 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ 106 ) 107 108 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ 109 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ 110 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ 111 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ 112 ) 113 114 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ 115 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ 116 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ 117 ) 118 119 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ 120 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ 121 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ 122 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ 123 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ 124 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ 125 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ 126 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ 127 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ 128 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ 129 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ 130 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ 131 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ 132 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ 133 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ 134 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ 135 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ 136 ) 137 138 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ 139 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ 140 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ 141 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ 142 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ 143 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ 144 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ 145 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ 146 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ 147 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ 148 ) 149 150 /* Check of parameters for configuration of ADC hierarchical scope: */ 151 /* ADC group injected */ 152 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ 153 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ 154 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ 155 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ 156 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ 157 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ 158 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \ 159 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ 160 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ 161 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ 162 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ 163 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ 164 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ 165 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ 166 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ 167 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \ 168 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ 169 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ 170 ) 171 172 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ 173 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ 174 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ 175 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ 176 ) 177 178 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ 179 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ 180 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ 181 ) 182 183 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ 184 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ 185 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ 186 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ 187 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ 188 ) 189 190 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ 191 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ 192 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ 193 ) 194 195 #if defined(ADC_MULTIMODE_SUPPORT) 196 /* Check of parameters for configuration of ADC hierarchical scope: */ 197 /* multimode. */ 198 #if defined(ADC3) 199 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ 200 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ 201 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ 202 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ 203 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ 204 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ 205 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ 206 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ 207 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ 208 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ 209 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ 210 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ 211 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ 212 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ 213 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ 214 ) 215 #else 216 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ 217 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ 218 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ 219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ 220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ 221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ 222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ 223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ 224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ 225 ) 226 #endif 227 228 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ 229 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ 230 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ 231 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ 232 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ 233 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ 234 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ 235 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ 236 ) 237 238 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ 239 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ 240 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ 241 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ 242 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ 243 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ 244 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ 245 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ 246 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ 247 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ 248 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ 249 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ 250 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ 251 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ 252 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ 253 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ 254 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ 255 ) 256 257 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ 258 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ 259 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ 260 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ 261 ) 262 263 #endif /* ADC_MULTIMODE_SUPPORT */ 264 /** 265 * @} 266 */ 267 268 269 /* Private function prototypes -----------------------------------------------*/ 270 271 /* Exported functions --------------------------------------------------------*/ 272 /** @addtogroup ADC_LL_Exported_Functions 273 * @{ 274 */ 275 276 /** @addtogroup ADC_LL_EF_Init 277 * @{ 278 */ 279 280 /** 281 * @brief De-initialize registers of all ADC instances belonging to 282 * the same ADC common instance to their default reset values. 283 * @param ADCxy_COMMON ADC common instance 284 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 285 * @retval An ErrorStatus enumeration value: 286 * - SUCCESS: ADC common registers are de-initialized 287 * - ERROR: not applicable 288 */ 289 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) 290 { 291 /* Check the parameters */ 292 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 293 294 295 /* Force reset of ADC clock (core clock) */ 296 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); 297 298 /* Release reset of ADC clock (core clock) */ 299 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); 300 301 return SUCCESS; 302 } 303 304 /** 305 * @brief Initialize some features of ADC common parameters 306 * (all ADC instances belonging to the same ADC common instance) 307 * and multimode (for devices with several ADC instances available). 308 * @note The setting of ADC common parameters is conditioned to 309 * ADC instances state: 310 * All ADC instances belonging to the same ADC common instance 311 * must be disabled. 312 * @param ADCxy_COMMON ADC common instance 313 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 314 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 315 * @retval An ErrorStatus enumeration value: 316 * - SUCCESS: ADC common registers are initialized 317 * - ERROR: ADC common registers are not initialized 318 */ 319 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 320 { 321 ErrorStatus status = SUCCESS; 322 323 /* Check the parameters */ 324 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 325 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); 326 327 #if defined(ADC_MULTIMODE_SUPPORT) 328 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); 329 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 330 { 331 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); 332 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); 333 } 334 #endif /* ADC_MULTIMODE_SUPPORT */ 335 336 /* Note: Hardware constraint (refer to description of functions */ 337 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ 338 /* On this STM32 series, setting of these features is conditioned to */ 339 /* ADC state: */ 340 /* All ADC instances of the ADC common group must be disabled. */ 341 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) 342 { 343 /* Configuration of ADC hierarchical scope: */ 344 /* - common to several ADC */ 345 /* (all ADC instances belonging to the same ADC common instance) */ 346 /* - Set ADC clock (conversion clock) */ 347 /* - multimode (if several ADC instances available on the */ 348 /* selected device) */ 349 /* - Set ADC multimode configuration */ 350 /* - Set ADC multimode DMA transfer */ 351 /* - Set ADC multimode: delay between 2 sampling phases */ 352 #if defined(ADC_MULTIMODE_SUPPORT) 353 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 354 { 355 MODIFY_REG(ADCxy_COMMON->CCR, 356 ADC_CCR_ADCPRE 357 | ADC_CCR_MULTI 358 | ADC_CCR_DMA 359 | ADC_CCR_DDS 360 | ADC_CCR_DELAY 361 , 362 ADC_CommonInitStruct->CommonClock 363 | ADC_CommonInitStruct->Multimode 364 | ADC_CommonInitStruct->MultiDMATransfer 365 | ADC_CommonInitStruct->MultiTwoSamplingDelay 366 ); 367 } 368 else 369 { 370 MODIFY_REG(ADCxy_COMMON->CCR, 371 ADC_CCR_ADCPRE 372 | ADC_CCR_MULTI 373 | ADC_CCR_DMA 374 | ADC_CCR_DDS 375 | ADC_CCR_DELAY 376 , 377 ADC_CommonInitStruct->CommonClock 378 | LL_ADC_MULTI_INDEPENDENT 379 ); 380 } 381 #else 382 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); 383 #endif 384 } 385 else 386 { 387 /* Initialization error: One or several ADC instances belonging to */ 388 /* the same ADC common instance are not disabled. */ 389 status = ERROR; 390 } 391 392 return status; 393 } 394 395 /** 396 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. 397 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 398 * whose fields will be set to default values. 399 * @retval None 400 */ 401 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 402 { 403 /* Set ADC_CommonInitStruct fields to default values */ 404 /* Set fields of ADC common */ 405 /* (all ADC instances belonging to the same ADC common instance) */ 406 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; 407 408 #if defined(ADC_MULTIMODE_SUPPORT) 409 /* Set fields of ADC multimode */ 410 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; 411 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; 412 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; 413 #endif /* ADC_MULTIMODE_SUPPORT */ 414 } 415 416 /** 417 * @brief De-initialize registers of the selected ADC instance 418 * to their default reset values. 419 * @note To reset all ADC instances quickly (perform a hard reset), 420 * use function @ref LL_ADC_CommonDeInit(). 421 * @param ADCx ADC instance 422 * @retval An ErrorStatus enumeration value: 423 * - SUCCESS: ADC registers are de-initialized 424 * - ERROR: ADC registers are not de-initialized 425 */ 426 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) 427 { 428 ErrorStatus status = SUCCESS; 429 430 /* Check the parameters */ 431 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 432 433 /* Disable ADC instance if not already disabled. */ 434 if (LL_ADC_IsEnabled(ADCx) == 1UL) 435 { 436 /* Set ADC group regular trigger source to SW start to ensure to not */ 437 /* have an external trigger event occurring during the conversion stop */ 438 /* ADC disable process. */ 439 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); 440 441 /* Set ADC group injected trigger source to SW start to ensure to not */ 442 /* have an external trigger event occurring during the conversion stop */ 443 /* ADC disable process. */ 444 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); 445 446 /* Disable the ADC instance */ 447 LL_ADC_Disable(ADCx); 448 } 449 450 /* Check whether ADC state is compliant with expected state */ 451 /* (hardware requirements of bits state to reset registers below) */ 452 if (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) 453 { 454 /* ========== Reset ADC registers ========== */ 455 /* Reset register SR */ 456 CLEAR_BIT(ADCx->SR, 457 (LL_ADC_FLAG_STRT 458 | LL_ADC_FLAG_JSTRT 459 | LL_ADC_FLAG_EOCS 460 | LL_ADC_FLAG_OVR 461 | LL_ADC_FLAG_JEOS 462 | LL_ADC_FLAG_AWD1) 463 ); 464 465 /* Reset register CR1 */ 466 CLEAR_BIT(ADCx->CR1, 467 (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN 468 | ADC_CR1_JAWDEN 469 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN 470 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN 471 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE 472 | ADC_CR1_AWDCH) 473 ); 474 475 /* Reset register CR2 */ 476 CLEAR_BIT(ADCx->CR2, 477 (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL 478 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL 479 | ADC_CR2_ALIGN | ADC_CR2_EOCS 480 | ADC_CR2_DDS | ADC_CR2_DMA 481 | ADC_CR2_CONT | ADC_CR2_ADON) 482 ); 483 484 /* Reset register SMPR1 */ 485 CLEAR_BIT(ADCx->SMPR1, 486 (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 487 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 488 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) 489 ); 490 491 /* Reset register SMPR2 */ 492 CLEAR_BIT(ADCx->SMPR2, 493 (ADC_SMPR2_SMP9 494 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 495 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 496 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) 497 ); 498 499 /* Reset register JOFR1 */ 500 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); 501 /* Reset register JOFR2 */ 502 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); 503 /* Reset register JOFR3 */ 504 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); 505 /* Reset register JOFR4 */ 506 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); 507 508 /* Reset register HTR */ 509 SET_BIT(ADCx->HTR, ADC_HTR_HT); 510 /* Reset register LTR */ 511 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); 512 513 /* Reset register SQR1 */ 514 CLEAR_BIT(ADCx->SQR1, 515 (ADC_SQR1_L 516 | ADC_SQR1_SQ16 517 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) 518 ); 519 520 /* Reset register SQR2 */ 521 CLEAR_BIT(ADCx->SQR2, 522 (ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 523 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) 524 ); 525 526 /* Reset register SQR3 */ 527 CLEAR_BIT(ADCx->SQR3, 528 (ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 529 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) 530 ); 531 532 /* Reset register JSQR */ 533 CLEAR_BIT(ADCx->JSQR, 534 (ADC_JSQR_JL 535 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 536 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) 537 ); 538 539 /* Reset register DR */ 540 /* bits in access mode read only, no direct reset applicable */ 541 542 /* Reset registers JDR1, JDR2, JDR3, JDR4 */ 543 /* bits in access mode read only, no direct reset applicable */ 544 545 /* Reset register CCR */ 546 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); 547 } 548 549 return status; 550 } 551 552 /** 553 * @brief Initialize some features of ADC instance. 554 * @note These parameters have an impact on ADC scope: ADC instance. 555 * Affects both group regular and group injected (availability 556 * of ADC group injected depends on STM32 families). 557 * Refer to corresponding unitary functions into 558 * @ref ADC_LL_EF_Configuration_ADC_Instance . 559 * @note The setting of these parameters by function @ref LL_ADC_Init() 560 * is conditioned to ADC state: 561 * ADC instance must be disabled. 562 * This condition is applied to all ADC features, for efficiency 563 * and compatibility over all STM32 families. However, the different 564 * features can be set under different ADC state conditions 565 * (setting possible with ADC enabled without conversion on going, 566 * ADC enabled with conversion on going, ...) 567 * Each feature can be updated afterwards with a unitary function 568 * and potentially with ADC in a different state than disabled, 569 * refer to description of each function for setting 570 * conditioned to ADC state. 571 * @note After using this function, some other features must be configured 572 * using LL unitary functions. 573 * The minimum configuration remaining to be done is: 574 * - Set ADC group regular or group injected sequencer: 575 * map channel on the selected sequencer rank. 576 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 577 * - Set ADC channel sampling time 578 * Refer to function LL_ADC_SetChannelSamplingTime(); 579 * @param ADCx ADC instance 580 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 581 * @retval An ErrorStatus enumeration value: 582 * - SUCCESS: ADC registers are initialized 583 * - ERROR: ADC registers are not initialized 584 */ 585 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) 586 { 587 ErrorStatus status = SUCCESS; 588 589 /* Check the parameters */ 590 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 591 592 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); 593 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); 594 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); 595 596 /* Note: Hardware constraint (refer to description of this function): */ 597 /* ADC instance must be disabled. */ 598 if (LL_ADC_IsEnabled(ADCx) == 0UL) 599 { 600 /* Configuration of ADC hierarchical scope: */ 601 /* - ADC instance */ 602 /* - Set ADC data resolution */ 603 /* - Set ADC conversion data alignment */ 604 MODIFY_REG(ADCx->CR1, 605 ADC_CR1_RES 606 | ADC_CR1_SCAN 607 , 608 ADC_InitStruct->Resolution 609 | ADC_InitStruct->SequencersScanMode 610 ); 611 612 MODIFY_REG(ADCx->CR2, 613 ADC_CR2_ALIGN 614 , 615 ADC_InitStruct->DataAlignment 616 ); 617 618 } 619 else 620 { 621 /* Initialization error: ADC instance is not disabled. */ 622 status = ERROR; 623 } 624 return status; 625 } 626 627 /** 628 * @brief Set each @ref LL_ADC_InitTypeDef field to default value. 629 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure 630 * whose fields will be set to default values. 631 * @retval None 632 */ 633 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) 634 { 635 /* Set ADC_InitStruct fields to default values */ 636 /* Set fields of ADC instance */ 637 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; 638 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; 639 640 /* Enable scan mode to have a generic behavior with ADC of other */ 641 /* STM32 families, without this setting available: */ 642 /* ADC group regular sequencer and ADC group injected sequencer depend */ 643 /* only of their own configuration. */ 644 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; 645 646 } 647 648 /** 649 * @brief Initialize some features of ADC group regular. 650 * @note These parameters have an impact on ADC scope: ADC group regular. 651 * Refer to corresponding unitary functions into 652 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 653 * (functions with prefix "REG"). 654 * @note The setting of these parameters by function @ref LL_ADC_Init() 655 * is conditioned to ADC state: 656 * ADC instance must be disabled. 657 * This condition is applied to all ADC features, for efficiency 658 * and compatibility over all STM32 families. However, the different 659 * features can be set under different ADC state conditions 660 * (setting possible with ADC enabled without conversion on going, 661 * ADC enabled with conversion on going, ...) 662 * Each feature can be updated afterwards with a unitary function 663 * and potentially with ADC in a different state than disabled, 664 * refer to description of each function for setting 665 * conditioned to ADC state. 666 * @note After using this function, other features must be configured 667 * using LL unitary functions. 668 * The minimum configuration remaining to be done is: 669 * - Set ADC group regular or group injected sequencer: 670 * map channel on the selected sequencer rank. 671 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 672 * - Set ADC channel sampling time 673 * Refer to function LL_ADC_SetChannelSamplingTime(); 674 * @param ADCx ADC instance 675 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 676 * @retval An ErrorStatus enumeration value: 677 * - SUCCESS: ADC registers are initialized 678 * - ERROR: ADC registers are not initialized 679 */ 680 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 681 { 682 ErrorStatus status = SUCCESS; 683 684 /* Check the parameters */ 685 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 686 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); 687 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); 688 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 689 { 690 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); 691 } 692 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); 693 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); 694 695 /* ADC group regular continuous mode and discontinuous mode */ 696 /* can not be enabled simultenaeously */ 697 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) 698 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); 699 700 /* Note: Hardware constraint (refer to description of this function): */ 701 /* ADC instance must be disabled. */ 702 if (LL_ADC_IsEnabled(ADCx) == 0UL) 703 { 704 /* Configuration of ADC hierarchical scope: */ 705 /* - ADC group regular */ 706 /* - Set ADC group regular trigger source */ 707 /* - Set ADC group regular sequencer length */ 708 /* - Set ADC group regular sequencer discontinuous mode */ 709 /* - Set ADC group regular continuous mode */ 710 /* - Set ADC group regular conversion data transfer: no transfer or */ 711 /* transfer by DMA, and DMA requests mode */ 712 /* Note: On this STM32 series, ADC trigger edge is set when starting */ 713 /* ADC conversion. */ 714 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ 715 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 716 { 717 MODIFY_REG(ADCx->CR1, 718 ADC_CR1_DISCEN 719 | ADC_CR1_DISCNUM 720 , 721 ADC_REG_InitStruct->SequencerDiscont 722 ); 723 } 724 else 725 { 726 MODIFY_REG(ADCx->CR1, 727 ADC_CR1_DISCEN 728 | ADC_CR1_DISCNUM 729 , 730 LL_ADC_REG_SEQ_DISCONT_DISABLE 731 ); 732 } 733 734 MODIFY_REG(ADCx->CR2, 735 ADC_CR2_EXTSEL 736 | ADC_CR2_EXTEN 737 | ADC_CR2_CONT 738 | ADC_CR2_DMA 739 | ADC_CR2_DDS 740 , 741 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) 742 | ADC_REG_InitStruct->ContinuousMode 743 | ADC_REG_InitStruct->DMATransfer 744 ); 745 746 /* Set ADC group regular sequencer length and scan direction */ 747 /* Note: Hardware constraint (refer to description of this function): */ 748 /* Note: If ADC instance feature scan mode is disabled */ 749 /* (refer to ADC instance initialization structure */ 750 /* parameter @ref SequencersScanMode */ 751 /* or function @ref LL_ADC_SetSequencersScanMode() ), */ 752 /* this parameter is discarded. */ 753 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); 754 } 755 else 756 { 757 /* Initialization error: ADC instance is not disabled. */ 758 status = ERROR; 759 } 760 return status; 761 } 762 763 /** 764 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. 765 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 766 * whose fields will be set to default values. 767 * @retval None 768 */ 769 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 770 { 771 /* Set ADC_REG_InitStruct fields to default values */ 772 /* Set fields of ADC group regular */ 773 /* Note: On this STM32 series, ADC trigger edge is set when starting */ 774 /* ADC conversion. */ 775 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ 776 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; 777 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; 778 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; 779 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; 780 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; 781 } 782 783 /** 784 * @brief Initialize some features of ADC group injected. 785 * @note These parameters have an impact on ADC scope: ADC group injected. 786 * Refer to corresponding unitary functions into 787 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 788 * (functions with prefix "INJ"). 789 * @note The setting of these parameters by function @ref LL_ADC_Init() 790 * is conditioned to ADC state: 791 * ADC instance must be disabled. 792 * This condition is applied to all ADC features, for efficiency 793 * and compatibility over all STM32 families. However, the different 794 * features can be set under different ADC state conditions 795 * (setting possible with ADC enabled without conversion on going, 796 * ADC enabled with conversion on going, ...) 797 * Each feature can be updated afterwards with a unitary function 798 * and potentially with ADC in a different state than disabled, 799 * refer to description of each function for setting 800 * conditioned to ADC state. 801 * @note After using this function, other features must be configured 802 * using LL unitary functions. 803 * The minimum configuration remaining to be done is: 804 * - Set ADC group injected sequencer: 805 * map channel on the selected sequencer rank. 806 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). 807 * - Set ADC channel sampling time 808 * Refer to function LL_ADC_SetChannelSamplingTime(); 809 * @param ADCx ADC instance 810 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 811 * @retval An ErrorStatus enumeration value: 812 * - SUCCESS: ADC registers are initialized 813 * - ERROR: ADC registers are not initialized 814 */ 815 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 816 { 817 ErrorStatus status = SUCCESS; 818 819 /* Check the parameters */ 820 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 821 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); 822 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); 823 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) 824 { 825 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); 826 } 827 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); 828 829 /* Note: Hardware constraint (refer to description of this function): */ 830 /* ADC instance must be disabled. */ 831 if (LL_ADC_IsEnabled(ADCx) == 0UL) 832 { 833 /* Configuration of ADC hierarchical scope: */ 834 /* - ADC group injected */ 835 /* - Set ADC group injected trigger source */ 836 /* - Set ADC group injected sequencer length */ 837 /* - Set ADC group injected sequencer discontinuous mode */ 838 /* - Set ADC group injected conversion trigger: independent or */ 839 /* from ADC group regular */ 840 /* Note: On this STM32 series, ADC trigger edge is set when starting */ 841 /* ADC conversion. */ 842 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ 843 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 844 { 845 MODIFY_REG(ADCx->CR1, 846 ADC_CR1_JDISCEN 847 | ADC_CR1_JAUTO 848 , 849 ADC_INJ_InitStruct->SequencerDiscont 850 | ADC_INJ_InitStruct->TrigAuto 851 ); 852 } 853 else 854 { 855 MODIFY_REG(ADCx->CR1, 856 ADC_CR1_JDISCEN 857 | ADC_CR1_JAUTO 858 , 859 LL_ADC_REG_SEQ_DISCONT_DISABLE 860 | ADC_INJ_InitStruct->TrigAuto 861 ); 862 } 863 864 MODIFY_REG(ADCx->CR2, 865 ADC_CR2_JEXTSEL 866 | ADC_CR2_JEXTEN 867 , 868 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) 869 ); 870 871 /* Note: Hardware constraint (refer to description of this function): */ 872 /* Note: If ADC instance feature scan mode is disabled */ 873 /* (refer to ADC instance initialization structure */ 874 /* parameter @ref SequencersScanMode */ 875 /* or function @ref LL_ADC_SetSequencersScanMode() ), */ 876 /* this parameter is discarded. */ 877 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); 878 } 879 else 880 { 881 /* Initialization error: ADC instance is not disabled. */ 882 status = ERROR; 883 } 884 return status; 885 } 886 887 /** 888 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. 889 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 890 * whose fields will be set to default values. 891 * @retval None 892 */ 893 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 894 { 895 /* Set ADC_INJ_InitStruct fields to default values */ 896 /* Set fields of ADC group injected */ 897 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; 898 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; 899 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; 900 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; 901 } 902 903 /** 904 * @} 905 */ 906 907 /** 908 * @} 909 */ 910 911 /** 912 * @} 913 */ 914 915 #endif /* ADC1 || ADC2 || ADC3 */ 916 917 /** 918 * @} 919 */ 920 921 #endif /* USE_FULL_LL_DRIVER */ 922