network.cpp
1 2 #include <stdint.h> 3 #include <string.h> 4 5 #include "emu.h" 6 7 8 #ifdef USE_ENC28J60 9 #include <enc28j60.h> 10 11 byte ENC28J60::buffer[1514]; 12 //uint8_t net_mac[6] = { 0x90, 0xAD, 0xBE, 0xEF, 0x13, 0x37 }; 13 uint8_t net_mac[6] = { 0x2C, 0xFD, 0x13, 0x37, 0x13, 0x37 }; 14 15 extern union _bytewordregs_ regs; 16 extern uint16_t segregs[6]; 17 18 struct netstruct { 19 uint8_t enabled; 20 uint8_t canrecv; 21 uint16_t pktlen; 22 } net; 23 24 void net_handler() { 25 uint32_t i; 26 uint16_t j; 27 //if (ethif==254) return; //networking not enabled 28 switch (regs.byteregs[regah]) { //function number 29 case 0x00: //enable packet reception 30 net.enabled = 1; 31 net.canrecv = 1; 32 return; 33 case 0x01: //send packet of CX at DS:SI 34 //if (verbose) { 35 //Serial.println("Sending packet of %u bytes.", regs.wordregs[regcx]); 36 //} 37 //sendpkt (&RAM[ ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi]], regs.wordregs[regcx]); 38 i = ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi]; 39 for (j=0; j<net.pktlen; j++) { 40 ENC28J60::buffer[j] = read86(i++); 41 } 42 SPI.setClockDivider(SPI_CLOCK_ENC28J60); 43 ENC28J60::packetSend(segregs[regcx]); 44 SPI.setClockDivider(SPI_CLOCK_SPIRAM); 45 return; 46 case 0x02: //return packet info (packet buffer in DS:SI, length in CX) 47 segregs[regds] = 0xD000; 48 regs.wordregs[regsi] = 0x0000; 49 regs.wordregs[regcx] = net.pktlen; 50 return; 51 case 0x03: //copy packet to final destination (given in ES:DI) 52 //memcpy (&RAM[ ( (uint32_t) segregs[reges] << 4) + (uint32_t) regs.wordregs[regdi]], &RAM[0xD0000], net.pktlen); 53 i = ( (uint32_t) segregs[reges] << 4) + (uint32_t) regs.wordregs[regdi]; 54 for (j=0; j<net.pktlen; j++) { 55 write86(i++, ENC28J60::buffer[j]); 56 } 57 net.canrecv = 1; 58 net.pktlen = 0; 59 return; 60 case 0x04: //disable packets 61 net.enabled = 0; 62 net.canrecv = 0; 63 return; 64 case 0x05: //DEBUG: dump packet (DS:SI) of CX bytes to stdout 65 /*for (i=0; i<regs.wordregs[regcx]; i++) { 66 printf ("%c", RAM[ ( (uint32_t) segregs[regds] << 4) + (uint32_t) regs.wordregs[regsi] + i]); 67 }*/ 68 return; 69 case 0x06: //DEBUG: print milestone string 70 //print("PACKET DRIVER MILESTONE REACHED\n"); 71 return; 72 } 73 } 74 75 uint8_t net_read_ram(uint32_t addr32) { 76 if (addr32 < 1514) return ENC28J60::buffer[addr32]; 77 return 0; 78 } 79 80 /*void net_write_ram(uint32_t addr32, uint8_t value) { 81 if (addr32 < 1514) ENC28J60::buffer[addr32] = value; 82 }*/ 83 84 void net_loop() { 85 uint16_t i, len; 86 uint8_t cc; 87 if (!net.enabled || !net.canrecv) return; 88 SPI.setClockDivider(SPI_CLOCK_ENC28J60); 89 len = ENC28J60::packetReceive(); 90 SPI.setClockDivider(SPI_CLOCK_SPIRAM); 91 if (len > 0) { 92 for (i=0; i<len; i++) { 93 Serial.print(ENC28J60::buffer[i], HEX); 94 Serial.write(' '); 95 } 96 Serial.println(""); 97 Serial.println(""); 98 net.canrecv = 0; 99 net.pktlen = len; 100 doirq(6); 101 } 102 } 103 104 void net_init() { 105 uint8_t ret; 106 Serial.println("enter net_init"); 107 //SPI.setClockDivider(SPI_CLOCK_ENC28J60); 108 ret = ENC28J60::initialize(1514, net_mac, NET_PIN); 109 //SPI.setClockDivider(SPI_CLOCK_LCD); 110 Serial.print("net init result = "); 111 Serial.println(ret); 112 ENC28J60::enablePromiscuous(); 113 //ENC28J60::broadcast_enabled = true; 114 while(1) { 115 uint16_t len, i; 116 //delay(100); 117 //SPI.setClockDivider(SPI_CLOCK_ENC28J60); 118 len = ENC28J60::packetReceive(); 119 //SPI.setClockDivider(SPI_CLOCK_LCD); 120 if (len > 0) { 121 for (i=0; i<len; i++) { 122 Serial.print(ENC28J60::buffer[i], HEX); 123 Serial.write(' '); 124 } 125 Serial.println(""); 126 Serial.println(""); 127 } 128 } 129 } 130 #else 131 uint8_t net_mac[6] = { 0x2C, 0xFD, 0x13, 0x37, 0x13, 0x37 }; 132 133 134 void net_init() { 135 } 136 137 void net_loop() { 138 } 139 140 void net_handler() { 141 } 142 uint8_t net_read_ram(uint32_t addr32) { 143 return 0; 144 } 145 #endif 146