cpu.c
1 2 /* 3 * O2EM Freeware Odyssey2 / Videopac+ Emulator 4 * 5 * Created by Daniel Boris <dboris@comcast.net> (c) 1997,1998 6 * 7 * Developed by Andre de la Rocha <adlroc@users.sourceforge.net> 8 * 9 * http://o2em.sourceforge.net 10 * 11 * 12 * 13 * 8048 microcontroller emulation 14 */ 15 16 17 #include <stdio.h> 18 #include "types.h" 19 #include "vmachine.h" 20 //#include "voice.h" 21 #include "vdc.h" 22 //#include "vpp.h" 23 #include "cpu.h" 24 25 26 Byte acc; /* Accumulator */ 27 ADDRESS pc; /* Program counter */ 28 long clk; /* clock */ 29 30 Byte itimer; /* Internal timer */ 31 Byte reg_pnt; /* pointer to register bank */ 32 Byte timer_on; /* 0=timer off/1=timer on */ 33 Byte count_on; /* 0=count off/1=count on */ 34 Byte psw; /* Processor status word */ 35 Byte sp; /* Stack pointer (part of psw) */ 36 37 Byte p1; /* I/O port 1 */ 38 Byte p2; /* I/O port 2 */ 39 Byte xirq_pend; /* external IRQ pending */ 40 Byte tirq_pend; /* timer IRQ pending */ 41 Byte t_flag; /* Timer flag */ 42 43 static ADDRESS lastpc; 44 static ADDRESS A11; /* PC bit 11 */ 45 static ADDRESS A11ff; 46 static Byte bs; /* Register Bank (part of psw) */ 47 static Byte f0; /* Flag Bit (part of psw) */ 48 static Byte f1; /* Flag Bit 1 */ 49 static Byte ac; /* Aux Carry (part of psw) */ 50 static Byte cy; /* Carry flag (part of psw) */ 51 static Byte xirq_en; /* external IRQ's enabled */ 52 static Byte tirq_en; /* Timer IRQ enabled */ 53 static Byte irq_ex; /* IRQ executing */ 54 55 static int master_count; 56 57 58 #define push(d) {intRAM[sp++] = (d); if (sp > 23) sp = 8;} 59 #define pull() (sp--, (sp < 8)?(sp=23):0, intRAM[sp]) 60 #define make_psw() {psw = (cy << 7) | ac | f0 | bs | 0x08; psw = psw | ((sp - 8) >> 1);} 61 #define illegal(o) {} 62 #define undef(i) {printf("** unimplemented instruction %x, %x**\n",i,pc);} 63 64 65 void init_cpu(void){ 66 pc=0; 67 sp=8; 68 bs=0; 69 p1=p2=0xFF; 70 ac=cy=f0=0; 71 A11=A11ff=0; 72 timer_on=0; 73 count_on=0; 74 reg_pnt=0; 75 tirq_en=xirq_en=irq_ex=xirq_pend=tirq_pend=0; 76 } 77 78 79 void ext_IRQ(void){ 80 int_clk = 5; /* length of pulse on /INT */ 81 if (xirq_en && !irq_ex) { 82 irq_ex=1; 83 xirq_pend=0; 84 clk+=2; 85 make_psw(); 86 push(pc & 0xFF); 87 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 88 pc = 0x03; 89 A11ff=A11; 90 A11=0; 91 } 92 if (pendirq && (!xirq_en)) xirq_pend=1; 93 } 94 95 96 void tim_IRQ(void){ 97 if (tirq_en && !irq_ex) { 98 irq_ex=2; 99 tirq_pend=0; 100 clk+=2; 101 make_psw(); 102 push(pc & 0xFF); 103 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 104 pc = 0x07; 105 A11ff=A11; 106 A11=0; 107 } 108 if (pendirq && (!tirq_en)) tirq_pend=1; 109 } 110 111 112 void make_psw_debug(void){ 113 make_psw(); 114 } 115 116 117 118 void cpu_exec(void) { 119 Byte op; 120 ADDRESS adr; 121 Byte dat; 122 int temp; 123 124 for (;;) { 125 126 clk=0; 127 128 lastpc=pc; 129 op=rom[pc++]; 130 switch (op) { 131 case 0x00: /* NOP */ 132 clk++; 133 break; 134 case 0x01: /* ILL */ 135 illegal(op); 136 clk++; 137 break; 138 case 0x02: /* OUTL BUS,A */ 139 clk+=2; 140 undef(0x02); 141 break; 142 case 0x03: /* ADD A,#data */ 143 clk+=2; 144 cy=ac=0; 145 dat=rom[pc++]; 146 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 147 temp=acc+dat; 148 if (temp > 0xFF) cy=1; 149 acc=(temp & 0xFF); 150 break; 151 case 0x04: /* JMP */ 152 pc=rom[pc] | A11; 153 clk+=2; 154 break; 155 case 0x05: /* EN I */ 156 xirq_en=1; 157 clk++; 158 break; 159 case 0x06: /* ILL */ 160 clk++; 161 illegal(op); 162 break; 163 case 0x07: /* DEC A */ 164 acc--; 165 clk++; 166 break; 167 case 0x08: /* INS A,BUS*/ 168 clk+=2; 169 acc=in_bus(); 170 break; 171 case 0x09: /* IN A,Pp */ 172 acc=p1; 173 clk+=2; 174 break; 175 case 0x0A: /* IN A,Pp */ 176 acc=read_P2(); 177 clk+=2; 178 break; 179 case 0x0B: /* ILL */ 180 clk++; 181 illegal(op); 182 case 0x0C: /* MOVD A,P4 */ 183 clk+=2; 184 //acc=read_PB(0); 185 break; 186 case 0x0D: /* MOVD A,P5 */ 187 clk+=2; 188 //acc=read_PB(1); 189 break; 190 case 0x0E: /* MOVD A,P6 */ 191 clk+=2; 192 //acc=read_PB(2); 193 break; 194 case 0x0F: /* MOVD A,P7 */ 195 clk+=2; 196 //acc=read_PB(3); 197 break; 198 case 0x10: /* INC @Ri */ 199 intRAM[intRAM[reg_pnt] & 0x3F]++; 200 clk++; 201 break; 202 case 0x11: /* INC @Ri */ 203 intRAM[intRAM[reg_pnt+1] & 0x3F]++; 204 clk++; 205 break; 206 case 0x12: /* JBb address */ 207 clk+=2; 208 dat = rom[pc]; 209 if (acc & 0x01) 210 pc=(pc & 0xF00) | dat; 211 else 212 pc++; 213 break; 214 case 0x13: /* ADDC A,#data */ 215 clk+=2; 216 dat=rom[pc++]; 217 ac=0; 218 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40; 219 temp=acc+dat+cy; 220 cy=0; 221 if (temp > 0xFF) cy=1; 222 acc=(temp & 0xFF); 223 break; 224 225 case 0x14: /* CALL */ 226 make_psw(); 227 adr = rom[pc] | A11; 228 pc++; 229 clk+=2; 230 push(pc & 0xFF); 231 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 232 pc = adr; 233 break; 234 case 0x15: /* DIS I */ 235 xirq_en=0; 236 clk++; 237 break; 238 case 0x16: /* JTF */ 239 clk+=2; 240 dat = rom[pc]; 241 if (t_flag) 242 pc=(pc & 0xF00) | dat; 243 else 244 pc++; 245 t_flag=0; 246 break; 247 case 0x17: /* INC A */ 248 acc++; 249 clk++; 250 break; 251 case 0x18: /* INC Rr */ 252 intRAM[reg_pnt]++; 253 clk++; 254 break; 255 case 0x19: /* INC Rr */ 256 intRAM[reg_pnt+1]++; 257 clk++; 258 break; 259 case 0x1A: /* INC Rr */ 260 intRAM[reg_pnt+2]++; 261 clk++; 262 break; 263 case 0x1B: /* INC Rr */ 264 intRAM[reg_pnt+3]++; 265 clk++; 266 break; 267 case 0x1C: /* INC Rr */ 268 intRAM[reg_pnt+4]++; 269 clk++; 270 break; 271 case 0x1D: /* INC Rr */ 272 intRAM[reg_pnt+5]++; 273 clk++; 274 break; 275 case 0x1E: /* INC Rr */ 276 intRAM[reg_pnt+6]++; 277 clk++; 278 break; 279 case 0x1F: /* INC Rr */ 280 intRAM[reg_pnt+7]++; 281 clk++; 282 break; 283 case 0x20: /* XCH A,@Ri */ 284 clk++; 285 dat=acc; 286 acc=intRAM[intRAM[reg_pnt] & 0x3F]; 287 intRAM[intRAM[reg_pnt] & 0x3F] = dat; 288 break; 289 case 0x21: /* XCH A,@Ri */ 290 clk++; 291 dat=acc; 292 acc=intRAM[intRAM[reg_pnt+1] & 0x3F]; 293 intRAM[intRAM[reg_pnt+1] & 0x3F] = dat; 294 break; 295 case 0x22: /* ILL */ 296 illegal(op); 297 break; 298 case 0x23: /* MOV a,#data */ 299 clk+=2; 300 acc = rom[pc++]; 301 break; 302 303 case 0x24: /* JMP */ 304 pc=rom[pc] | 0x100 | A11; 305 clk+=2; 306 break; 307 case 0x25: /* EN TCNTI */ 308 tirq_en=1; 309 clk++; 310 break; 311 case 0x26: /* JNT0 */ 312 clk+=2; 313 dat = rom[pc]; 314 //JMH if (!get_voice_status()) 315 // pc=(pc & 0xF00) | dat; 316 // else 317 pc++; 318 break; 319 case 0x27: /* CLR A */ 320 clk++; 321 acc=0; 322 break; 323 case 0x28: /* XCH A,Rr */ 324 dat=acc; 325 acc=intRAM[reg_pnt]; 326 intRAM[reg_pnt]=dat; 327 clk++; 328 break; 329 case 0x29: /* XCH A,Rr */ 330 dat=acc; 331 acc=intRAM[reg_pnt+1]; 332 intRAM[reg_pnt+1]=dat; 333 clk++; 334 break; 335 case 0x2A: /* XCH A,Rr */ 336 dat=acc; 337 acc=intRAM[reg_pnt+2]; 338 intRAM[reg_pnt+2]=dat; 339 clk++; 340 break; 341 case 0x2B: /* XCH A,Rr */ 342 dat=acc; 343 acc=intRAM[reg_pnt+3]; 344 intRAM[reg_pnt+3]=dat; 345 clk++; 346 break; 347 case 0x2C: /* XCH A,Rr */ 348 dat=acc; 349 acc=intRAM[reg_pnt+4]; 350 intRAM[reg_pnt+4]=dat; 351 clk++; 352 break; 353 case 0x2D: /* XCH A,Rr */ 354 dat=acc; 355 acc=intRAM[reg_pnt+5]; 356 intRAM[reg_pnt+5]=dat; 357 clk++; 358 break; 359 case 0x2E: /* XCH A,Rr */ 360 dat=acc; 361 acc=intRAM[reg_pnt+6]; 362 intRAM[reg_pnt+6]=dat; 363 clk++; 364 break; 365 case 0x2F: /* XCH A,Rr */ 366 dat=acc; 367 acc=intRAM[reg_pnt+7]; 368 intRAM[reg_pnt+7]=dat; 369 clk++; 370 break; 371 case 0x30: /* XCHD A,@Ri */ 372 clk++; 373 adr=intRAM[reg_pnt] & 0x3F; 374 dat=acc & 0x0F; 375 acc=acc & 0xF0; 376 acc=acc | (intRAM[adr] & 0x0F); 377 intRAM[adr] &= 0xF0; 378 intRAM[adr] |= dat; 379 break; 380 case 0x31: /* XCHD A,@Ri */ 381 clk++; 382 adr=intRAM[reg_pnt+1] & 0x3F; 383 dat=acc & 0x0F; 384 acc=acc & 0xF0; 385 acc=acc | (intRAM[adr] & 0x0F); 386 intRAM[adr] &= 0xF0; 387 intRAM[adr] |= dat; 388 break; 389 case 0x32: /* JBb address */ 390 clk+=2; 391 dat=rom[pc]; 392 if (acc & 0x02) 393 pc=(pc & 0xF00) | dat; 394 else 395 pc++; 396 break; 397 case 0x33: /* ILL */ 398 clk++; 399 illegal(op); 400 break; 401 case 0x34: /* CALL */ 402 make_psw(); 403 adr = rom[pc] | 0x100 | A11; 404 pc++; 405 clk+=2; 406 push(pc & 0xFF); 407 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 408 pc = adr; 409 break; 410 case 0x35: /* DIS TCNTI */ 411 tirq_en=0; 412 tirq_pend=0; 413 clk++; 414 break; 415 case 0x36: /* JT0 */ 416 clk+=2; 417 dat=rom[pc]; 418 // JMH if (get_voice_status()) 419 // pc=(pc & 0xF00) | dat; 420 // else 421 pc++; 422 break; 423 case 0x37: /* CPL A */ 424 acc = acc ^ 0xFF; 425 clk++; 426 break; 427 case 0x38: /* ILL */ 428 clk++; 429 illegal(op); 430 break; 431 case 0x39: /* OUTL P1,A */ 432 clk+=2; 433 write_p1(acc); 434 break; 435 case 0x3A: /* OUTL P2,A */ 436 clk+=2; 437 p2=acc; 438 break; 439 case 0x3B: /* ILL */ 440 clk++; 441 illegal(op); 442 break; 443 case 0x3C: /* MOVD P4,A */ 444 clk+=2; 445 //write_PB(0,acc); 446 break; 447 case 0x3D: /* MOVD P5,A */ 448 clk+=2; 449 //write_PB(1,acc); 450 break; 451 case 0x3E: /* MOVD P6,A */ 452 clk+=2; 453 //write_PB(2,acc); 454 break; 455 case 0x3F: /* MOVD P7,A */ 456 clk+=2; 457 //write_PB(3,acc); 458 break; 459 case 0x40: /* ORL A,@Ri */ 460 clk++; 461 acc = acc | intRAM[intRAM[reg_pnt] & 0x3F]; 462 break; 463 case 0x41: /* ORL A,@Ri */ 464 clk++; 465 acc = acc | intRAM[intRAM[reg_pnt+1] & 0x3F]; 466 break; 467 case 0x42: /* MOV A,T */ 468 clk++; 469 acc = itimer; 470 break; 471 case 0x43: /* ORL A,#data */ 472 clk+=2; 473 acc = acc | rom[pc++]; 474 break; 475 case 0x44: /* JMP */ 476 pc=rom[pc] | 0x200 | A11; 477 clk+=2; 478 break; 479 case 0x45: /* STRT CNT */ 480 /* printf("START: %d=%d\n",master_clk/22,itimer); */ 481 count_on=1; 482 clk++; 483 break; 484 case 0x46: /* JNT1 */ 485 clk+=2; 486 dat = rom[pc]; 487 if (!read_t1()) 488 pc=(pc & 0xF00) | dat; 489 else 490 pc++; 491 break; 492 case 0x47: /* SWAP A */ 493 clk++; 494 dat=(acc & 0xF0) >> 4; 495 acc = acc << 4; 496 acc = acc | dat; 497 break; 498 case 0x48: /* ORL A,Rr */ 499 clk++; 500 acc = acc | intRAM[reg_pnt]; 501 break; 502 case 0x49: /* ORL A,Rr */ 503 clk++; 504 acc = acc | intRAM[reg_pnt+1]; 505 break; 506 case 0x4A: /* ORL A,Rr */ 507 clk++; 508 acc = acc | intRAM[reg_pnt+2]; 509 break; 510 case 0x4B: /* ORL A,Rr */ 511 clk++; 512 acc = acc | intRAM[reg_pnt+3]; 513 break; 514 case 0x4C: /* ORL A,Rr */ 515 clk++; 516 acc = acc | intRAM[reg_pnt+4]; 517 break; 518 case 0x4D: /* ORL A,Rr */ 519 clk++; 520 acc = acc | intRAM[reg_pnt+5]; 521 break; 522 case 0x4E: /* ORL A,Rr */ 523 clk++; 524 acc = acc | intRAM[reg_pnt+6]; 525 break; 526 case 0x4F: /* ORL A,Rr */ 527 clk++; 528 acc = acc | intRAM[reg_pnt+7]; 529 break; 530 531 case 0x50: /* ANL A,@Ri */ 532 acc = acc & intRAM[intRAM[reg_pnt] & 0x3F]; 533 clk++; 534 break; 535 case 0x51: /* ANL A,@Ri */ 536 acc = acc & intRAM[intRAM[reg_pnt+1] & 0x3F]; 537 clk++; 538 break; 539 case 0x52: /* JBb address */ 540 clk+=2; 541 dat=rom[pc]; 542 if (acc & 0x04) 543 pc=(pc & 0xF00) | dat; 544 else 545 pc++; 546 break; 547 case 0x53: /* ANL A,#data */ 548 clk+=2; 549 acc = acc & rom[pc++]; 550 break; 551 case 0x54: /* CALL */ 552 make_psw(); 553 adr = rom[pc] | 0x200 | A11; 554 pc++; 555 clk+=2; 556 push(pc & 0xFF); 557 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 558 pc = adr; 559 break; 560 case 0x55: /* STRT T */ 561 timer_on=1; 562 clk++; 563 break; 564 case 0x56: /* JT1 */ 565 clk+=2; 566 dat = rom[pc]; 567 if (read_t1()) 568 pc=(pc & 0xF00) | dat; 569 else 570 pc++; 571 break; 572 case 0x57: /* DA A */ 573 clk++; 574 if (((acc & 0x0F) > 0x09) || ac) acc+=6; 575 dat = (acc & 0xF0) >> 4; 576 if ((dat > 9) || cy) { 577 dat+=6; 578 cy=1; 579 } 580 else { 581 cy=0; 582 } 583 /* if (dat > 0x0F) cy=1; */ 584 acc = (acc & 0x0F) | (dat << 4); 585 break; 586 case 0x58: /* ANL A,Rr */ 587 clk++; 588 acc = acc & intRAM[reg_pnt]; 589 break; 590 case 0x59: /* ANL A,Rr */ 591 clk++; 592 acc = acc & intRAM[reg_pnt+1]; 593 break; 594 case 0x5A: /* ANL A,Rr */ 595 clk++; 596 acc = acc & intRAM[reg_pnt+2]; 597 break; 598 case 0x5B: /* ANL A,Rr */ 599 clk++; 600 acc = acc & intRAM[reg_pnt+3]; 601 break; 602 case 0x5C: /* ANL A,Rr */ 603 clk++; 604 acc = acc & intRAM[reg_pnt+4]; 605 break; 606 case 0x5D: /* ANL A,Rr */ 607 clk++; 608 acc = acc & intRAM[reg_pnt+5]; 609 break; 610 case 0x5E: /* ANL A,Rr */ 611 clk++; 612 acc = acc & intRAM[reg_pnt+6]; 613 break; 614 case 0x5F: /* ANL A,Rr */ 615 clk++; 616 acc = acc & intRAM[reg_pnt+7]; 617 break; 618 619 case 0x60: /* ADD A,@Ri */ 620 clk++; 621 cy=ac=0; 622 dat=intRAM[intRAM[reg_pnt] & 0x3F]; 623 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 624 temp=acc+dat; 625 if (temp > 0xFF) cy=1; 626 acc=(temp & 0xFF); 627 break; 628 case 0x61: /* ADD A,@Ri */ 629 clk++; 630 cy=ac=0; 631 dat=intRAM[intRAM[reg_pnt+1] & 0x3F]; 632 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 633 temp=acc+dat; 634 if (temp > 0xFF) cy=1; 635 acc=(temp & 0xFF); 636 break; 637 case 0x62: /* MOV T,A */ 638 clk++; 639 itimer=acc; 640 break; 641 case 0x63: /* ILL */ 642 clk++; 643 illegal(op); 644 break; 645 case 0x64: /* JMP */ 646 pc=rom[pc] | 0x300 | A11; 647 clk+=2; 648 break; 649 case 0x65: /* STOP TCNT */ 650 clk++; 651 /* printf("STOP %d\n",master_clk/22); */ 652 count_on=timer_on=0; 653 break; 654 case 0x66: /* ILL */ 655 clk++; 656 illegal(op); 657 break; 658 case 0x67: /* RRC A */ 659 dat=cy; 660 cy=acc & 0x01; 661 acc = acc >> 1; 662 if (dat) 663 acc = acc | 0x80; 664 else 665 acc = acc & 0x7F; 666 clk++; 667 break; 668 case 0x68: /* ADD A,Rr */ 669 clk++; 670 cy=ac=0; 671 dat=intRAM[reg_pnt]; 672 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 673 temp=acc+dat; 674 if (temp > 0xFF) cy=1; 675 acc=(temp & 0xFF); 676 break; 677 case 0x69: /* ADD A,Rr */ 678 clk++; 679 cy=ac=0; 680 dat=intRAM[reg_pnt+1]; 681 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 682 temp=acc+dat; 683 if (temp > 0xFF) cy=1; 684 acc=(temp & 0xFF); 685 break; 686 case 0x6A: /* ADD A,Rr */ 687 clk++; 688 cy=ac=0; 689 dat=intRAM[reg_pnt+2]; 690 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 691 temp=acc+dat; 692 if (temp > 0xFF) cy=1; 693 acc=(temp & 0xFF); 694 break; 695 case 0x6B: /* ADD A,Rr */ 696 clk++; 697 cy=ac=0; 698 dat=intRAM[reg_pnt+3]; 699 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 700 temp=acc+dat; 701 if (temp > 0xFF) cy=1; 702 acc=(temp & 0xFF); 703 break; 704 case 0x6C: /* ADD A,Rr */ 705 clk++; 706 cy=ac=0; 707 dat=intRAM[reg_pnt+4]; 708 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 709 temp=acc+dat; 710 if (temp > 0xFF) cy=1; 711 acc=(temp & 0xFF); 712 break; 713 case 0x6D: /* ADD A,Rr */ 714 clk++; 715 cy=ac=0; 716 dat=intRAM[reg_pnt+5]; 717 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 718 temp=acc+dat; 719 if (temp > 0xFF) cy=1; 720 acc=(temp & 0xFF); 721 break; 722 case 0x6E: /* ADD A,Rr */ 723 clk++; 724 cy=ac=0; 725 dat=intRAM[reg_pnt+6]; 726 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 727 temp=acc+dat; 728 if (temp > 0xFF) cy=1; 729 acc=(temp & 0xFF); 730 break; 731 case 0x6F: /* ADD A,Rr */ 732 clk++; 733 cy=ac=0; 734 dat=intRAM[reg_pnt+7]; 735 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40; 736 temp=acc+dat; 737 if (temp > 0xFF) cy=1; 738 acc=(temp & 0xFF); 739 break; 740 case 0x70: /* ADDC A,@Ri */ 741 clk++; 742 ac=0; 743 dat=intRAM[intRAM[reg_pnt] & 0x3F]; 744 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40; 745 temp=acc+dat+cy; 746 cy=0; 747 if (temp > 0xFF) cy=1; 748 acc=(temp & 0xFF); 749 break; 750 case 0x71: /* ADDC A,@Ri */ 751 clk++; 752 ac=0; 753 dat=intRAM[intRAM[reg_pnt+1] & 0x3F]; 754 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40; 755 temp=acc+dat+cy; 756 cy=0; 757 if (temp > 0xFF) cy=1; 758 acc=(temp & 0xFF); 759 break; 760 761 case 0x72: /* JBb address */ 762 clk+=2; 763 dat=rom[pc]; 764 if (acc & 0x08) 765 pc=(pc & 0xF00) | dat; 766 else 767 pc++; 768 break; 769 case 0x73: /* ILL */ 770 clk++; 771 illegal(op); 772 break; 773 case 0x74: /* CALL */ 774 make_psw(); 775 adr = rom[pc] | 0x300 | A11; 776 pc++; 777 clk+=2; 778 push(pc & 0xFF); 779 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 780 pc = adr; 781 break; 782 case 0x75: /* EN CLK */ 783 clk++; 784 undef(op); 785 break; 786 case 0x76: /* JF1 address */ 787 clk+=2; 788 dat=rom[pc]; 789 if (f1) 790 pc=(pc & 0xF00) | dat; 791 else 792 pc++; 793 break; 794 case 0x77: /* RR A */ 795 clk++; 796 dat=acc & 0x01; 797 acc = acc >> 1; 798 if (dat) 799 acc = acc | 0x80; 800 else 801 acc = acc & 0x7f; 802 break; 803 804 case 0x78: /* ADDC A,Rr */ 805 clk++; 806 ac=0; 807 dat=intRAM[reg_pnt]; 808 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40; 809 temp=acc+dat+cy; 810 cy=0; 811 if (temp > 0xFF) cy=1; 812 acc=(temp & 0xFF); 813 break; 814 case 0x79: /* ADDC A,Rr */ 815 clk++; 816 ac=0; 817 dat=intRAM[reg_pnt+1]; 818 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40; 819 temp=acc+dat+cy; 820 cy=0; 821 if (temp > 0xFF) cy=1; 822 acc=(temp & 0xFF); 823 break; 824 case 0x7A: /* ADDC A,Rr */ 825 clk++; 826 ac=0; 827 dat=intRAM[reg_pnt+2]; 828 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40; 829 temp=acc+dat+cy; 830 cy=0; 831 if (temp > 0xFF) cy=1; 832 acc=(temp & 0xFF); 833 break; 834 case 0x7B: /* ADDC A,Rr */ 835 clk++; 836 ac=0; 837 dat=intRAM[reg_pnt+3]; 838 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40; 839 temp=acc+dat+cy; 840 cy=0; 841 if (temp > 0xFF) cy=1; 842 acc=(temp & 0xFF); 843 break; 844 case 0x7C: /* ADDC A,Rr */ 845 clk++; 846 ac=0; 847 dat=intRAM[reg_pnt+4]; 848 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40; 849 temp=acc+dat+cy; 850 cy=0; 851 if (temp > 0xFF) cy=1; 852 acc=(temp & 0xFF); 853 break; 854 case 0x7D: /* ADDC A,Rr */ 855 clk++; 856 ac=0; 857 dat=intRAM[reg_pnt+5]; 858 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40; 859 temp=acc+dat+cy; 860 cy=0; 861 if (temp > 0xFF) cy=1; 862 acc=(temp & 0xFF); 863 break; 864 case 0x7E: /* ADDC A,Rr */ 865 clk++; 866 ac=0; 867 dat=intRAM[reg_pnt+6]; 868 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40; 869 temp=acc+dat+cy; 870 cy=0; 871 if (temp > 0xFF) cy=1; 872 acc=(temp & 0xFF); 873 break; 874 case 0x7F: /* ADDC A,Rr */ 875 clk++; 876 ac=0; 877 dat=intRAM[reg_pnt+7]; 878 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40; 879 temp=acc+dat+cy; 880 cy=0; 881 if (temp > 0xFF) cy=1; 882 acc=(temp & 0xFF); 883 break; 884 885 case 0x80: /* MOVX A,@Ri */ 886 acc=ext_read(intRAM[reg_pnt]); 887 clk+=2; 888 break; 889 case 0x81: /* MOVX A,@Ri */ 890 acc=ext_read(intRAM[reg_pnt+1]); 891 clk+=2; 892 break; 893 case 0x82: /* ILL */ 894 clk++; 895 illegal(op); 896 break; 897 case 0x83: /* RET */ 898 pc = ((pull() & 0x0F) << 8); 899 pc = pc | pull(); 900 break; 901 902 case 0x84: /* JMP */ 903 pc=rom[pc] | 0x400 | A11; 904 clk+=2; 905 break; 906 case 0x85: /* CLR F0 */ 907 clk++; 908 f0=0; 909 break; 910 case 0x86: /* JNI address */ 911 clk+=2; 912 dat=rom[pc]; 913 if (int_clk > 0) 914 pc=(pc & 0xF00) | dat; 915 else 916 pc++; 917 break; 918 break; 919 case 0x87: /* ILL */ 920 illegal(op); 921 clk++; 922 break; 923 case 0x88: /* BUS,#data */ 924 clk+=2; 925 undef(op); 926 break; 927 case 0x89: /* ORL Pp,#data */ 928 write_p1(p1 | rom[pc++]); 929 clk+=2; 930 break; 931 case 0x8A: /* ORL Pp,#data */ 932 p2 = p2 | rom[pc++]; 933 clk+=2; 934 break; 935 case 0x8B: /* ILL */ 936 illegal(op); 937 clk++; 938 break; 939 case 0x8C: /* ORLD P4,A */ 940 //write_PB(0,read_PB(0)|acc); 941 clk+=2; 942 break; 943 case 0x8D: /* ORLD P5,A */ 944 //write_PB(1,read_PB(1)|acc); 945 clk+=2; 946 break; 947 case 0x8E: /* ORLD P6,A */ 948 //write_PB(2,read_PB(2)|acc); 949 clk+=2; 950 break; 951 case 0x8F: /* ORLD P7,A */ 952 //write_PB(3,read_PB(3)|acc); 953 clk+=2; 954 break; 955 case 0x90: /* MOVX @Ri,A */ 956 ext_write(acc,intRAM[reg_pnt]); 957 clk+=2; 958 break; 959 case 0x91: /* MOVX @Ri,A */ 960 ext_write(acc,intRAM[reg_pnt+1]); 961 clk+=2; 962 break; 963 case 0x92: /* JBb address */ 964 clk+=2; 965 dat=rom[pc]; 966 if (acc & 0x10) 967 pc=(pc & 0xF00) | dat; 968 else 969 pc++; 970 break; 971 case 0x93: /* RETR*/ 972 /* printf("RETR %d\n",master_clk/22); */ 973 clk+=2; 974 dat=pull(); 975 pc = (dat & 0x0F) << 8; 976 cy = (dat & 0x80) >> 7; 977 ac = dat & 0x40; 978 f0 = dat & 0x20; 979 bs = dat & 0x10; 980 if (bs) 981 reg_pnt=24; 982 else 983 reg_pnt=0; 984 pc = pc | pull(); 985 irq_ex=0; 986 A11=A11ff; 987 break; 988 case 0x94: /* CALL */ 989 make_psw(); 990 adr = rom[pc] | 0x400 | A11; 991 pc++; 992 clk+=2; 993 push(pc & 0xFF); 994 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 995 pc = adr; 996 break; 997 case 0x95: /* CPL F0 */ 998 f0 = f0 ^ 0x20; 999 clk++; 1000 break; 1001 case 0x96: /* JNZ address */ 1002 clk+=2; 1003 dat=rom[pc]; 1004 if (acc != 0) 1005 pc=(pc & 0xF00) | dat; 1006 else 1007 pc++; 1008 break; 1009 case 0x97: /* CLR C */ 1010 cy=0; 1011 clk++; 1012 break; 1013 case 0x98: /* ANL BUS,#data */ 1014 clk+=2; 1015 undef(op); 1016 break; 1017 case 0x99: /* ANL Pp,#data */ 1018 write_p1(p1 & rom[pc++]); 1019 clk+=2; 1020 break; 1021 case 0x9A: /* ANL Pp,#data */ 1022 p2 = p2 & rom[pc++]; 1023 clk+=2; 1024 break; 1025 case 0x9B: /* ILL */ 1026 illegal(op); 1027 clk++; 1028 break; 1029 case 0x9C: /* ANLD P4,A */ 1030 //write_PB(0,read_PB(0)&acc); 1031 clk+=2; 1032 break; 1033 case 0x9D: /* ANLD P5,A */ 1034 //write_PB(1,read_PB(1)&acc); 1035 clk+=2; 1036 break; 1037 case 0x9E: /* ANLD P6,A */ 1038 //write_PB(2,read_PB(2)&acc); 1039 clk+=2; 1040 break; 1041 case 0x9F: /* ANLD P7,A */ 1042 //write_PB(3,read_PB(3)&acc); 1043 clk+=2; 1044 break; 1045 case 0xA0: /* MOV @Ri,A */ 1046 intRAM[intRAM[reg_pnt] & 0x3F]=acc; 1047 clk++; 1048 break; 1049 case 0xA1: /* MOV @Ri,A */ 1050 intRAM[intRAM[reg_pnt+1] & 0x3F]=acc; 1051 clk++; 1052 break; 1053 case 0xA2: /* ILL */ 1054 clk++; 1055 illegal(op); 1056 break; 1057 case 0xA3: /* MOVP A,@A */ 1058 acc=rom[(pc & 0xF00) | acc]; 1059 clk+=2; 1060 break; 1061 case 0xA4: /* JMP */ 1062 pc=rom[pc] | 0x500 | A11; 1063 clk+=2; 1064 break; 1065 case 0xA5: /* CLR F1 */ 1066 clk++; 1067 f1=0; 1068 break; 1069 case 0xA6: /* ILL */ 1070 illegal(op); 1071 clk++; 1072 break; 1073 case 0xA7: /* CPL C */ 1074 cy = cy ^ 0x01; 1075 clk++; 1076 break; 1077 case 0xA8: /* MOV Rr,A */ 1078 intRAM[reg_pnt] = acc; 1079 break; 1080 case 0xA9: /* MOV Rr,A */ 1081 intRAM[reg_pnt+1] = acc; 1082 break; 1083 case 0xAA: /* MOV Rr,A */ 1084 intRAM[reg_pnt+2] = acc; 1085 break; 1086 case 0xAB: /* MOV Rr,A */ 1087 intRAM[reg_pnt+3] = acc; 1088 break; 1089 case 0xAC: /* MOV Rr,A */ 1090 intRAM[reg_pnt+4] = acc; 1091 break; 1092 case 0xAD: /* MOV Rr,A */ 1093 intRAM[reg_pnt+5] = acc; 1094 break; 1095 case 0xAE: /* MOV Rr,A */ 1096 intRAM[reg_pnt+6] = acc; 1097 break; 1098 case 0xAF: /* MOV Rr,A */ 1099 intRAM[reg_pnt+7] = acc; 1100 break; 1101 case 0xB0: /* MOV @Ri,#data */ 1102 intRAM[intRAM[reg_pnt] & 0x3F]=rom[pc++]; 1103 clk+=2; 1104 break; 1105 case 0xB1: /* MOV @Ri,#data */ 1106 intRAM[intRAM[reg_pnt+1] & 0x3F]=rom[pc++]; 1107 clk+=2; 1108 break; 1109 case 0xB2: /* JBb address */ 1110 clk+=2; 1111 dat=rom[pc]; 1112 if (acc & 0x20) 1113 pc=(pc & 0xF00) | dat; 1114 else 1115 pc++; 1116 break; 1117 case 0xB3: /* JMPP @A */ 1118 adr = (pc & 0xF00) | acc; 1119 pc=(pc & 0xF00) | rom[adr]; 1120 clk+=2; 1121 break; 1122 case 0xB4: /* CALL */ 1123 make_psw(); 1124 adr = rom[pc] | 0x500 | A11; 1125 pc++; 1126 clk+=2; 1127 push(pc & 0xFF); 1128 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 1129 pc = adr; 1130 break; 1131 case 0xB5: /* CPL F1 */ 1132 f1 = f1 ^ 0x01; 1133 clk++; 1134 break; 1135 case 0xB6: /* JF0 address */ 1136 clk+=2; 1137 dat=rom[pc]; 1138 if (f0) 1139 pc=(pc & 0xF00) | dat; 1140 else 1141 pc++; 1142 break; 1143 case 0xB7: /* ILL */ 1144 clk++; 1145 illegal(op); 1146 break; 1147 case 0xB8: /* MOV Rr,#data */ 1148 intRAM[reg_pnt]=rom[pc++]; 1149 clk+=2; 1150 break; 1151 case 0xB9: /* MOV Rr,#data */ 1152 intRAM[reg_pnt+1]=rom[pc++]; 1153 clk+=2; 1154 break; 1155 case 0xBA: /* MOV Rr,#data */ 1156 intRAM[reg_pnt+2]=rom[pc++]; 1157 clk+=2; 1158 break; 1159 case 0xBB: /* MOV Rr,#data */ 1160 intRAM[reg_pnt+3]=rom[pc++]; 1161 clk+=2; 1162 break; 1163 case 0xBC: /* MOV Rr,#data */ 1164 intRAM[reg_pnt+4]=rom[pc++]; 1165 clk+=2; 1166 break; 1167 case 0xBD: /* MOV Rr,#data */ 1168 intRAM[reg_pnt+5]=rom[pc++]; 1169 clk+=2; 1170 break; 1171 case 0xBE: /* MOV Rr,#data */ 1172 intRAM[reg_pnt+6]=rom[pc++]; 1173 clk+=2; 1174 break; 1175 case 0xBF: /* MOV Rr,#data */ 1176 intRAM[reg_pnt+7]=rom[pc++]; 1177 clk+=2; 1178 break; 1179 case 0xC0: /* ILL */ 1180 illegal(op); 1181 clk++; 1182 break; 1183 case 0xC1: /* ILL */ 1184 illegal(op); 1185 clk++; 1186 break; 1187 case 0xC2: /* ILL */ 1188 illegal(op); 1189 clk++; 1190 break; 1191 case 0xC3: /* ILL */ 1192 illegal(op); 1193 clk++; 1194 break; 1195 case 0xC4: /* JMP */ 1196 pc=rom[pc] | 0x600 | A11; 1197 clk+=2; 1198 break; 1199 case 0xC5: /* SEL RB0 */ 1200 bs=reg_pnt=0; 1201 clk++; 1202 break; 1203 case 0xC6: /* JZ address */ 1204 clk+=2; 1205 dat=rom[pc]; 1206 if (acc == 0) 1207 pc=(pc & 0xF00) | dat; 1208 else 1209 pc++; 1210 break; 1211 case 0xC7: /* MOV A,PSW */ 1212 clk++; 1213 make_psw(); 1214 acc=psw; 1215 break; 1216 case 0xC8: /* DEC Rr */ 1217 intRAM[reg_pnt]--; 1218 clk++; 1219 break; 1220 case 0xC9: /* DEC Rr */ 1221 intRAM[reg_pnt+1]--; 1222 clk++; 1223 break; 1224 case 0xCA: /* DEC Rr */ 1225 intRAM[reg_pnt+2]--; 1226 clk++; 1227 break; 1228 case 0xCB: /* DEC Rr */ 1229 intRAM[reg_pnt+3]--; 1230 clk++; 1231 break; 1232 case 0xCC: /* DEC Rr */ 1233 intRAM[reg_pnt+4]--; 1234 clk++; 1235 break; 1236 case 0xCD: /* DEC Rr */ 1237 intRAM[reg_pnt+5]--; 1238 clk++; 1239 break; 1240 case 0xCE: /* DEC Rr */ 1241 intRAM[reg_pnt+6]--; 1242 clk++; 1243 break; 1244 case 0xCF: /* DEC Rr */ 1245 intRAM[reg_pnt+7]--; 1246 clk++; 1247 break; 1248 case 0xD0: /* XRL A,@Ri */ 1249 acc = acc ^ intRAM[intRAM[reg_pnt] & 0x3F]; 1250 clk++; 1251 break; 1252 case 0xD1: /* XRL A,@Ri */ 1253 acc = acc ^ intRAM[intRAM[reg_pnt+1] & 0x3F]; 1254 clk++; 1255 break; 1256 case 0xD2: /* JBb address */ 1257 clk+=2; 1258 dat = rom[pc]; 1259 if (acc & 0x40) 1260 pc=(pc & 0xF00) | dat; 1261 else 1262 pc++; 1263 break; 1264 case 0xD3: /* XRL A,#data */ 1265 clk+=2; 1266 acc = acc ^ rom[pc++]; 1267 break; 1268 case 0xD4: /* CALL */ 1269 make_psw(); 1270 adr = rom[pc] | 0x600 | A11; 1271 pc++; 1272 clk+=2; 1273 push(pc & 0xFF); 1274 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 1275 pc = adr; 1276 break; 1277 case 0xD5: /* SEL RB1 */ 1278 bs=0x10; 1279 reg_pnt=24; 1280 clk++; 1281 break; 1282 case 0xD6: /* ILL */ 1283 illegal(op); 1284 clk++; 1285 break; 1286 case 0xD7: /* MOV PSW,A */ 1287 psw=acc; 1288 clk++; 1289 cy = (psw & 0x80) >> 7; 1290 ac = psw & 0x40; 1291 f0 = psw & 0x20; 1292 bs = psw & 0x10; 1293 if (bs) 1294 reg_pnt = 24; 1295 else 1296 reg_pnt = 0; 1297 sp = (psw & 0x07) << 1; 1298 sp+=8; 1299 break; 1300 case 0xD8: /* XRL A,Rr */ 1301 acc = acc ^ intRAM[reg_pnt]; 1302 clk++; 1303 break; 1304 case 0xD9: /* XRL A,Rr */ 1305 acc = acc ^ intRAM[reg_pnt+1]; 1306 clk++; 1307 break; 1308 case 0xDA: /* XRL A,Rr */ 1309 acc = acc ^ intRAM[reg_pnt+2]; 1310 clk++; 1311 break; 1312 case 0xDB: /* XRL A,Rr */ 1313 acc = acc ^ intRAM[reg_pnt+3]; 1314 clk++; 1315 break; 1316 case 0xDC: /* XRL A,Rr */ 1317 acc = acc ^ intRAM[reg_pnt+4]; 1318 clk++; 1319 break; 1320 case 0xDD: /* XRL A,Rr */ 1321 acc = acc ^ intRAM[reg_pnt+5]; 1322 clk++; 1323 break; 1324 case 0xDE: /* XRL A,Rr */ 1325 acc = acc ^ intRAM[reg_pnt+6]; 1326 clk++; 1327 break; 1328 case 0xDF: /* XRL A,Rr */ 1329 acc = acc ^ intRAM[reg_pnt+7]; 1330 clk++; 1331 break; 1332 case 0xE0: /* ILL */ 1333 clk++; 1334 illegal(op); 1335 break; 1336 case 0xE1: /* ILL */ 1337 clk++; 1338 illegal(op); 1339 break; 1340 case 0xE2: /* ILL */ 1341 clk++; 1342 illegal(op); 1343 break; 1344 case 0xE3: /* MOVP3 A,@A */ 1345 1346 adr = 0x300 | acc; 1347 acc=rom[adr]; 1348 clk+=2; 1349 break; 1350 case 0xE4: /* JMP */ 1351 pc=rom[pc] | 0x700 | A11; 1352 clk+=2; 1353 break; 1354 case 0xE5: /* SEL MB0 */ 1355 A11=0; 1356 A11ff = 0; 1357 clk++; 1358 break; 1359 case 0xE6: /* JNC address */ 1360 clk+=2; 1361 dat=rom[pc]; 1362 if (!cy) 1363 pc=(pc & 0xF00) | dat; 1364 else 1365 pc++; 1366 break; 1367 case 0xE7: /* RL A */ 1368 clk++; 1369 dat=acc & 0x80; 1370 acc = acc << 1; 1371 if (dat) 1372 acc = acc | 0x01; 1373 else 1374 acc = acc & 0xFE; 1375 break; 1376 case 0xE8: /* DJNZ Rr,address */ 1377 clk+=2; 1378 intRAM[reg_pnt]--; 1379 dat=rom[pc]; 1380 if (intRAM[reg_pnt] != 0) { 1381 pc = pc & 0xF00; 1382 pc = pc | dat; 1383 } else pc++; 1384 break; 1385 case 0xE9: /* DJNZ Rr,address */ 1386 clk+=2; 1387 intRAM[reg_pnt+1]--; 1388 dat=rom[pc]; 1389 if (intRAM[reg_pnt+1] != 0) { 1390 pc = pc & 0xF00; 1391 pc = pc | dat; 1392 } else pc++; 1393 break; 1394 case 0xEA: /* DJNZ Rr,address */ 1395 clk+=2; 1396 intRAM[reg_pnt+2]--; 1397 dat=rom[pc]; 1398 if (intRAM[reg_pnt+2] != 0) { 1399 pc = pc & 0xF00; 1400 pc = pc | dat; 1401 } else pc++; 1402 break; 1403 case 0xEB: /* DJNZ Rr,address */ 1404 clk+=2; 1405 intRAM[reg_pnt+3]--; 1406 dat=rom[pc]; 1407 if (intRAM[reg_pnt+3] != 0) { 1408 pc = pc & 0xF00; 1409 pc = pc | dat; 1410 } else pc++; 1411 break; 1412 case 0xEC: /* DJNZ Rr,address */ 1413 clk+=2; 1414 intRAM[reg_pnt+4]--; 1415 dat=rom[pc]; 1416 if (intRAM[reg_pnt+4] != 0) { 1417 pc = pc & 0xF00; 1418 pc = pc | dat; 1419 } else pc++; 1420 break; 1421 case 0xED: /* DJNZ Rr,address */ 1422 clk+=2; 1423 intRAM[reg_pnt+5]--; 1424 dat=rom[pc]; 1425 if (intRAM[reg_pnt+5] != 0) { 1426 pc = pc & 0xF00; 1427 pc = pc | dat; 1428 } else pc++; 1429 break; 1430 case 0xEE: /* DJNZ Rr,address */ 1431 clk+=2; 1432 intRAM[reg_pnt+6]--; 1433 dat=rom[pc]; 1434 if (intRAM[reg_pnt+6] != 0) { 1435 pc = pc & 0xF00; 1436 pc = pc | dat; 1437 } else pc++; 1438 break; 1439 case 0xEF: /* DJNZ Rr,address */ 1440 clk+=2; 1441 intRAM[reg_pnt+7]--; 1442 dat=rom[pc]; 1443 if (intRAM[reg_pnt+7] != 0) { 1444 pc = pc & 0xF00; 1445 pc = pc | dat; 1446 } else pc++; 1447 break; 1448 case 0xF0: /* MOV A,@Ri */ 1449 clk++; 1450 acc=intRAM[intRAM[reg_pnt] & 0x3F]; 1451 break; 1452 case 0xF1: /* MOV A,@Ri */ 1453 clk++; 1454 acc=intRAM[intRAM[reg_pnt + 1] & 0x3F]; 1455 break; 1456 case 0xF2: /* JBb address */ 1457 clk+=2; 1458 dat=rom[pc]; 1459 if (acc & 0x80) 1460 pc=(pc & 0xF00) | dat; 1461 else 1462 pc++; 1463 break; 1464 case 0xF3: /* ILL */ 1465 illegal(op); 1466 clk++; 1467 break; 1468 case 0xF4: /* CALL */ 1469 clk+=2; 1470 make_psw(); 1471 adr = rom[pc] | 0x700 | A11; 1472 pc++; 1473 push(pc & 0xFF); 1474 push(((pc & 0xF00) >> 8) | (psw & 0xF0)); 1475 pc = adr; 1476 break; 1477 case 0xF5: /* SEL MB1 */ 1478 if (irq_ex) { 1479 A11ff = 0x800; 1480 } 1481 else 1482 { 1483 A11=0x800; 1484 A11ff = 0x800; 1485 } 1486 clk++; 1487 break; 1488 case 0xF6: /* JC address */ 1489 clk+=2; 1490 dat=rom[pc]; 1491 if (cy) 1492 pc=(pc & 0xF00) | dat; 1493 else 1494 pc++; 1495 break; 1496 case 0xF7: /* RLC A */ 1497 dat=cy; 1498 cy=(acc & 0x80) >> 7; 1499 acc = acc << 1; 1500 if (dat) 1501 acc = acc | 0x01; 1502 else 1503 acc = acc & 0xFE; 1504 clk++; 1505 break; 1506 case 0xF8: /* MOV A,Rr */ 1507 clk++; 1508 acc = intRAM[reg_pnt]; 1509 break; 1510 case 0xF9: /* MOV A,Rr */ 1511 clk++; 1512 acc = intRAM[reg_pnt + 1]; 1513 break; 1514 case 0xFA: /* MOV A,Rr */ 1515 clk++; 1516 acc = intRAM[reg_pnt + 2]; 1517 break; 1518 case 0xFB: /* MOV A,Rr */ 1519 clk++; 1520 acc = intRAM[reg_pnt + 3]; 1521 break; 1522 case 0xFC: /* MOV A,Rr */ 1523 clk++; 1524 acc = intRAM[reg_pnt + 4]; 1525 break; 1526 case 0xFD: /* MOV A,Rr */ 1527 clk++; 1528 acc = intRAM[reg_pnt + 5]; 1529 break; 1530 case 0xFE: /* MOV A,Rr */ 1531 clk++; 1532 acc = intRAM[reg_pnt + 6]; 1533 break; 1534 case 0xFF: /* MOV A,Rr */ 1535 clk++; 1536 acc = intRAM[reg_pnt + 7]; 1537 break; 1538 } 1539 1540 1541 master_clk+=clk; 1542 h_clk+=clk; 1543 clk_counter+=clk; 1544 1545 /* flag for JNI */ 1546 if (int_clk > clk) 1547 int_clk -= clk; 1548 else 1549 int_clk = 0; 1550 1551 /* pending IRQs */ 1552 if (xirq_pend) ext_IRQ(); 1553 if (tirq_pend) tim_IRQ(); 1554 1555 if (h_clk > LINECNT-1) { 1556 h_clk-=LINECNT; 1557 if (enahirq && (VDCwrite[0xA0] & 0x01)) ext_IRQ(); 1558 if (count_on && mstate == 0) { 1559 itimer++; 1560 if (itimer == 0) { 1561 t_flag=1; 1562 tim_IRQ(); 1563 if (!ccolflag) { 1564 clear_collision(); 1565 ccolflag=1; 1566 } 1567 draw_region(); 1568 } 1569 } 1570 } 1571 1572 if (timer_on) { 1573 master_count+=clk; 1574 if (master_count > 31) { 1575 master_count-=31; 1576 itimer++; 1577 if (itimer == 0) { 1578 t_flag=1; 1579 tim_IRQ(); 1580 } 1581 } 1582 } 1583 1584 if ((mstate==0) && (master_clk > VBLCLK)) 1585 handle_vbl(); 1586 1587 if ((mstate==1) && (master_clk > evblclk)) { 1588 handle_evbl(); 1589 break; 1590 } 1591 1592 if (app_data.debug) break; 1593 } 1594 1595 } 1596