1  /*****************************************************************************\
   2       Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
   3                  This file is licensed under the Snes9x License.
   4     For further information, consult the LICENSE file in the root directory.
   5  \*****************************************************************************/
   6  
   7  #include "snes9x.h"
   8  #include "memory.h"
   9  #include "apu.h"
  10  #ifdef DEBUGGER
  11  #include "debug.h"
  12  #endif
  13  
  14  #if RETRO_LESS_ACCURATE_CPU
  15  #define AddCycles(n)	{ CPU.Cycles += (n); }
  16  #else
  17  #define AddCycles(n)	{ CPU.Cycles += (n); while (CPU.Cycles >= CPU.NextEvent) S9xDoHEventProcessing(); }
  18  #endif
  19  
  20  #include "cpuaddr.h"
  21  #include "cpumacro.h"
  22  
  23  /* ADC ********************************************************************* */
  24  
  25  static void Op69M1 (void)
  26  {
  27  	ADC8(Immediate8(READ));
  28  }
  29  
  30  static void Op69M0 (void)
  31  {
  32  	ADC16(Immediate16(READ));
  33  }
  34  
  35  static void Op69Slow (void)
  36  {
  37  	if (CheckMemory())
  38  		ADC8(Immediate8Slow(READ));
  39  	else
  40  		ADC16(Immediate16Slow(READ));
  41  }
  42  
  43  rOP8 (65M1,     Direct,                           WRAP_BANK, ADC)
  44  rOP16(65M0,     Direct,                           WRAP_BANK, ADC)
  45  rOPM (65Slow,   DirectSlow,                       WRAP_BANK, ADC)
  46  
  47  rOP8 (75E0M1,   DirectIndexedXE0,                 WRAP_BANK, ADC)
  48  rOP16(75E0M0,   DirectIndexedXE0,                 WRAP_BANK, ADC)
  49  rOPM (75Slow,   DirectIndexedXSlow,               WRAP_BANK, ADC)
  50  
  51  rOP8 (72E0M1,   DirectIndirectE0,                 WRAP_NONE, ADC)
  52  rOP16(72E0M0,   DirectIndirectE0,                 WRAP_NONE, ADC)
  53  rOPM (72Slow,   DirectIndirectSlow,               WRAP_NONE, ADC)
  54  
  55  rOP8 (61E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, ADC)
  56  rOP16(61E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, ADC)
  57  rOPM (61Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, ADC)
  58  
  59  rOP8 (71E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ADC)
  60  rOP16(71E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ADC)
  61  rOP8 (71E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ADC)
  62  rOP16(71E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ADC)
  63  rOPM (71Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, ADC)
  64  
  65  rOP8 (67M1,     DirectIndirectLong,               WRAP_NONE, ADC)
  66  rOP16(67M0,     DirectIndirectLong,               WRAP_NONE, ADC)
  67  rOPM (67Slow,   DirectIndirectLongSlow,           WRAP_NONE, ADC)
  68  
  69  rOP8 (77M1,     DirectIndirectIndexedLong,        WRAP_NONE, ADC)
  70  rOP16(77M0,     DirectIndirectIndexedLong,        WRAP_NONE, ADC)
  71  rOPM (77Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, ADC)
  72  
  73  rOP8 (6DM1,     Absolute,                         WRAP_NONE, ADC)
  74  rOP16(6DM0,     Absolute,                         WRAP_NONE, ADC)
  75  rOPM (6DSlow,   AbsoluteSlow,                     WRAP_NONE, ADC)
  76  
  77  rOP8 (7DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ADC)
  78  rOP16(7DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ADC)
  79  rOP8 (7DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ADC)
  80  rOP16(7DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ADC)
  81  rOPM (7DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ADC)
  82  
  83  rOP8 (79M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, ADC)
  84  rOP16(79M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, ADC)
  85  rOP8 (79M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, ADC)
  86  rOP16(79M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, ADC)
  87  rOPM (79Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, ADC)
  88  
  89  rOP8 (6FM1,     AbsoluteLong,                     WRAP_NONE, ADC)
  90  rOP16(6FM0,     AbsoluteLong,                     WRAP_NONE, ADC)
  91  rOPM (6FSlow,   AbsoluteLongSlow,                 WRAP_NONE, ADC)
  92  
  93  rOP8 (7FM1,     AbsoluteLongIndexedX,             WRAP_NONE, ADC)
  94  rOP16(7FM0,     AbsoluteLongIndexedX,             WRAP_NONE, ADC)
  95  rOPM (7FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, ADC)
  96  
  97  rOP8 (63M1,     StackRelative,                    WRAP_NONE, ADC)
  98  rOP16(63M0,     StackRelative,                    WRAP_NONE, ADC)
  99  rOPM (63Slow,   StackRelativeSlow,                WRAP_NONE, ADC)
 100  
 101  rOP8 (73M1,     StackRelativeIndirectIndexed,     WRAP_NONE, ADC)
 102  rOP16(73M0,     StackRelativeIndirectIndexed,     WRAP_NONE, ADC)
 103  rOPM (73Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, ADC)
 104  
 105  /* AND ********************************************************************* */
 106  
 107  static void Op29M1 (void)
 108  {
 109  	Registers.AL &= Immediate8(READ);
 110  	SetZN8(Registers.AL);
 111  }
 112  
 113  static void Op29M0 (void)
 114  {
 115  	Registers.A.W &= Immediate16(READ);
 116  	SetZN16(Registers.A.W);
 117  }
 118  
 119  static void Op29Slow (void)
 120  {
 121  	if (CheckMemory())
 122  	{
 123  		Registers.AL &= Immediate8Slow(READ);
 124  		SetZN8(Registers.AL);
 125  	}
 126  	else
 127  	{
 128  		Registers.A.W &= Immediate16Slow(READ);
 129  		SetZN16(Registers.A.W);
 130  	}
 131  }
 132  
 133  rOP8 (25M1,     Direct,                           WRAP_BANK, AND)
 134  rOP16(25M0,     Direct,                           WRAP_BANK, AND)
 135  rOPM (25Slow,   DirectSlow,                       WRAP_BANK, AND)
 136  
 137  rOP8 (35E0M1,   DirectIndexedXE0,                 WRAP_BANK, AND)
 138  rOP16(35E0M0,   DirectIndexedXE0,                 WRAP_BANK, AND)
 139  rOPM (35Slow,   DirectIndexedXSlow,               WRAP_BANK, AND)
 140  
 141  rOP8 (32E0M1,   DirectIndirectE0,                 WRAP_NONE, AND)
 142  rOP16(32E0M0,   DirectIndirectE0,                 WRAP_NONE, AND)
 143  rOPM (32Slow,   DirectIndirectSlow,               WRAP_NONE, AND)
 144  
 145  rOP8 (21E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, AND)
 146  rOP16(21E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, AND)
 147  rOPM (21Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, AND)
 148  
 149  rOP8 (31E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, AND)
 150  rOP16(31E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, AND)
 151  rOP8 (31E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, AND)
 152  rOP16(31E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, AND)
 153  rOPM (31Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, AND)
 154  
 155  rOP8 (27M1,     DirectIndirectLong,               WRAP_NONE, AND)
 156  rOP16(27M0,     DirectIndirectLong,               WRAP_NONE, AND)
 157  rOPM (27Slow,   DirectIndirectLongSlow,           WRAP_NONE, AND)
 158  
 159  rOP8 (37M1,     DirectIndirectIndexedLong,        WRAP_NONE, AND)
 160  rOP16(37M0,     DirectIndirectIndexedLong,        WRAP_NONE, AND)
 161  rOPM (37Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, AND)
 162  
 163  rOP8 (2DM1,     Absolute,                         WRAP_NONE, AND)
 164  rOP16(2DM0,     Absolute,                         WRAP_NONE, AND)
 165  rOPM (2DSlow,   AbsoluteSlow,                     WRAP_NONE, AND)
 166  
 167  rOP8 (3DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, AND)
 168  rOP16(3DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, AND)
 169  rOP8 (3DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, AND)
 170  rOP16(3DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, AND)
 171  rOPM (3DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, AND)
 172  
 173  rOP8 (39M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, AND)
 174  rOP16(39M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, AND)
 175  rOP8 (39M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, AND)
 176  rOP16(39M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, AND)
 177  rOPM (39Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, AND)
 178  
 179  rOP8 (2FM1,     AbsoluteLong,                     WRAP_NONE, AND)
 180  rOP16(2FM0,     AbsoluteLong,                     WRAP_NONE, AND)
 181  rOPM (2FSlow,   AbsoluteLongSlow,                 WRAP_NONE, AND)
 182  
 183  rOP8 (3FM1,     AbsoluteLongIndexedX,             WRAP_NONE, AND)
 184  rOP16(3FM0,     AbsoluteLongIndexedX,             WRAP_NONE, AND)
 185  rOPM (3FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, AND)
 186  
 187  rOP8 (23M1,     StackRelative,                    WRAP_NONE, AND)
 188  rOP16(23M0,     StackRelative,                    WRAP_NONE, AND)
 189  rOPM (23Slow,   StackRelativeSlow,                WRAP_NONE, AND)
 190  
 191  rOP8 (33M1,     StackRelativeIndirectIndexed,     WRAP_NONE, AND)
 192  rOP16(33M0,     StackRelativeIndirectIndexed,     WRAP_NONE, AND)
 193  rOPM (33Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, AND)
 194  
 195  /* ASL ********************************************************************* */
 196  
 197  static void Op0AM1 (void)
 198  {
 199  	AddCycles(ONE_CYCLE);
 200  	ClearFlags(Carry);
 201  	SetFlags(Registers.AL >> 7);
 202  	Registers.AL <<= 1;
 203  	SetZN8(Registers.AL);
 204  }
 205  
 206  static void Op0AM0 (void)
 207  {
 208  	AddCycles(ONE_CYCLE);
 209  	ClearFlags(Carry);
 210  	SetFlags(Registers.AH >> 7);
 211  	Registers.A.W <<= 1;
 212  	SetZN16(Registers.A.W);
 213  }
 214  
 215  static void Op0ASlow (void)
 216  {
 217  	AddCycles(ONE_CYCLE);
 218  	ClearFlags(Carry);
 219  
 220  	if (CheckMemory())
 221  	{
 222  		SetFlags(Registers.AL >> 7);
 223  		Registers.AL <<= 1;
 224  		SetZN8(Registers.AL);
 225  	}
 226  	else
 227  	{
 228  		SetFlags(Registers.AH >> 7);
 229  		Registers.A.W <<= 1;
 230  		SetZN16(Registers.A.W);
 231  	}
 232  }
 233  
 234  mOP8 (06M1,     Direct,                           WRAP_BANK, ASL)
 235  mOP16(06M0,     Direct,                           WRAP_BANK, ASL)
 236  mOPM (06Slow,   DirectSlow,                       WRAP_BANK, ASL)
 237  
 238  mOP8 (16E0M1,   DirectIndexedXE0,                 WRAP_BANK, ASL)
 239  mOP16(16E0M0,   DirectIndexedXE0,                 WRAP_BANK, ASL)
 240  mOPM (16Slow,   DirectIndexedXSlow,               WRAP_BANK, ASL)
 241  
 242  mOP8 (0EM1,     Absolute,                         WRAP_NONE, ASL)
 243  mOP16(0EM0,     Absolute,                         WRAP_NONE, ASL)
 244  mOPM (0ESlow,   AbsoluteSlow,                     WRAP_NONE, ASL)
 245  
 246  mOP8 (1EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ASL)
 247  mOP16(1EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ASL)
 248  mOP8 (1EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ASL)
 249  mOP16(1EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ASL)
 250  mOPM (1ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ASL)
 251  
 252  /* BIT ********************************************************************* */
 253  
 254  static void Op89M1 (void)
 255  {
 256  	SetZeroX((Registers.AL & Immediate8(READ)) == 0);
 257  }
 258  
 259  static void Op89M0 (void)
 260  {
 261  	SetZeroX((Registers.A.W & Immediate16(READ)) == 0);
 262  }
 263  
 264  static void Op89Slow (void)
 265  {
 266  	if (CheckMemory())
 267  	{
 268  		SetZeroX((Registers.AL & Immediate8Slow(READ)) == 0);
 269  	}
 270  	else
 271  	{
 272  		SetZeroX((Registers.A.W & Immediate16Slow(READ)) == 0);
 273  	}
 274  }
 275  
 276  rOP8 (24M1,     Direct,                           WRAP_BANK, BIT)
 277  rOP16(24M0,     Direct,                           WRAP_BANK, BIT)
 278  rOPM (24Slow,   DirectSlow,                       WRAP_BANK, BIT)
 279  
 280  rOP8 (34E0M1,   DirectIndexedXE0,                 WRAP_BANK, BIT)
 281  rOP16(34E0M0,   DirectIndexedXE0,                 WRAP_BANK, BIT)
 282  rOPM (34Slow,   DirectIndexedXSlow,               WRAP_BANK, BIT)
 283  
 284  rOP8 (2CM1,     Absolute,                         WRAP_NONE, BIT)
 285  rOP16(2CM0,     Absolute,                         WRAP_NONE, BIT)
 286  rOPM (2CSlow,   AbsoluteSlow,                     WRAP_NONE, BIT)
 287  
 288  rOP8 (3CM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, BIT)
 289  rOP16(3CM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, BIT)
 290  rOP8 (3CM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, BIT)
 291  rOP16(3CM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, BIT)
 292  rOPM (3CSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, BIT)
 293  
 294  /* CMP ********************************************************************* */
 295  
 296  static void OpC9M1 (void)
 297  {
 298  	int16	Int16 = (int16) Registers.AL - (int16) Immediate8(READ);
 299  	SetCarryX(Int16 >= 0);
 300  	SetZN8(Int16);
 301  }
 302  
 303  static void OpC9M0 (void)
 304  {
 305  	int32	Int32 = (int32) Registers.A.W - (int32) Immediate16(READ);
 306  	SetCarryX(Int32 >= 0);
 307  	SetZN16((uint16) Int32);
 308  }
 309  
 310  static void OpC9Slow (void)
 311  {
 312  	if (CheckMemory())
 313  	{
 314  		int16	Int16 = (int16) Registers.AL - (int16) Immediate8Slow(READ);
 315  		SetCarryX(Int16 >= 0);
 316  		SetZN8(Int16);
 317  	}
 318  	else
 319  	{
 320  		int32	Int32 = (int32) Registers.A.W - (int32) Immediate16Slow(READ);
 321  		SetCarryX(Int32 >= 0);
 322  		SetZN16((uint16) Int32);
 323  	}
 324  }
 325  
 326  rOP8 (C5M1,     Direct,                           WRAP_BANK, CMP)
 327  rOP16(C5M0,     Direct,                           WRAP_BANK, CMP)
 328  rOPM (C5Slow,   DirectSlow,                       WRAP_BANK, CMP)
 329  
 330  rOP8 (D5E0M1,   DirectIndexedXE0,                 WRAP_BANK, CMP)
 331  rOP16(D5E0M0,   DirectIndexedXE0,                 WRAP_BANK, CMP)
 332  rOPM (D5Slow,   DirectIndexedXSlow,               WRAP_BANK, CMP)
 333  
 334  rOP8 (D2E0M1,   DirectIndirectE0,                 WRAP_NONE, CMP)
 335  rOP16(D2E0M0,   DirectIndirectE0,                 WRAP_NONE, CMP)
 336  rOPM (D2Slow,   DirectIndirectSlow,               WRAP_NONE, CMP)
 337  
 338  rOP8 (C1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, CMP)
 339  rOP16(C1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, CMP)
 340  rOPM (C1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, CMP)
 341  
 342  rOP8 (D1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, CMP)
 343  rOP16(D1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, CMP)
 344  rOP8 (D1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, CMP)
 345  rOP16(D1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, CMP)
 346  rOPM (D1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, CMP)
 347  
 348  rOP8 (C7M1,     DirectIndirectLong,               WRAP_NONE, CMP)
 349  rOP16(C7M0,     DirectIndirectLong,               WRAP_NONE, CMP)
 350  rOPM (C7Slow,   DirectIndirectLongSlow,           WRAP_NONE, CMP)
 351  
 352  rOP8 (D7M1,     DirectIndirectIndexedLong,        WRAP_NONE, CMP)
 353  rOP16(D7M0,     DirectIndirectIndexedLong,        WRAP_NONE, CMP)
 354  rOPM (D7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, CMP)
 355  
 356  rOP8 (CDM1,     Absolute,                         WRAP_NONE, CMP)
 357  rOP16(CDM0,     Absolute,                         WRAP_NONE, CMP)
 358  rOPM (CDSlow,   AbsoluteSlow,                     WRAP_NONE, CMP)
 359  
 360  rOP8 (DDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, CMP)
 361  rOP16(DDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, CMP)
 362  rOP8 (DDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, CMP)
 363  rOP16(DDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, CMP)
 364  rOPM (DDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, CMP)
 365  
 366  rOP8 (D9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, CMP)
 367  rOP16(D9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, CMP)
 368  rOP8 (D9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, CMP)
 369  rOP16(D9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, CMP)
 370  rOPM (D9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, CMP)
 371  
 372  rOP8 (CFM1,     AbsoluteLong,                     WRAP_NONE, CMP)
 373  rOP16(CFM0,     AbsoluteLong,                     WRAP_NONE, CMP)
 374  rOPM (CFSlow,   AbsoluteLongSlow,                 WRAP_NONE, CMP)
 375  
 376  rOP8 (DFM1,     AbsoluteLongIndexedX,             WRAP_NONE, CMP)
 377  rOP16(DFM0,     AbsoluteLongIndexedX,             WRAP_NONE, CMP)
 378  rOPM (DFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, CMP)
 379  
 380  rOP8 (C3M1,     StackRelative,                    WRAP_NONE, CMP)
 381  rOP16(C3M0,     StackRelative,                    WRAP_NONE, CMP)
 382  rOPM (C3Slow,   StackRelativeSlow,                WRAP_NONE, CMP)
 383  
 384  rOP8 (D3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, CMP)
 385  rOP16(D3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, CMP)
 386  rOPM (D3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, CMP)
 387  
 388  /* CPX ********************************************************************* */
 389  
 390  static void OpE0X1 (void)
 391  {
 392  	int16	Int16 = (int16) Registers.XL - (int16) Immediate8(READ);
 393  	SetCarryX(Int16 >= 0);
 394  	SetZN8(Int16);
 395  }
 396  
 397  static void OpE0X0 (void)
 398  {
 399  	int32	Int32 = (int32) Registers.X.W - (int32) Immediate16(READ);
 400  	SetCarryX(Int32 >= 0);
 401  	SetZN16((uint16) Int32);
 402  }
 403  
 404  static void OpE0Slow (void)
 405  {
 406  	if (CheckIndex())
 407  	{
 408  		int16	Int16 = (int16) Registers.XL - (int16) Immediate8Slow(READ);
 409  		SetCarryX(Int16 >= 0);
 410  		SetZN8(Int16);
 411  	}
 412  	else
 413  	{
 414  		int32	Int32 = (int32) Registers.X.W - (int32) Immediate16Slow(READ);
 415  		SetCarryX(Int32 >= 0);
 416  		SetZN16((uint16) Int32);
 417  	}
 418  }
 419  
 420  rOP8 (E4X1,     Direct,                           WRAP_BANK, CPX)
 421  rOP16(E4X0,     Direct,                           WRAP_BANK, CPX)
 422  rOPX (E4Slow,   DirectSlow,                       WRAP_BANK, CPX)
 423  
 424  rOP8 (ECX1,     Absolute,                         WRAP_NONE, CPX)
 425  rOP16(ECX0,     Absolute,                         WRAP_NONE, CPX)
 426  rOPX (ECSlow,   AbsoluteSlow,                     WRAP_NONE, CPX)
 427  
 428  /* CPY ********************************************************************* */
 429  
 430  static void OpC0X1 (void)
 431  {
 432  	int16	Int16 = (int16) Registers.YL - (int16) Immediate8(READ);
 433  	SetCarryX(Int16 >= 0);
 434  	SetZN8(Int16);
 435  }
 436  
 437  static void OpC0X0 (void)
 438  {
 439  	int32	Int32 = (int32) Registers.Y.W - (int32) Immediate16(READ);
 440  	SetCarryX(Int32 >= 0);
 441  	SetZN16((uint16) Int32);
 442  }
 443  
 444  static void OpC0Slow (void)
 445  {
 446  	if (CheckIndex())
 447  	{
 448  		int16	Int16 = (int16) Registers.YL - (int16) Immediate8Slow(READ);
 449  		SetCarryX(Int16 >= 0);
 450  		SetZN8(Int16);
 451  	}
 452  	else
 453  	{
 454  		int32	Int32 = (int32) Registers.Y.W - (int32) Immediate16Slow(READ);
 455  		SetCarryX(Int32 >= 0);
 456  		SetZN16((uint16) Int32);
 457  	}
 458  }
 459  
 460  rOP8 (C4X1,     Direct,                           WRAP_BANK, CPY)
 461  rOP16(C4X0,     Direct,                           WRAP_BANK, CPY)
 462  rOPX (C4Slow,   DirectSlow,                       WRAP_BANK, CPY)
 463  
 464  rOP8 (CCX1,     Absolute,                         WRAP_NONE, CPY)
 465  rOP16(CCX0,     Absolute,                         WRAP_NONE, CPY)
 466  rOPX (CCSlow,   AbsoluteSlow,                     WRAP_NONE, CPY)
 467  
 468  /* DEC ********************************************************************* */
 469  
 470  static void Op3AM1 (void)
 471  {
 472  	AddCycles(ONE_CYCLE);
 473  	Registers.AL--;
 474  	SetZN8(Registers.AL);
 475  }
 476  
 477  static void Op3AM0 (void)
 478  {
 479  	AddCycles(ONE_CYCLE);
 480  	Registers.A.W--;
 481  	SetZN16(Registers.A.W);
 482  }
 483  
 484  static void Op3ASlow (void)
 485  {
 486  	AddCycles(ONE_CYCLE);
 487  
 488  	if (CheckMemory())
 489  	{
 490  		Registers.AL--;
 491  		SetZN8(Registers.AL);
 492  	}
 493  	else
 494  	{
 495  		Registers.A.W--;
 496  		SetZN16(Registers.A.W);
 497  	}
 498  }
 499  
 500  mOP8 (C6M1,     Direct,                           WRAP_BANK, DEC)
 501  mOP16(C6M0,     Direct,                           WRAP_BANK, DEC)
 502  mOPM (C6Slow,   DirectSlow,                       WRAP_BANK, DEC)
 503  
 504  mOP8 (D6E0M1,   DirectIndexedXE0,                 WRAP_BANK, DEC)
 505  mOP16(D6E0M0,   DirectIndexedXE0,                 WRAP_BANK, DEC)
 506  mOPM (D6Slow,   DirectIndexedXSlow,               WRAP_BANK, DEC)
 507  
 508  mOP8 (CEM1,     Absolute,                         WRAP_NONE, DEC)
 509  mOP16(CEM0,     Absolute,                         WRAP_NONE, DEC)
 510  mOPM (CESlow,   AbsoluteSlow,                     WRAP_NONE, DEC)
 511  
 512  mOP8 (DEM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, DEC)
 513  mOP16(DEM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, DEC)
 514  mOP8 (DEM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, DEC)
 515  mOP16(DEM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, DEC)
 516  mOPM (DESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, DEC)
 517  
 518  /* EOR ********************************************************************* */
 519  
 520  static void Op49M1 (void)
 521  {
 522  	Registers.AL ^= Immediate8(READ);
 523  	SetZN8(Registers.AL);
 524  }
 525  
 526  static void Op49M0 (void)
 527  {
 528  	Registers.A.W ^= Immediate16(READ);
 529  	SetZN16(Registers.A.W);
 530  }
 531  
 532  static void Op49Slow (void)
 533  {
 534  	if (CheckMemory())
 535  	{
 536  		Registers.AL ^= Immediate8Slow(READ);
 537  		SetZN8(Registers.AL);
 538  	}
 539  	else
 540  	{
 541  		Registers.A.W ^= Immediate16Slow(READ);
 542  		SetZN16(Registers.A.W);
 543  	}
 544  }
 545  
 546  rOP8 (45M1,     Direct,                           WRAP_BANK, EOR)
 547  rOP16(45M0,     Direct,                           WRAP_BANK, EOR)
 548  rOPM (45Slow,   DirectSlow,                       WRAP_BANK, EOR)
 549  
 550  rOP8 (55E0M1,   DirectIndexedXE0,                 WRAP_BANK, EOR)
 551  rOP16(55E0M0,   DirectIndexedXE0,                 WRAP_BANK, EOR)
 552  rOPM (55Slow,   DirectIndexedXSlow,               WRAP_BANK, EOR)
 553  
 554  rOP8 (52E0M1,   DirectIndirectE0,                 WRAP_NONE, EOR)
 555  rOP16(52E0M0,   DirectIndirectE0,                 WRAP_NONE, EOR)
 556  rOPM (52Slow,   DirectIndirectSlow,               WRAP_NONE, EOR)
 557  
 558  rOP8 (41E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, EOR)
 559  rOP16(41E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, EOR)
 560  rOPM (41Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, EOR)
 561  
 562  rOP8 (51E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, EOR)
 563  rOP16(51E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, EOR)
 564  rOP8 (51E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, EOR)
 565  rOP16(51E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, EOR)
 566  rOPM (51Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, EOR)
 567  
 568  rOP8 (47M1,     DirectIndirectLong,               WRAP_NONE, EOR)
 569  rOP16(47M0,     DirectIndirectLong,               WRAP_NONE, EOR)
 570  rOPM (47Slow,   DirectIndirectLongSlow,           WRAP_NONE, EOR)
 571  
 572  rOP8 (57M1,     DirectIndirectIndexedLong,        WRAP_NONE, EOR)
 573  rOP16(57M0,     DirectIndirectIndexedLong,        WRAP_NONE, EOR)
 574  rOPM (57Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, EOR)
 575  
 576  rOP8 (4DM1,     Absolute,                         WRAP_NONE, EOR)
 577  rOP16(4DM0,     Absolute,                         WRAP_NONE, EOR)
 578  rOPM (4DSlow,   AbsoluteSlow,                     WRAP_NONE, EOR)
 579  
 580  rOP8 (5DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, EOR)
 581  rOP16(5DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, EOR)
 582  rOP8 (5DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, EOR)
 583  rOP16(5DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, EOR)
 584  rOPM (5DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, EOR)
 585  
 586  rOP8 (59M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, EOR)
 587  rOP16(59M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, EOR)
 588  rOP8 (59M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, EOR)
 589  rOP16(59M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, EOR)
 590  rOPM (59Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, EOR)
 591  
 592  rOP8 (4FM1,     AbsoluteLong,                     WRAP_NONE, EOR)
 593  rOP16(4FM0,     AbsoluteLong,                     WRAP_NONE, EOR)
 594  rOPM (4FSlow,   AbsoluteLongSlow,                 WRAP_NONE, EOR)
 595  
 596  rOP8 (5FM1,     AbsoluteLongIndexedX,             WRAP_NONE, EOR)
 597  rOP16(5FM0,     AbsoluteLongIndexedX,             WRAP_NONE, EOR)
 598  rOPM (5FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, EOR)
 599  
 600  rOP8 (43M1,     StackRelative,                    WRAP_NONE, EOR)
 601  rOP16(43M0,     StackRelative,                    WRAP_NONE, EOR)
 602  rOPM (43Slow,   StackRelativeSlow,                WRAP_NONE, EOR)
 603  
 604  rOP8 (53M1,     StackRelativeIndirectIndexed,     WRAP_NONE, EOR)
 605  rOP16(53M0,     StackRelativeIndirectIndexed,     WRAP_NONE, EOR)
 606  rOPM (53Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, EOR)
 607  
 608  /* INC ********************************************************************* */
 609  
 610  static void Op1AM1 (void)
 611  {
 612  	AddCycles(ONE_CYCLE);
 613  	Registers.AL++;
 614  	SetZN8(Registers.AL);
 615  }
 616  
 617  static void Op1AM0 (void)
 618  {
 619  	AddCycles(ONE_CYCLE);
 620  	Registers.A.W++;
 621  	SetZN16(Registers.A.W);
 622  }
 623  
 624  static void Op1ASlow (void)
 625  {
 626  	AddCycles(ONE_CYCLE);
 627  
 628  	if (CheckMemory())
 629  	{
 630  		Registers.AL++;
 631  		SetZN8(Registers.AL);
 632  	}
 633  	else
 634  	{
 635  		Registers.A.W++;
 636  		SetZN16(Registers.A.W);
 637  	}
 638  }
 639  
 640  mOP8 (E6M1,     Direct,                           WRAP_BANK, INC)
 641  mOP16(E6M0,     Direct,                           WRAP_BANK, INC)
 642  mOPM (E6Slow,   DirectSlow,                       WRAP_BANK, INC)
 643  
 644  mOP8 (F6E0M1,   DirectIndexedXE0,                 WRAP_BANK, INC)
 645  mOP16(F6E0M0,   DirectIndexedXE0,                 WRAP_BANK, INC)
 646  mOPM (F6Slow,   DirectIndexedXSlow,               WRAP_BANK, INC)
 647  
 648  mOP8 (EEM1,     Absolute,                         WRAP_NONE, INC)
 649  mOP16(EEM0,     Absolute,                         WRAP_NONE, INC)
 650  mOPM (EESlow,   AbsoluteSlow,                     WRAP_NONE, INC)
 651  
 652  mOP8 (FEM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, INC)
 653  mOP16(FEM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, INC)
 654  mOP8 (FEM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, INC)
 655  mOP16(FEM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, INC)
 656  mOPM (FESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, INC)
 657  
 658  /* LDA ********************************************************************* */
 659  
 660  static void OpA9M1 (void)
 661  {
 662  	Registers.AL = Immediate8(READ);
 663  	SetZN8(Registers.AL);
 664  }
 665  
 666  static void OpA9M0 (void)
 667  {
 668  	Registers.A.W = Immediate16(READ);
 669  	SetZN16(Registers.A.W);
 670  }
 671  
 672  static void OpA9Slow (void)
 673  {
 674  	if (CheckMemory())
 675  	{
 676  		Registers.AL = Immediate8Slow(READ);
 677  		SetZN8(Registers.AL);
 678  	}
 679  	else
 680  	{
 681  		Registers.A.W = Immediate16Slow(READ);
 682  		SetZN16(Registers.A.W);
 683  	}
 684  }
 685  
 686  rOP8 (A5M1,     Direct,                           WRAP_BANK, LDA)
 687  rOP16(A5M0,     Direct,                           WRAP_BANK, LDA)
 688  rOPM (A5Slow,   DirectSlow,                       WRAP_BANK, LDA)
 689  
 690  rOP8 (B5E0M1,   DirectIndexedXE0,                 WRAP_BANK, LDA)
 691  rOP16(B5E0M0,   DirectIndexedXE0,                 WRAP_BANK, LDA)
 692  rOPM (B5Slow,   DirectIndexedXSlow,               WRAP_BANK, LDA)
 693  
 694  rOP8 (B2E0M1,   DirectIndirectE0,                 WRAP_NONE, LDA)
 695  rOP16(B2E0M0,   DirectIndirectE0,                 WRAP_NONE, LDA)
 696  rOPM (B2Slow,   DirectIndirectSlow,               WRAP_NONE, LDA)
 697  
 698  rOP8 (A1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, LDA)
 699  rOP16(A1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, LDA)
 700  rOPM (A1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, LDA)
 701  
 702  rOP8 (B1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, LDA)
 703  rOP16(B1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, LDA)
 704  rOP8 (B1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, LDA)
 705  rOP16(B1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, LDA)
 706  rOPM (B1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, LDA)
 707  
 708  rOP8 (A7M1,     DirectIndirectLong,               WRAP_NONE, LDA)
 709  rOP16(A7M0,     DirectIndirectLong,               WRAP_NONE, LDA)
 710  rOPM (A7Slow,   DirectIndirectLongSlow,           WRAP_NONE, LDA)
 711  
 712  rOP8 (B7M1,     DirectIndirectIndexedLong,        WRAP_NONE, LDA)
 713  rOP16(B7M0,     DirectIndirectIndexedLong,        WRAP_NONE, LDA)
 714  rOPM (B7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, LDA)
 715  
 716  rOP8 (ADM1,     Absolute,                         WRAP_NONE, LDA)
 717  rOP16(ADM0,     Absolute,                         WRAP_NONE, LDA)
 718  rOPM (ADSlow,   AbsoluteSlow,                     WRAP_NONE, LDA)
 719  
 720  rOP8 (BDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, LDA)
 721  rOP16(BDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, LDA)
 722  rOP8 (BDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, LDA)
 723  rOP16(BDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, LDA)
 724  rOPM (BDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, LDA)
 725  
 726  rOP8 (B9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, LDA)
 727  rOP16(B9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, LDA)
 728  rOP8 (B9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, LDA)
 729  rOP16(B9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, LDA)
 730  rOPM (B9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, LDA)
 731  
 732  rOP8 (AFM1,     AbsoluteLong,                     WRAP_NONE, LDA)
 733  rOP16(AFM0,     AbsoluteLong,                     WRAP_NONE, LDA)
 734  rOPM (AFSlow,   AbsoluteLongSlow,                 WRAP_NONE, LDA)
 735  
 736  rOP8 (BFM1,     AbsoluteLongIndexedX,             WRAP_NONE, LDA)
 737  rOP16(BFM0,     AbsoluteLongIndexedX,             WRAP_NONE, LDA)
 738  rOPM (BFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, LDA)
 739  
 740  rOP8 (A3M1,     StackRelative,                    WRAP_NONE, LDA)
 741  rOP16(A3M0,     StackRelative,                    WRAP_NONE, LDA)
 742  rOPM (A3Slow,   StackRelativeSlow,                WRAP_NONE, LDA)
 743  
 744  rOP8 (B3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, LDA)
 745  rOP16(B3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, LDA)
 746  rOPM (B3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, LDA)
 747  
 748  /* LDX ********************************************************************* */
 749  
 750  static void OpA2X1 (void)
 751  {
 752  	Registers.XL = Immediate8(READ);
 753  	SetZN8(Registers.XL);
 754  }
 755  
 756  static void OpA2X0 (void)
 757  {
 758  	Registers.X.W = Immediate16(READ);
 759  	SetZN16(Registers.X.W);
 760  }
 761  
 762  static void OpA2Slow (void)
 763  {
 764  	if (CheckIndex())
 765  	{
 766  		Registers.XL = Immediate8Slow(READ);
 767  		SetZN8(Registers.XL);
 768  	}
 769  	else
 770  	{
 771  		Registers.X.W = Immediate16Slow(READ);
 772  		SetZN16(Registers.X.W);
 773  	}
 774  }
 775  
 776  rOP8 (A6X1,     Direct,                           WRAP_BANK, LDX)
 777  rOP16(A6X0,     Direct,                           WRAP_BANK, LDX)
 778  rOPX (A6Slow,   DirectSlow,                       WRAP_BANK, LDX)
 779  
 780  rOP8 (B6E0X1,   DirectIndexedYE0,                 WRAP_BANK, LDX)
 781  rOP16(B6E0X0,   DirectIndexedYE0,                 WRAP_BANK, LDX)
 782  rOPX (B6Slow,   DirectIndexedYSlow,               WRAP_BANK, LDX)
 783  
 784  rOP8 (AEX1,     Absolute,                         WRAP_BANK, LDX)
 785  rOP16(AEX0,     Absolute,                         WRAP_BANK, LDX)
 786  rOPX (AESlow,   AbsoluteSlow,                     WRAP_BANK, LDX)
 787  
 788  rOP8 (BEX1,     AbsoluteIndexedYX1,               WRAP_BANK, LDX)
 789  rOP16(BEX0,     AbsoluteIndexedYX0,               WRAP_BANK, LDX)
 790  rOPX (BESlow,   AbsoluteIndexedYSlow,             WRAP_BANK, LDX)
 791  
 792  /* LDY ********************************************************************* */
 793  
 794  static void OpA0X1 (void)
 795  {
 796  	Registers.YL = Immediate8(READ);
 797  	SetZN8(Registers.YL);
 798  }
 799  
 800  static void OpA0X0 (void)
 801  {
 802  	Registers.Y.W = Immediate16(READ);
 803  	SetZN16(Registers.Y.W);
 804  }
 805  
 806  static void OpA0Slow (void)
 807  {
 808  	if (CheckIndex())
 809  	{
 810  		Registers.YL = Immediate8Slow(READ);
 811  		SetZN8(Registers.YL);
 812  	}
 813  	else
 814  	{
 815  		Registers.Y.W = Immediate16Slow(READ);
 816  		SetZN16(Registers.Y.W);
 817  	}
 818  }
 819  
 820  rOP8 (A4X1,     Direct,                           WRAP_BANK, LDY)
 821  rOP16(A4X0,     Direct,                           WRAP_BANK, LDY)
 822  rOPX (A4Slow,   DirectSlow,                       WRAP_BANK, LDY)
 823  
 824  rOP8 (B4E0X1,   DirectIndexedXE0,                 WRAP_BANK, LDY)
 825  rOP16(B4E0X0,   DirectIndexedXE0,                 WRAP_BANK, LDY)
 826  rOPX (B4Slow,   DirectIndexedXSlow,               WRAP_BANK, LDY)
 827  
 828  rOP8 (ACX1,     Absolute,                         WRAP_BANK, LDY)
 829  rOP16(ACX0,     Absolute,                         WRAP_BANK, LDY)
 830  rOPX (ACSlow,   AbsoluteSlow,                     WRAP_BANK, LDY)
 831  
 832  rOP8 (BCX1,     AbsoluteIndexedXX1,               WRAP_BANK, LDY)
 833  rOP16(BCX0,     AbsoluteIndexedXX0,               WRAP_BANK, LDY)
 834  rOPX (BCSlow,   AbsoluteIndexedXSlow,             WRAP_BANK, LDY)
 835  
 836  /* LSR ********************************************************************* */
 837  
 838  static void Op4AM1 (void)
 839  {
 840  	AddCycles(ONE_CYCLE);
 841  	SetCarryX(Registers.AL & 1);
 842  	Registers.AL >>= 1;
 843  	SetZN8(Registers.AL);
 844  }
 845  
 846  static void Op4AM0 (void)
 847  {
 848  	AddCycles(ONE_CYCLE);
 849  	SetCarryX(Registers.A.W & 1);
 850  	Registers.A.W >>= 1;
 851  	SetZN16(Registers.A.W);
 852  }
 853  
 854  static void Op4ASlow (void)
 855  {
 856  	AddCycles(ONE_CYCLE);
 857  
 858  	if (CheckMemory())
 859  	{
 860  		SetCarryX(Registers.AL & 1);
 861  		Registers.AL >>= 1;
 862  		SetZN8(Registers.AL);
 863  	}
 864  	else
 865  	{
 866  		SetCarryX(Registers.A.W & 1);
 867  		Registers.A.W >>= 1;
 868  		SetZN16(Registers.A.W);
 869  	}
 870  }
 871  
 872  mOP8 (46M1,     Direct,                           WRAP_BANK, LSR)
 873  mOP16(46M0,     Direct,                           WRAP_BANK, LSR)
 874  mOPM (46Slow,   DirectSlow,                       WRAP_BANK, LSR)
 875  
 876  mOP8 (56E0M1,   DirectIndexedXE0,                 WRAP_BANK, LSR)
 877  mOP16(56E0M0,   DirectIndexedXE0,                 WRAP_BANK, LSR)
 878  mOPM (56Slow,   DirectIndexedXSlow,               WRAP_BANK, LSR)
 879  
 880  mOP8 (4EM1,     Absolute,                         WRAP_NONE, LSR)
 881  mOP16(4EM0,     Absolute,                         WRAP_NONE, LSR)
 882  mOPM (4ESlow,   AbsoluteSlow,                     WRAP_NONE, LSR)
 883  
 884  mOP8 (5EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, LSR)
 885  mOP16(5EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, LSR)
 886  mOP8 (5EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, LSR)
 887  mOP16(5EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, LSR)
 888  mOPM (5ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, LSR)
 889  
 890  /* ORA ********************************************************************* */
 891  
 892  static void Op09M1 (void)
 893  {
 894  	Registers.AL |= Immediate8(READ);
 895  	SetZN8(Registers.AL);
 896  }
 897  
 898  static void Op09M0 (void)
 899  {
 900  	Registers.A.W |= Immediate16(READ);
 901  	SetZN16(Registers.A.W);
 902  }
 903  
 904  static void Op09Slow (void)
 905  {
 906  	if (CheckMemory())
 907  	{
 908  		Registers.AL |= Immediate8Slow(READ);
 909  		SetZN8(Registers.AL);
 910  	}
 911  	else
 912  	{
 913  		Registers.A.W |= Immediate16Slow(READ);
 914  		SetZN16(Registers.A.W);
 915  	}
 916  }
 917  
 918  rOP8 (05M1,     Direct,                           WRAP_BANK, ORA)
 919  rOP16(05M0,     Direct,                           WRAP_BANK, ORA)
 920  rOPM (05Slow,   DirectSlow,                       WRAP_BANK, ORA)
 921  
 922  rOP8 (15E0M1,   DirectIndexedXE0,                 WRAP_BANK, ORA)
 923  rOP16(15E0M0,   DirectIndexedXE0,                 WRAP_BANK, ORA)
 924  rOPM (15Slow,   DirectIndexedXSlow,               WRAP_BANK, ORA)
 925  
 926  rOP8 (12E0M1,   DirectIndirectE0,                 WRAP_NONE, ORA)
 927  rOP16(12E0M0,   DirectIndirectE0,                 WRAP_NONE, ORA)
 928  rOPM (12Slow,   DirectIndirectSlow,               WRAP_NONE, ORA)
 929  
 930  rOP8 (01E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, ORA)
 931  rOP16(01E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, ORA)
 932  rOPM (01Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, ORA)
 933  
 934  rOP8 (11E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ORA)
 935  rOP16(11E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, ORA)
 936  rOP8 (11E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ORA)
 937  rOP16(11E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, ORA)
 938  rOPM (11Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, ORA)
 939  
 940  rOP8 (07M1,     DirectIndirectLong,               WRAP_NONE, ORA)
 941  rOP16(07M0,     DirectIndirectLong,               WRAP_NONE, ORA)
 942  rOPM (07Slow,   DirectIndirectLongSlow,           WRAP_NONE, ORA)
 943  
 944  rOP8 (17M1,     DirectIndirectIndexedLong,        WRAP_NONE, ORA)
 945  rOP16(17M0,     DirectIndirectIndexedLong,        WRAP_NONE, ORA)
 946  rOPM (17Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, ORA)
 947  
 948  rOP8 (0DM1,     Absolute,                         WRAP_NONE, ORA)
 949  rOP16(0DM0,     Absolute,                         WRAP_NONE, ORA)
 950  rOPM (0DSlow,   AbsoluteSlow,                     WRAP_NONE, ORA)
 951  
 952  rOP8 (1DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ORA)
 953  rOP16(1DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ORA)
 954  rOP8 (1DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ORA)
 955  rOP16(1DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ORA)
 956  rOPM (1DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ORA)
 957  
 958  rOP8 (19M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, ORA)
 959  rOP16(19M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, ORA)
 960  rOP8 (19M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, ORA)
 961  rOP16(19M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, ORA)
 962  rOPM (19Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, ORA)
 963  
 964  rOP8 (0FM1,     AbsoluteLong,                     WRAP_NONE, ORA)
 965  rOP16(0FM0,     AbsoluteLong,                     WRAP_NONE, ORA)
 966  rOPM (0FSlow,   AbsoluteLongSlow,                 WRAP_NONE, ORA)
 967  
 968  rOP8 (1FM1,     AbsoluteLongIndexedX,             WRAP_NONE, ORA)
 969  rOP16(1FM0,     AbsoluteLongIndexedX,             WRAP_NONE, ORA)
 970  rOPM (1FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, ORA)
 971  
 972  rOP8 (03M1,     StackRelative,                    WRAP_NONE, ORA)
 973  rOP16(03M0,     StackRelative,                    WRAP_NONE, ORA)
 974  rOPM (03Slow,   StackRelativeSlow,                WRAP_NONE, ORA)
 975  
 976  rOP8 (13M1,     StackRelativeIndirectIndexed,     WRAP_NONE, ORA)
 977  rOP16(13M0,     StackRelativeIndirectIndexed,     WRAP_NONE, ORA)
 978  rOPM (13Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, ORA)
 979  
 980  /* ROL ********************************************************************* */
 981  
 982  static void Op2AM1 (void)
 983  {
 984  	uint32	w = (((uint32) Registers.AL) << 1) | CheckCarry();
 985  	AddCycles(ONE_CYCLE);
 986  	ClearFlags(Carry);
 987  	SetFlags((w >> 8) & 1);
 988  	w &= 0xFF;
 989  	Registers.AL = w;
 990  	SetZN8(w);
 991  }
 992  
 993  static void Op2AM0 (void)
 994  {
 995  	uint32	w = (((uint32) Registers.A.W) << 1) | CheckCarry();
 996  	AddCycles(ONE_CYCLE);
 997  	ClearFlags(Carry);
 998  	SetFlags((w >> 16) & 1);
 999  	w &= 0xFFFF;
1000  	Registers.A.W = w;
1001  	SetZN16(w);
1002  }
1003  
1004  static void Op2ASlow (void)
1005  {
1006  	if (CheckMemory())
1007  		Op2AM1();
1008  	else
1009  		Op2AM0();
1010  }
1011  
1012  mOP8 (26M1,     Direct,                           WRAP_BANK, ROL)
1013  mOP16(26M0,     Direct,                           WRAP_BANK, ROL)
1014  mOPM (26Slow,   DirectSlow,                       WRAP_BANK, ROL)
1015  
1016  mOP8 (36E0M1,   DirectIndexedXE0,                 WRAP_BANK, ROL)
1017  mOP16(36E0M0,   DirectIndexedXE0,                 WRAP_BANK, ROL)
1018  mOPM (36Slow,   DirectIndexedXSlow,               WRAP_BANK, ROL)
1019  
1020  mOP8 (2EM1,     Absolute,                         WRAP_NONE, ROL)
1021  mOP16(2EM0,     Absolute,                         WRAP_NONE, ROL)
1022  mOPM (2ESlow,   AbsoluteSlow,                     WRAP_NONE, ROL)
1023  
1024  mOP8 (3EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROL)
1025  mOP16(3EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROL)
1026  mOP8 (3EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROL)
1027  mOP16(3EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROL)
1028  mOPM (3ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ROL)
1029  
1030  /* ROR ********************************************************************* */
1031  
1032  static void Op6AM1 (void)
1033  {
1034  	uint32 w = (((uint32) CheckCarry()) << 8) | Registers.AL;
1035  	AddCycles(ONE_CYCLE);
1036  	ClearFlags(Carry);
1037  	SetFlags(w & 1);
1038  	w >>= 1;
1039  	Registers.AL = w;
1040  	SetZN8(w);
1041  }
1042  
1043  static void Op6AM0 (void)
1044  {
1045  	uint32 w = (((uint32) CheckCarry()) << 16) | Registers.A.W;
1046  	AddCycles(ONE_CYCLE);
1047  	ClearFlags(Carry);
1048  	SetFlags(w & 1);
1049  	w >>= 1;
1050  	Registers.A.W = w;
1051  	SetZN16(w);
1052  }
1053  
1054  static void Op6ASlow (void)
1055  {
1056  	if (CheckMemory())
1057  		Op6AM1();
1058  	else
1059  		Op6AM0();
1060  }
1061  
1062  mOP8 (66M1,     Direct,                           WRAP_BANK, ROR)
1063  mOP16(66M0,     Direct,                           WRAP_BANK, ROR)
1064  mOPM (66Slow,   DirectSlow,                       WRAP_BANK, ROR)
1065  
1066  mOP8 (76E0M1,   DirectIndexedXE0,                 WRAP_BANK, ROR)
1067  mOP16(76E0M0,   DirectIndexedXE0,                 WRAP_BANK, ROR)
1068  mOPM (76Slow,   DirectIndexedXSlow,               WRAP_BANK, ROR)
1069  
1070  mOP8 (6EM1,     Absolute,                         WRAP_NONE, ROR)
1071  mOP16(6EM0,     Absolute,                         WRAP_NONE, ROR)
1072  mOPM (6ESlow,   AbsoluteSlow,                     WRAP_NONE, ROR)
1073  
1074  mOP8 (7EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROR)
1075  mOP16(7EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, ROR)
1076  mOP8 (7EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROR)
1077  mOP16(7EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, ROR)
1078  mOPM (7ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, ROR)
1079  
1080  /* SBC ********************************************************************* */
1081  
1082  static void OpE9M1 (void)
1083  {
1084  	SBC8(Immediate8(READ));
1085  }
1086  
1087  static void OpE9M0 (void)
1088  {
1089  	SBC16(Immediate16(READ));
1090  }
1091  
1092  static void OpE9Slow (void)
1093  {
1094  	if (CheckMemory())
1095  		SBC8(Immediate8Slow(READ));
1096  	else
1097  		SBC16(Immediate16Slow(READ));
1098  }
1099  
1100  rOP8 (E5M1,     Direct,                           WRAP_BANK, SBC)
1101  rOP16(E5M0,     Direct,                           WRAP_BANK, SBC)
1102  rOPM (E5Slow,   DirectSlow,                       WRAP_BANK, SBC)
1103  
1104  rOP8 (F5E0M1,   DirectIndexedXE0,                 WRAP_BANK, SBC)
1105  rOP16(F5E0M0,   DirectIndexedXE0,                 WRAP_BANK, SBC)
1106  rOPM (F5Slow,   DirectIndexedXSlow,               WRAP_BANK, SBC)
1107  
1108  rOP8 (F2E0M1,   DirectIndirectE0,                 WRAP_NONE, SBC)
1109  rOP16(F2E0M0,   DirectIndirectE0,                 WRAP_NONE, SBC)
1110  rOPM (F2Slow,   DirectIndirectSlow,               WRAP_NONE, SBC)
1111  
1112  rOP8 (E1E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, SBC)
1113  rOP16(E1E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, SBC)
1114  rOPM (E1Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, SBC)
1115  
1116  rOP8 (F1E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, SBC)
1117  rOP16(F1E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, SBC)
1118  rOP8 (F1E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, SBC)
1119  rOP16(F1E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, SBC)
1120  rOPM (F1Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, SBC)
1121  
1122  rOP8 (E7M1,     DirectIndirectLong,               WRAP_NONE, SBC)
1123  rOP16(E7M0,     DirectIndirectLong,               WRAP_NONE, SBC)
1124  rOPM (E7Slow,   DirectIndirectLongSlow,           WRAP_NONE, SBC)
1125  
1126  rOP8 (F7M1,     DirectIndirectIndexedLong,        WRAP_NONE, SBC)
1127  rOP16(F7M0,     DirectIndirectIndexedLong,        WRAP_NONE, SBC)
1128  rOPM (F7Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, SBC)
1129  
1130  rOP8 (EDM1,     Absolute,                         WRAP_NONE, SBC)
1131  rOP16(EDM0,     Absolute,                         WRAP_NONE, SBC)
1132  rOPM (EDSlow,   AbsoluteSlow,                     WRAP_NONE, SBC)
1133  
1134  rOP8 (FDM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, SBC)
1135  rOP16(FDM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, SBC)
1136  rOP8 (FDM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, SBC)
1137  rOP16(FDM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, SBC)
1138  rOPM (FDSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, SBC)
1139  
1140  rOP8 (F9M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, SBC)
1141  rOP16(F9M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, SBC)
1142  rOP8 (F9M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, SBC)
1143  rOP16(F9M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, SBC)
1144  rOPM (F9Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, SBC)
1145  
1146  rOP8 (EFM1,     AbsoluteLong,                     WRAP_NONE, SBC)
1147  rOP16(EFM0,     AbsoluteLong,                     WRAP_NONE, SBC)
1148  rOPM (EFSlow,   AbsoluteLongSlow,                 WRAP_NONE, SBC)
1149  
1150  rOP8 (FFM1,     AbsoluteLongIndexedX,             WRAP_NONE, SBC)
1151  rOP16(FFM0,     AbsoluteLongIndexedX,             WRAP_NONE, SBC)
1152  rOPM (FFSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, SBC)
1153  
1154  rOP8 (E3M1,     StackRelative,                    WRAP_NONE, SBC)
1155  rOP16(E3M0,     StackRelative,                    WRAP_NONE, SBC)
1156  rOPM (E3Slow,   StackRelativeSlow,                WRAP_NONE, SBC)
1157  
1158  rOP8 (F3M1,     StackRelativeIndirectIndexed,     WRAP_NONE, SBC)
1159  rOP16(F3M0,     StackRelativeIndirectIndexed,     WRAP_NONE, SBC)
1160  rOPM (F3Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, SBC)
1161  
1162  /* STA ********************************************************************* */
1163  
1164  wOP8 (85M1,     Direct,                           WRAP_BANK, STA)
1165  wOP16(85M0,     Direct,                           WRAP_BANK, STA)
1166  wOPM (85Slow,   DirectSlow,                       WRAP_BANK, STA)
1167  
1168  wOP8 (95E0M1,   DirectIndexedXE0,                 WRAP_BANK, STA)
1169  wOP16(95E0M0,   DirectIndexedXE0,                 WRAP_BANK, STA)
1170  wOPM (95Slow,   DirectIndexedXSlow,               WRAP_BANK, STA)
1171  
1172  wOP8 (92E0M1,   DirectIndirectE0,                 WRAP_NONE, STA)
1173  wOP16(92E0M0,   DirectIndirectE0,                 WRAP_NONE, STA)
1174  wOPM (92Slow,   DirectIndirectSlow,               WRAP_NONE, STA)
1175  
1176  wOP8 (81E0M1,   DirectIndexedIndirectE0,          WRAP_NONE, STA)
1177  wOP16(81E0M0,   DirectIndexedIndirectE0,          WRAP_NONE, STA)
1178  wOPM (81Slow,   DirectIndexedIndirectSlow,        WRAP_NONE, STA)
1179  
1180  wOP8 (91E0M1X1, DirectIndirectIndexedE0X1,        WRAP_NONE, STA)
1181  wOP16(91E0M0X1, DirectIndirectIndexedE0X1,        WRAP_NONE, STA)
1182  wOP8 (91E0M1X0, DirectIndirectIndexedE0X0,        WRAP_NONE, STA)
1183  wOP16(91E0M0X0, DirectIndirectIndexedE0X0,        WRAP_NONE, STA)
1184  wOPM (91Slow,   DirectIndirectIndexedSlow,        WRAP_NONE, STA)
1185  
1186  wOP8 (87M1,     DirectIndirectLong,               WRAP_NONE, STA)
1187  wOP16(87M0,     DirectIndirectLong,               WRAP_NONE, STA)
1188  wOPM (87Slow,   DirectIndirectLongSlow,           WRAP_NONE, STA)
1189  
1190  wOP8 (97M1,     DirectIndirectIndexedLong,        WRAP_NONE, STA)
1191  wOP16(97M0,     DirectIndirectIndexedLong,        WRAP_NONE, STA)
1192  wOPM (97Slow,   DirectIndirectIndexedLongSlow,    WRAP_NONE, STA)
1193  
1194  wOP8 (8DM1,     Absolute,                         WRAP_NONE, STA)
1195  wOP16(8DM0,     Absolute,                         WRAP_NONE, STA)
1196  wOPM (8DSlow,   AbsoluteSlow,                     WRAP_NONE, STA)
1197  
1198  wOP8 (9DM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, STA)
1199  wOP16(9DM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, STA)
1200  wOP8 (9DM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, STA)
1201  wOP16(9DM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, STA)
1202  wOPM (9DSlow,   AbsoluteIndexedXSlow,             WRAP_NONE, STA)
1203  
1204  wOP8 (99M1X1,   AbsoluteIndexedYX1,               WRAP_NONE, STA)
1205  wOP16(99M0X1,   AbsoluteIndexedYX1,               WRAP_NONE, STA)
1206  wOP8 (99M1X0,   AbsoluteIndexedYX0,               WRAP_NONE, STA)
1207  wOP16(99M0X0,   AbsoluteIndexedYX0,               WRAP_NONE, STA)
1208  wOPM (99Slow,   AbsoluteIndexedYSlow,             WRAP_NONE, STA)
1209  
1210  wOP8 (8FM1,     AbsoluteLong,                     WRAP_NONE, STA)
1211  wOP16(8FM0,     AbsoluteLong,                     WRAP_NONE, STA)
1212  wOPM (8FSlow,   AbsoluteLongSlow,                 WRAP_NONE, STA)
1213  
1214  wOP8 (9FM1,     AbsoluteLongIndexedX,             WRAP_NONE, STA)
1215  wOP16(9FM0,     AbsoluteLongIndexedX,             WRAP_NONE, STA)
1216  wOPM (9FSlow,   AbsoluteLongIndexedXSlow,         WRAP_NONE, STA)
1217  
1218  wOP8 (83M1,     StackRelative,                    WRAP_NONE, STA)
1219  wOP16(83M0,     StackRelative,                    WRAP_NONE, STA)
1220  wOPM (83Slow,   StackRelativeSlow,                WRAP_NONE, STA)
1221  
1222  wOP8 (93M1,     StackRelativeIndirectIndexed,     WRAP_NONE, STA)
1223  wOP16(93M0,     StackRelativeIndirectIndexed,     WRAP_NONE, STA)
1224  wOPM (93Slow,   StackRelativeIndirectIndexedSlow, WRAP_NONE, STA)
1225  
1226  /* STX ********************************************************************* */
1227  
1228  wOP8 (86X1,     Direct,                           WRAP_BANK, STX)
1229  wOP16(86X0,     Direct,                           WRAP_BANK, STX)
1230  wOPX (86Slow,   DirectSlow,                       WRAP_BANK, STX)
1231  
1232  wOP8 (96E0X1,   DirectIndexedYE0,                 WRAP_BANK, STX)
1233  wOP16(96E0X0,   DirectIndexedYE0,                 WRAP_BANK, STX)
1234  wOPX (96Slow,   DirectIndexedYSlow,               WRAP_BANK, STX)
1235  
1236  wOP8 (8EX1,     Absolute,                         WRAP_BANK, STX)
1237  wOP16(8EX0,     Absolute,                         WRAP_BANK, STX)
1238  wOPX (8ESlow,   AbsoluteSlow,                     WRAP_BANK, STX)
1239  
1240  /* STY ********************************************************************* */
1241  
1242  wOP8 (84X1,     Direct,                           WRAP_BANK, STY)
1243  wOP16(84X0,     Direct,                           WRAP_BANK, STY)
1244  wOPX (84Slow,   DirectSlow,                       WRAP_BANK, STY)
1245  
1246  wOP8 (94E0X1,   DirectIndexedXE0,                 WRAP_BANK, STY)
1247  wOP16(94E0X0,   DirectIndexedXE0,                 WRAP_BANK, STY)
1248  wOPX (94Slow,   DirectIndexedXSlow,               WRAP_BANK, STY)
1249  
1250  wOP8 (8CX1,     Absolute,                         WRAP_BANK, STY)
1251  wOP16(8CX0,     Absolute,                         WRAP_BANK, STY)
1252  wOPX (8CSlow,   AbsoluteSlow,                     WRAP_BANK, STY)
1253  
1254  /* STZ ********************************************************************* */
1255  
1256  wOP8 (64M1,     Direct,                           WRAP_BANK, STZ)
1257  wOP16(64M0,     Direct,                           WRAP_BANK, STZ)
1258  wOPM (64Slow,   DirectSlow,                       WRAP_BANK, STZ)
1259  
1260  wOP8 (74E0M1,   DirectIndexedXE0,                 WRAP_BANK, STZ)
1261  wOP16(74E0M0,   DirectIndexedXE0,                 WRAP_BANK, STZ)
1262  wOPM (74Slow,   DirectIndexedXSlow,               WRAP_BANK, STZ)
1263  
1264  wOP8 (9CM1,     Absolute,                         WRAP_NONE, STZ)
1265  wOP16(9CM0,     Absolute,                         WRAP_NONE, STZ)
1266  wOPM (9CSlow,   AbsoluteSlow,                     WRAP_NONE, STZ)
1267  
1268  wOP8 (9EM1X1,   AbsoluteIndexedXX1,               WRAP_NONE, STZ)
1269  wOP16(9EM0X1,   AbsoluteIndexedXX1,               WRAP_NONE, STZ)
1270  wOP8 (9EM1X0,   AbsoluteIndexedXX0,               WRAP_NONE, STZ)
1271  wOP16(9EM0X0,   AbsoluteIndexedXX0,               WRAP_NONE, STZ)
1272  wOPM (9ESlow,   AbsoluteIndexedXSlow,             WRAP_NONE, STZ)
1273  
1274  /* TRB ********************************************************************* */
1275  
1276  mOP8 (14M1,     Direct,                           WRAP_BANK, TRB)
1277  mOP16(14M0,     Direct,                           WRAP_BANK, TRB)
1278  mOPM (14Slow,   DirectSlow,                       WRAP_BANK, TRB)
1279  
1280  mOP8 (1CM1,     Absolute,                         WRAP_BANK, TRB)
1281  mOP16(1CM0,     Absolute,                         WRAP_BANK, TRB)
1282  mOPM (1CSlow,   AbsoluteSlow,                     WRAP_BANK, TRB)
1283  
1284  /* TSB ********************************************************************* */
1285  
1286  mOP8 (04M1,     Direct,                           WRAP_BANK, TSB)
1287  mOP16(04M0,     Direct,                           WRAP_BANK, TSB)
1288  mOPM (04Slow,   DirectSlow,                       WRAP_BANK, TSB)
1289  
1290  mOP8 (0CM1,     Absolute,                         WRAP_BANK, TSB)
1291  mOP16(0CM0,     Absolute,                         WRAP_BANK, TSB)
1292  mOPM (0CSlow,   AbsoluteSlow,                     WRAP_BANK, TSB)
1293  
1294  /* Branch Instructions ***************************************************** */
1295  
1296  // BCC
1297  bOP(90E0,   Immediate8,     !CheckCarry(),    0, 0)
1298  bOP(90Slow, Immediate8Slow, !CheckCarry(),    0, CheckEmulation())
1299  
1300  // BCS
1301  bOP(B0E0,   Immediate8,      CheckCarry(),    0, 0)
1302  bOP(B0Slow, Immediate8Slow,  CheckCarry(),    0, CheckEmulation())
1303  
1304  // BEQ
1305  bOP(F0E0,   Immediate8,      CheckZero(),     2, 0)
1306  bOP(F0Slow, Immediate8Slow,  CheckZero(),     2, CheckEmulation())
1307  
1308  // BMI
1309  bOP(30E0,   Immediate8,      CheckNegative(), 1, 0)
1310  bOP(30Slow, Immediate8Slow,  CheckNegative(), 1, CheckEmulation())
1311  
1312  // BNE
1313  bOP(D0E0,   Immediate8,     !CheckZero(),     1, 0)
1314  bOP(D0Slow, Immediate8Slow, !CheckZero(),     1, CheckEmulation())
1315  
1316  // BPL
1317  bOP(10E0,   Immediate8,     !CheckNegative(), 1, 0)
1318  bOP(10Slow, Immediate8Slow, !CheckNegative(), 1, CheckEmulation())
1319  
1320  // BRA
1321  bOP(80E0,   Immediate8,     1,                X, 0)
1322  bOP(80Slow, Immediate8Slow, 1,                X, CheckEmulation())
1323  
1324  // BVC
1325  bOP(50E0,   Immediate8,     !CheckOverflow(), 0, 0)
1326  bOP(50Slow, Immediate8Slow, !CheckOverflow(), 0, CheckEmulation())
1327  
1328  // BVS
1329  bOP(70E0,   Immediate8,      CheckOverflow(), 0, 0)
1330  bOP(70Slow, Immediate8Slow,  CheckOverflow(), 0, CheckEmulation())
1331  
1332  // BRL
1333  static void Op82 (void)
1334  {
1335  	S9xSetPCBase(ICPU.ShiftedPB + RelativeLong(JUMP));
1336  }
1337  
1338  static void Op82Slow (void)
1339  {
1340  	S9xSetPCBase(ICPU.ShiftedPB + RelativeLongSlow(JUMP));
1341  }
1342  
1343  /* Flag Instructions ******************************************************* */
1344  
1345  // CLC
1346  static void Op18 (void)
1347  {
1348  	ClearCarry();
1349  	AddCycles(ONE_CYCLE);
1350  }
1351  
1352  // SEC
1353  static void Op38 (void)
1354  {
1355  	SetCarry();
1356  	AddCycles(ONE_CYCLE);
1357  }
1358  
1359  // CLD
1360  static void OpD8 (void)
1361  {
1362  	ClearDecimal();
1363  	AddCycles(ONE_CYCLE);
1364  }
1365  
1366  // SED
1367  static void OpF8 (void)
1368  {
1369  	SetDecimal();
1370  	AddCycles(ONE_CYCLE);
1371  }
1372  
1373  // CLI
1374  static void Op58 (void)
1375  {
1376  	AddCycles(ONE_CYCLE);
1377  
1378  	CPU.IRQFlagChanging |= IRQ_CLEAR_FLAG;
1379  }
1380  
1381  // SEI
1382  static void Op78 (void)
1383  {
1384  	AddCycles(ONE_CYCLE);
1385  
1386  	CPU.IRQFlagChanging |= IRQ_SET_FLAG;
1387  }
1388  
1389  // CLV
1390  static void OpB8 (void)
1391  {
1392  	ClearOverflow();
1393  	AddCycles(ONE_CYCLE);
1394  }
1395  
1396  /* DEX/DEY ***************************************************************** */
1397  
1398  static void OpCAX1 (void)
1399  {
1400  	AddCycles(ONE_CYCLE);
1401  	Registers.XL--;
1402  	SetZN8(Registers.XL);
1403  }
1404  
1405  static void OpCAX0 (void)
1406  {
1407  	AddCycles(ONE_CYCLE);
1408  	Registers.X.W--;
1409  	SetZN16(Registers.X.W);
1410  }
1411  
1412  static void OpCASlow (void)
1413  {
1414  	AddCycles(ONE_CYCLE);
1415  
1416  	if (CheckIndex())
1417  	{
1418  		Registers.XL--;
1419  		SetZN8(Registers.XL);
1420  	}
1421  	else
1422  	{
1423  		Registers.X.W--;
1424  		SetZN16(Registers.X.W);
1425  	}
1426  }
1427  
1428  static void Op88X1 (void)
1429  {
1430  	AddCycles(ONE_CYCLE);
1431  	Registers.YL--;
1432  	SetZN8(Registers.YL);
1433  }
1434  
1435  static void Op88X0 (void)
1436  {
1437  	AddCycles(ONE_CYCLE);
1438  	Registers.Y.W--;
1439  	SetZN16(Registers.Y.W);
1440  }
1441  
1442  static void Op88Slow (void)
1443  {
1444  	AddCycles(ONE_CYCLE);
1445  
1446  	if (CheckIndex())
1447  	{
1448  		Registers.YL--;
1449  		SetZN8(Registers.YL);
1450  	}
1451  	else
1452  	{
1453  		Registers.Y.W--;
1454  		SetZN16(Registers.Y.W);
1455  	}
1456  }
1457  
1458  /* INX/INY ***************************************************************** */
1459  
1460  static void OpE8X1 (void)
1461  {
1462  	AddCycles(ONE_CYCLE);
1463  	Registers.XL++;
1464  	SetZN8(Registers.XL);
1465  }
1466  
1467  static void OpE8X0 (void)
1468  {
1469  	AddCycles(ONE_CYCLE);
1470  	Registers.X.W++;
1471  	SetZN16(Registers.X.W);
1472  }
1473  
1474  static void OpE8Slow (void)
1475  {
1476  	AddCycles(ONE_CYCLE);
1477  
1478  	if (CheckIndex())
1479  	{
1480  		Registers.XL++;
1481  		SetZN8(Registers.XL);
1482  	}
1483  	else
1484  	{
1485  		Registers.X.W++;
1486  		SetZN16(Registers.X.W);
1487  	}
1488  }
1489  
1490  static void OpC8X1 (void)
1491  {
1492  	AddCycles(ONE_CYCLE);
1493  	Registers.YL++;
1494  	SetZN8(Registers.YL);
1495  }
1496  
1497  static void OpC8X0 (void)
1498  {
1499  	AddCycles(ONE_CYCLE);
1500  	Registers.Y.W++;
1501  	SetZN16(Registers.Y.W);
1502  }
1503  
1504  static void OpC8Slow (void)
1505  {
1506  	AddCycles(ONE_CYCLE);
1507  
1508  	if (CheckIndex())
1509  	{
1510  		Registers.YL++;
1511  		SetZN8(Registers.YL);
1512  	}
1513  	else
1514  	{
1515  		Registers.Y.W++;
1516  		SetZN16(Registers.Y.W);
1517  	}
1518  }
1519  
1520  /* NOP ********************************************************************* */
1521  
1522  static void OpEA (void)
1523  {
1524  	AddCycles(ONE_CYCLE);
1525  }
1526  
1527  /* PUSH Instructions ******************************************************* */
1528  
1529  #define PushW(w) \
1530  	S9xSetWord(w, Registers.S.W - 1, WRAP_BANK, WRITE_10); \
1531  	Registers.S.W -= 2;
1532  
1533  #define PushWE(w) \
1534  	Registers.SL--; \
1535  	S9xSetWord(w, Registers.S.W, WRAP_PAGE, WRITE_10); \
1536  	Registers.SL--;
1537  
1538  #define PushB(b) \
1539  	S9xSetByte(b, Registers.S.W--);
1540  
1541  #define PushBE(b) \
1542  	S9xSetByte(b, Registers.S.W); \
1543  	Registers.SL--;
1544  
1545  // PEA
1546  static void OpF4E0 (void)
1547  {
1548  	uint16	val = (uint16) Absolute(NONE);
1549  	PushW(val);
1550  	OpenBus = val & 0xff;
1551  }
1552  
1553  static void OpF4Slow (void)
1554  {
1555  	uint16	val = (uint16) AbsoluteSlow(NONE);
1556  	PushW(val);
1557  	OpenBus = val & 0xff;
1558  	if (CheckEmulation())
1559  		Registers.SH = 1;
1560  }
1561  
1562  // PEI
1563  static void OpD4E0 (void)
1564  {
1565  	uint16	val = (uint16) DirectIndirectE0(NONE);
1566  	PushW(val);
1567  	OpenBus = val & 0xff;
1568  }
1569  
1570  static void OpD4Slow (void)
1571  {
1572  	uint16	val = (uint16) DirectIndirectSlow(NONE);
1573  	PushW(val);
1574  	OpenBus = val & 0xff;
1575  	if (CheckEmulation())
1576  		Registers.SH = 1;
1577  }
1578  
1579  // PER
1580  static void Op62E0 (void)
1581  {
1582  	uint16	val = (uint16) RelativeLong(NONE);
1583  	PushW(val);
1584  	OpenBus = val & 0xff;
1585  }
1586  
1587  static void Op62Slow (void)
1588  {
1589  	uint16	val = (uint16) RelativeLongSlow(NONE);
1590  	PushW(val);
1591  	OpenBus = val & 0xff;
1592  	if (CheckEmulation())
1593  		Registers.SH = 1;
1594  }
1595  
1596  // PHA
1597  static void Op48E0M1 (void)
1598  {
1599  	AddCycles(ONE_CYCLE);
1600  	PushB(Registers.AL);
1601  	OpenBus = Registers.AL;
1602  }
1603  
1604  static void Op48E0M0 (void)
1605  {
1606  	AddCycles(ONE_CYCLE);
1607  	PushW(Registers.A.W);
1608  	OpenBus = Registers.AL;
1609  }
1610  
1611  static void Op48Slow (void)
1612  {
1613  	AddCycles(ONE_CYCLE);
1614  
1615  	if (CheckEmulation())
1616  	{
1617  		PushBE(Registers.AL);
1618  	}
1619  	else
1620  	if (CheckMemory())
1621  	{
1622  		PushB(Registers.AL);
1623  	}
1624  	else
1625  	{
1626  		PushW(Registers.A.W);
1627  	}
1628  
1629  	OpenBus = Registers.AL;
1630  }
1631  
1632  // PHB
1633  static void Op8BE0 (void)
1634  {
1635  	AddCycles(ONE_CYCLE);
1636  	PushB(Registers.DB);
1637  	OpenBus = Registers.DB;
1638  }
1639  
1640  static void Op8BSlow (void)
1641  {
1642  	AddCycles(ONE_CYCLE);
1643  
1644  	if (CheckEmulation())
1645  	{
1646  		PushBE(Registers.DB);
1647  	}
1648  	else
1649  	{
1650  		PushB(Registers.DB);
1651  	}
1652  
1653  	OpenBus = Registers.DB;
1654  }
1655  
1656  // PHD
1657  static void Op0BE0 (void)
1658  {
1659  	AddCycles(ONE_CYCLE);
1660  	PushW(Registers.D.W);
1661  	OpenBus = Registers.DL;
1662  }
1663  
1664  static void Op0BSlow (void)
1665  {
1666  	AddCycles(ONE_CYCLE);
1667  	PushW(Registers.D.W);
1668  	OpenBus = Registers.DL;
1669  	if (CheckEmulation())
1670  		Registers.SH = 1;
1671  }
1672  
1673  // PHK
1674  static void Op4BE0 (void)
1675  {
1676  	AddCycles(ONE_CYCLE);
1677  	PushB(Registers.PB);
1678  	OpenBus = Registers.PB;
1679  }
1680  
1681  static void Op4BSlow (void)
1682  {
1683  	AddCycles(ONE_CYCLE);
1684  
1685  	if (CheckEmulation())
1686  	{
1687  		PushBE(Registers.PB);
1688  	}
1689  	else
1690  	{
1691  		PushB(Registers.PB);
1692  	}
1693  
1694  	OpenBus = Registers.PB;
1695  }
1696  
1697  // PHP
1698  static void Op08E0 (void)
1699  {
1700  	AddCycles(ONE_CYCLE);
1701  	PushB(Registers.PL);
1702  	OpenBus = Registers.PL;
1703  }
1704  
1705  static void Op08Slow (void)
1706  {
1707  	AddCycles(ONE_CYCLE);
1708  
1709  	if (CheckEmulation())
1710  	{
1711  		PushBE(Registers.PL);
1712  	}
1713  	else
1714  	{
1715  		PushB(Registers.PL);
1716  	}
1717  
1718  	OpenBus = Registers.PL;
1719  }
1720  
1721  // PHX
1722  static void OpDAE0X1 (void)
1723  {
1724  	AddCycles(ONE_CYCLE);
1725  	PushB(Registers.XL);
1726  	OpenBus = Registers.XL;
1727  }
1728  
1729  static void OpDAE0X0 (void)
1730  {
1731  	AddCycles(ONE_CYCLE);
1732  	PushW(Registers.X.W);
1733  	OpenBus = Registers.XL;
1734  }
1735  
1736  static void OpDASlow (void)
1737  {
1738  	AddCycles(ONE_CYCLE);
1739  
1740  	if (CheckEmulation())
1741  	{
1742  		PushBE(Registers.XL);
1743  	}
1744  	else
1745  	if (CheckIndex())
1746  	{
1747  		PushB(Registers.XL);
1748  	}
1749  	else
1750  	{
1751  		PushW(Registers.X.W);
1752  	}
1753  
1754  	OpenBus = Registers.XL;
1755  }
1756  
1757  // PHY
1758  static void Op5AE0X1 (void)
1759  {
1760  	AddCycles(ONE_CYCLE);
1761  	PushB(Registers.YL);
1762  	OpenBus = Registers.YL;
1763  }
1764  
1765  static void Op5AE0X0 (void)
1766  {
1767  	AddCycles(ONE_CYCLE);
1768  	PushW(Registers.Y.W);
1769  	OpenBus = Registers.YL;
1770  }
1771  
1772  static void Op5ASlow (void)
1773  {
1774  	AddCycles(ONE_CYCLE);
1775  
1776  	if (CheckEmulation())
1777  	{
1778  		PushBE(Registers.YL);
1779  	}
1780  	else
1781  	if (CheckIndex())
1782  	{
1783  		PushB(Registers.YL);
1784  	}
1785  	else
1786  	{
1787  		PushW(Registers.Y.W);
1788  	}
1789  
1790  	OpenBus = Registers.YL;
1791  }
1792  
1793  /* PULL Instructions ******************************************************* */
1794  
1795  #define PullW(w) \
1796  	w = S9xGetWord(Registers.S.W + 1, WRAP_BANK); \
1797  	Registers.S.W += 2;
1798  
1799  #define PullWE(w) \
1800  	Registers.SL++; \
1801  	w = S9xGetWord(Registers.S.W, WRAP_PAGE); \
1802  	Registers.SL++;
1803  
1804  #define PullB(b) \
1805  	b = S9xGetByte(++Registers.S.W);
1806  
1807  #define PullBE(b) \
1808  	Registers.SL++; \
1809  	b = S9xGetByte(Registers.S.W);
1810  
1811  // PLA
1812  static void Op68E0M1 (void)
1813  {
1814  	AddCycles(TWO_CYCLES);
1815  	PullB(Registers.AL);
1816  	SetZN8(Registers.AL);
1817  	OpenBus = Registers.AL;
1818  }
1819  
1820  static void Op68E0M0 (void)
1821  {
1822  	AddCycles(TWO_CYCLES);
1823  	PullW(Registers.A.W);
1824  	SetZN16(Registers.A.W);
1825  	OpenBus = Registers.AH;
1826  }
1827  
1828  static void Op68Slow (void)
1829  {
1830  	AddCycles(TWO_CYCLES);
1831  
1832  	if (CheckEmulation())
1833  	{
1834  		PullBE(Registers.AL);
1835  		SetZN8(Registers.AL);
1836  		OpenBus = Registers.AL;
1837  	}
1838  	else
1839  	if (CheckMemory())
1840  	{
1841  		PullB(Registers.AL);
1842  		SetZN8(Registers.AL);
1843  		OpenBus = Registers.AL;
1844  	}
1845  	else
1846  	{
1847  		PullW(Registers.A.W);
1848  		SetZN16(Registers.A.W);
1849  		OpenBus = Registers.AH;
1850  	}
1851  }
1852  
1853  // PLB
1854  static void OpABE0 (void)
1855  {
1856  	AddCycles(TWO_CYCLES);
1857  	PullB(Registers.DB);
1858  	SetZN8(Registers.DB);
1859  	ICPU.ShiftedDB = Registers.DB << 16;
1860  	OpenBus = Registers.DB;
1861  }
1862  
1863  static void OpABSlow (void)
1864  {
1865  	AddCycles(TWO_CYCLES);
1866  
1867  	if (CheckEmulation())
1868  	{
1869  		PullBE(Registers.DB);
1870  	}
1871  	else
1872  	{
1873  		PullB(Registers.DB);
1874  	}
1875  
1876  	SetZN8(Registers.DB);
1877  	ICPU.ShiftedDB = Registers.DB << 16;
1878  	OpenBus = Registers.DB;
1879  }
1880  
1881  // PLD
1882  static void Op2BE0 (void)
1883  {
1884  	AddCycles(TWO_CYCLES);
1885  	PullW(Registers.D.W);
1886  	SetZN16(Registers.D.W);
1887  	OpenBus = Registers.DH;
1888  }
1889  
1890  static void Op2BSlow (void)
1891  {
1892  	AddCycles(TWO_CYCLES);
1893  	PullW(Registers.D.W);
1894  	SetZN16(Registers.D.W);
1895  	OpenBus = Registers.DH;
1896  	if (CheckEmulation())
1897  		Registers.SH = 1;
1898  }
1899  
1900  // PLP
1901  static void Op28E0 (void)
1902  {
1903  	AddCycles(TWO_CYCLES);
1904  	PullB(Registers.PL);
1905  	OpenBus = Registers.PL;
1906  
1907  	if (CheckIndex())
1908  	{
1909  		Registers.XH = 0;
1910  		Registers.YH = 0;
1911  	}
1912  
1913  	S9xFixCycles();
1914  }
1915  
1916  static void Op28Slow (void)
1917  {
1918  	AddCycles(TWO_CYCLES);
1919  
1920  	if (CheckEmulation())
1921  	{
1922  		PullBE(Registers.PL);
1923  		OpenBus = Registers.PL;
1924  		SetFlags(MemoryFlag | IndexFlag);
1925  	}
1926  	else
1927  	{
1928  		PullB(Registers.PL);
1929  		OpenBus = Registers.PL;
1930  	}
1931  
1932  
1933  	if (CheckIndex())
1934  	{
1935  		Registers.XH = 0;
1936  		Registers.YH = 0;
1937  	}
1938  
1939  	S9xFixCycles();
1940  }
1941  
1942  // PLX
1943  static void OpFAE0X1 (void)
1944  {
1945  	AddCycles(TWO_CYCLES);
1946  	PullB(Registers.XL);
1947  	SetZN8(Registers.XL);
1948  	OpenBus = Registers.XL;
1949  }
1950  
1951  static void OpFAE0X0 (void)
1952  {
1953  	AddCycles(TWO_CYCLES);
1954  	PullW(Registers.X.W);
1955  	SetZN16(Registers.X.W);
1956  	OpenBus = Registers.XH;
1957  }
1958  
1959  static void OpFASlow (void)
1960  {
1961  	AddCycles(TWO_CYCLES);
1962  
1963  	if (CheckEmulation())
1964  	{
1965  		PullBE(Registers.XL);
1966  		SetZN8(Registers.XL);
1967  		OpenBus = Registers.XL;
1968  	}
1969  	else
1970  	if (CheckIndex())
1971  	{
1972  		PullB(Registers.XL);
1973  		SetZN8(Registers.XL);
1974  		OpenBus = Registers.XL;
1975  	}
1976  	else
1977  	{
1978  		PullW(Registers.X.W);
1979  		SetZN16(Registers.X.W);
1980  		OpenBus = Registers.XH;
1981  	}
1982  }
1983  
1984  // PLY
1985  static void Op7AE0X1 (void)
1986  {
1987  	AddCycles(TWO_CYCLES);
1988  	PullB(Registers.YL);
1989  	SetZN8(Registers.YL);
1990  	OpenBus = Registers.YL;
1991  }
1992  
1993  static void Op7AE0X0 (void)
1994  {
1995  	AddCycles(TWO_CYCLES);
1996  	PullW(Registers.Y.W);
1997  	SetZN16(Registers.Y.W);
1998  	OpenBus = Registers.YH;
1999  }
2000  
2001  static void Op7ASlow (void)
2002  {
2003  	AddCycles(TWO_CYCLES);
2004  
2005  	if (CheckEmulation())
2006  	{
2007  		PullBE(Registers.YL);
2008  		SetZN8(Registers.YL);
2009  		OpenBus = Registers.YL;
2010  	}
2011  	else
2012  	if (CheckIndex())
2013  	{
2014  		PullB(Registers.YL);
2015  		SetZN8(Registers.YL);
2016  		OpenBus = Registers.YL;
2017  	}
2018  	else
2019  	{
2020  		PullW(Registers.Y.W);
2021  		SetZN16(Registers.Y.W);
2022  		OpenBus = Registers.YH;
2023  	}
2024  }
2025  
2026  /* Transfer Instructions *************************************************** */
2027  
2028  // TAX
2029  static void OpAAX1 (void)
2030  {
2031  	AddCycles(ONE_CYCLE);
2032  	Registers.XL = Registers.AL;
2033  	SetZN8(Registers.XL);
2034  }
2035  
2036  static void OpAAX0 (void)
2037  {
2038  	AddCycles(ONE_CYCLE);
2039  	Registers.X.W = Registers.A.W;
2040  	SetZN16(Registers.X.W);
2041  }
2042  
2043  static void OpAASlow (void)
2044  {
2045  	AddCycles(ONE_CYCLE);
2046  
2047  	if (CheckIndex())
2048  	{
2049  		Registers.XL = Registers.AL;
2050  		SetZN8(Registers.XL);
2051  	}
2052  	else
2053  	{
2054  		Registers.X.W = Registers.A.W;
2055  		SetZN16(Registers.X.W);
2056  	}
2057  }
2058  
2059  // TAY
2060  static void OpA8X1 (void)
2061  {
2062  	AddCycles(ONE_CYCLE);
2063  	Registers.YL = Registers.AL;
2064  	SetZN8(Registers.YL);
2065  }
2066  
2067  static void OpA8X0 (void)
2068  {
2069  	AddCycles(ONE_CYCLE);
2070  	Registers.Y.W = Registers.A.W;
2071  	SetZN16(Registers.Y.W);
2072  }
2073  
2074  static void OpA8Slow (void)
2075  {
2076  	AddCycles(ONE_CYCLE);
2077  
2078  	if (CheckIndex())
2079  	{
2080  		Registers.YL = Registers.AL;
2081  		SetZN8(Registers.YL);
2082  	}
2083  	else
2084  	{
2085  		Registers.Y.W = Registers.A.W;
2086  		SetZN16(Registers.Y.W);
2087  	}
2088  }
2089  
2090  // TCD
2091  static void Op5B (void)
2092  {
2093  	AddCycles(ONE_CYCLE);
2094  	Registers.D.W = Registers.A.W;
2095  	SetZN16(Registers.D.W);
2096  }
2097  
2098  // TCS
2099  static void Op1B (void)
2100  {
2101  	AddCycles(ONE_CYCLE);
2102  	Registers.S.W = Registers.A.W;
2103  	if (CheckEmulation())
2104  		Registers.SH = 1;
2105  }
2106  
2107  // TDC
2108  static void Op7B (void)
2109  {
2110  	AddCycles(ONE_CYCLE);
2111  	Registers.A.W = Registers.D.W;
2112  	SetZN16(Registers.A.W);
2113  }
2114  
2115  // TSC
2116  static void Op3B (void)
2117  {
2118  	AddCycles(ONE_CYCLE);
2119  	Registers.A.W = Registers.S.W;
2120  	SetZN16(Registers.A.W);
2121  }
2122  
2123  // TSX
2124  static void OpBAX1 (void)
2125  {
2126  	AddCycles(ONE_CYCLE);
2127  	Registers.XL = Registers.SL;
2128  	SetZN8(Registers.XL);
2129  }
2130  
2131  static void OpBAX0 (void)
2132  {
2133  	AddCycles(ONE_CYCLE);
2134  	Registers.X.W = Registers.S.W;
2135  	SetZN16(Registers.X.W);
2136  }
2137  
2138  static void OpBASlow (void)
2139  {
2140  	AddCycles(ONE_CYCLE);
2141  
2142  	if (CheckIndex())
2143  	{
2144  		Registers.XL = Registers.SL;
2145  		SetZN8(Registers.XL);
2146  	}
2147  	else
2148  	{
2149  		Registers.X.W = Registers.S.W;
2150  		SetZN16(Registers.X.W);
2151  	}
2152  }
2153  
2154  // TXA
2155  static void Op8AM1 (void)
2156  {
2157  	AddCycles(ONE_CYCLE);
2158  	Registers.AL = Registers.XL;
2159  	SetZN8(Registers.AL);
2160  }
2161  
2162  static void Op8AM0 (void)
2163  {
2164  	AddCycles(ONE_CYCLE);
2165  	Registers.A.W = Registers.X.W;
2166  	SetZN16(Registers.A.W);
2167  }
2168  
2169  static void Op8ASlow (void)
2170  {
2171  	AddCycles(ONE_CYCLE);
2172  
2173  	if (CheckMemory())
2174  	{
2175  		Registers.AL = Registers.XL;
2176  		SetZN8(Registers.AL);
2177  	}
2178  	else
2179  	{
2180  		Registers.A.W = Registers.X.W;
2181  		SetZN16(Registers.A.W);
2182  	}
2183  }
2184  
2185  // TXS
2186  static void Op9A (void)
2187  {
2188  	AddCycles(ONE_CYCLE);
2189  	Registers.S.W = Registers.X.W;
2190  	if (CheckEmulation())
2191  		Registers.SH = 1;
2192  }
2193  
2194  // TXY
2195  static void Op9BX1 (void)
2196  {
2197  	AddCycles(ONE_CYCLE);
2198  	Registers.YL = Registers.XL;
2199  	SetZN8(Registers.YL);
2200  }
2201  
2202  static void Op9BX0 (void)
2203  {
2204  	AddCycles(ONE_CYCLE);
2205  	Registers.Y.W = Registers.X.W;
2206  	SetZN16(Registers.Y.W);
2207  }
2208  
2209  static void Op9BSlow (void)
2210  {
2211  	AddCycles(ONE_CYCLE);
2212  
2213  	if (CheckIndex())
2214  	{
2215  		Registers.YL = Registers.XL;
2216  		SetZN8(Registers.YL);
2217  	}
2218  	else
2219  	{
2220  		Registers.Y.W = Registers.X.W;
2221  		SetZN16(Registers.Y.W);
2222  	}
2223  }
2224  
2225  // TYA
2226  static void Op98M1 (void)
2227  {
2228  	AddCycles(ONE_CYCLE);
2229  	Registers.AL = Registers.YL;
2230  	SetZN8(Registers.AL);
2231  }
2232  
2233  static void Op98M0 (void)
2234  {
2235  	AddCycles(ONE_CYCLE);
2236  	Registers.A.W = Registers.Y.W;
2237  	SetZN16(Registers.A.W);
2238  }
2239  
2240  static void Op98Slow (void)
2241  {
2242  	AddCycles(ONE_CYCLE);
2243  
2244  	if (CheckMemory())
2245  	{
2246  		Registers.AL = Registers.YL;
2247  		SetZN8(Registers.AL);
2248  	}
2249  	else
2250  	{
2251  		Registers.A.W = Registers.Y.W;
2252  		SetZN16(Registers.A.W);
2253  	}
2254  }
2255  
2256  // TYX
2257  static void OpBBX1 (void)
2258  {
2259  	AddCycles(ONE_CYCLE);
2260  	Registers.XL = Registers.YL;
2261  	SetZN8(Registers.XL);
2262  }
2263  
2264  static void OpBBX0 (void)
2265  {
2266  	AddCycles(ONE_CYCLE);
2267  	Registers.X.W = Registers.Y.W;
2268  	SetZN16(Registers.X.W);
2269  }
2270  
2271  static void OpBBSlow (void)
2272  {
2273  	AddCycles(ONE_CYCLE);
2274  
2275  	if (CheckIndex())
2276  	{
2277  		Registers.XL = Registers.YL;
2278  		SetZN8(Registers.XL);
2279  	}
2280  	else
2281  	{
2282  		Registers.X.W = Registers.Y.W;
2283  		SetZN16(Registers.X.W);
2284  	}
2285  }
2286  
2287  /* XCE ********************************************************************* */
2288  
2289  static void OpFB (void)
2290  {
2291  	AddCycles(ONE_CYCLE);
2292  
2293  	uint8	A1 = CheckCarry() ? 1 : 0;
2294  	uint8	A2 = Registers.PH;
2295  
2296  	SetCarryX(A2 & 1);
2297  	Registers.PH = A1;
2298  
2299  	if (CheckEmulation())
2300  	{
2301  		SetFlags(MemoryFlag | IndexFlag);
2302  		Registers.SH = 1;
2303  	}
2304  
2305  	if (CheckIndex())
2306  	{
2307  		Registers.XH = 0;
2308  		Registers.YH = 0;
2309  	}
2310  
2311  	S9xFixCycles();
2312  }
2313  
2314  /* BRK ********************************************************************* */
2315  
2316  static void Op00 (void)
2317  {
2318  #ifdef DEBUGGER
2319  	if (CPU.Flags & TRACE_FLAG)
2320  		S9xTraceMessage("*** BRK");
2321  #endif
2322  
2323  	AddCycles(CPU.MemSpeed);
2324  
2325  	uint16	addr;
2326  
2327  	if (!CheckEmulation())
2328  	{
2329  		PushB(Registers.PB);
2330  		PushW(Registers.PCw + 1);
2331  		PushB(Registers.PL);
2332  		OpenBus = Registers.PL;
2333  		ClearDecimal();
2334  		SetIRQ();
2335  
2336  		addr = S9xGetWord(0xFFE6);
2337  	}
2338  	else
2339  	{
2340  		PushWE(Registers.PCw + 1);
2341  		PushBE(Registers.PL);
2342  		OpenBus = Registers.PL;
2343  		ClearDecimal();
2344  		SetIRQ();
2345  
2346  		addr = S9xGetWord(0xFFFE);
2347  	}
2348  
2349  	S9xSetPCBase(addr);
2350  	OpenBus = addr >> 8;
2351  }
2352  
2353  /* IRQ ********************************************************************* */
2354  
2355  static void S9xOpcode_IRQ (void)
2356  {
2357  #ifdef DEBUGGER
2358  	if (CPU.Flags & TRACE_FLAG)
2359  		S9xTraceMessage("*** IRQ");
2360  #endif
2361  
2362  	// IRQ and NMI do an opcode fetch as their first "IO" cycle.
2363  	AddCycles(CPU.MemSpeed + ONE_CYCLE);
2364  
2365  	if (!CheckEmulation())
2366  	{
2367  		PushB(Registers.PB);
2368  		PushW(Registers.PCw);
2369  		PushB(Registers.PL);
2370  		OpenBus = Registers.PL;
2371  		ClearDecimal();
2372  		SetIRQ();
2373  
2374  		uint16	addr = S9xGetWord(0xFFEE);
2375  		OpenBus = addr >> 8;
2376  		S9xSetPCBase(addr);
2377  	}
2378  	else
2379  	{
2380  		PushWE(Registers.PCw);
2381  		PushBE(Registers.PL);
2382  		OpenBus = Registers.PL;
2383  		ClearDecimal();
2384  		SetIRQ();
2385  
2386  		uint16	addr = S9xGetWord(0xFFFE);
2387  		OpenBus = addr >> 8;
2388  		S9xSetPCBase(addr);
2389  	}
2390  }
2391  
2392  /* NMI ********************************************************************* */
2393  
2394  static void S9xOpcode_NMI (void)
2395  {
2396  #ifdef DEBUGGER
2397  	if (CPU.Flags & TRACE_FLAG)
2398  		S9xTraceMessage("*** NMI");
2399  #endif
2400  
2401  	// IRQ and NMI do an opcode fetch as their first "IO" cycle.
2402  	AddCycles(CPU.MemSpeed + ONE_CYCLE);
2403  
2404  	if (!CheckEmulation())
2405  	{
2406  		PushB(Registers.PB);
2407  		PushW(Registers.PCw);
2408  		PushB(Registers.PL);
2409  		OpenBus = Registers.PL;
2410  		ClearDecimal();
2411  		SetIRQ();
2412  
2413  		uint16	addr = S9xGetWord(0xFFEA);
2414  		OpenBus = addr >> 8;
2415  		S9xSetPCBase(addr);
2416  	}
2417  	else
2418  	{
2419  		PushWE(Registers.PCw);
2420  		PushBE(Registers.PL);
2421  		OpenBus = Registers.PL;
2422  		ClearDecimal();
2423  		SetIRQ();
2424  
2425  		uint16	addr = S9xGetWord(0xFFFA);
2426  		OpenBus = addr >> 8;
2427  		S9xSetPCBase(addr);
2428  	}
2429  }
2430  
2431  /* COP ********************************************************************* */
2432  
2433  static void Op02 (void)
2434  {
2435  #ifdef DEBUGGER
2436  	if (CPU.Flags & TRACE_FLAG)
2437  		S9xTraceMessage("*** COP");
2438  #endif
2439  
2440  	AddCycles(CPU.MemSpeed);
2441  
2442  	uint16	addr;
2443  
2444  	if (!CheckEmulation())
2445  	{
2446  		PushB(Registers.PB);
2447  		PushW(Registers.PCw + 1);
2448  		PushB(Registers.PL);
2449  		OpenBus = Registers.PL;
2450  		ClearDecimal();
2451  		SetIRQ();
2452  
2453  		addr = S9xGetWord(0xFFE4);
2454  	}
2455  	else
2456  	{
2457  		PushWE(Registers.PCw + 1);
2458  		PushBE(Registers.PL);
2459  		OpenBus = Registers.PL;
2460  		ClearDecimal();
2461  		SetIRQ();
2462  
2463  		addr = S9xGetWord(0xFFF4);
2464  	}
2465  
2466  	S9xSetPCBase(addr);
2467  	OpenBus = addr >> 8;
2468  }
2469  
2470  /* JML ********************************************************************* */
2471  
2472  static void OpDC (void)
2473  {
2474  	S9xSetPCBase(AbsoluteIndirectLong(JUMP));
2475  }
2476  
2477  static void OpDCSlow (void)
2478  {
2479  	S9xSetPCBase(AbsoluteIndirectLongSlow(JUMP));
2480  }
2481  
2482  static void Op5C (void)
2483  {
2484  	S9xSetPCBase(AbsoluteLong(JUMP));
2485  }
2486  
2487  static void Op5CSlow (void)
2488  {
2489  	S9xSetPCBase(AbsoluteLongSlow(JUMP));
2490  }
2491  
2492  /* JMP ********************************************************************* */
2493  
2494  static void Op4C (void)
2495  {
2496  	S9xSetPCBase(ICPU.ShiftedPB + ((uint16) Absolute(JUMP)));
2497  }
2498  
2499  static void Op4CSlow (void)
2500  {
2501  	S9xSetPCBase(ICPU.ShiftedPB + ((uint16) AbsoluteSlow(JUMP)));
2502  }
2503  
2504  static void Op6C (void)
2505  {
2506  	S9xSetPCBase(ICPU.ShiftedPB + ((uint16) AbsoluteIndirect(JUMP)));
2507  }
2508  
2509  static void Op6CSlow (void)
2510  {
2511  	S9xSetPCBase(ICPU.ShiftedPB + ((uint16) AbsoluteIndirectSlow(JUMP)));
2512  }
2513  
2514  static void Op7C (void)
2515  {
2516  	S9xSetPCBase(ICPU.ShiftedPB + ((uint16) AbsoluteIndexedIndirect(JUMP)));
2517  }
2518  
2519  static void Op7CSlow (void)
2520  {
2521  	S9xSetPCBase(ICPU.ShiftedPB + ((uint16) AbsoluteIndexedIndirectSlow(JUMP)));
2522  }
2523  
2524  /* JSL/RTL ***************************************************************** */
2525  
2526  static void Op22E0 (void)
2527  {
2528  	uint32	addr = AbsoluteLong(JSR);
2529  	PushB(Registers.PB);
2530  	PushW(Registers.PCw - 1);
2531  	S9xSetPCBase(addr);
2532  }
2533  
2534  static void Op22Slow (void)
2535  {
2536  	uint32	addr = AbsoluteLongSlow(JSR);
2537  	PushB(Registers.PB);
2538  	PushW(Registers.PCw - 1);
2539  	if (CheckEmulation())
2540  		Registers.SH = 1;
2541  	S9xSetPCBase(addr);
2542  }
2543  
2544  static void Op6BE0 (void)
2545  {
2546  	AddCycles(TWO_CYCLES);
2547  	PullW(Registers.PCw);
2548  	PullB(Registers.PB);
2549  	Registers.PCw++;
2550  	S9xSetPCBase(Registers.PBPC);
2551  }
2552  
2553  static void Op6BSlow (void)
2554  {
2555  	AddCycles(TWO_CYCLES);
2556  	PullW(Registers.PCw);
2557  	PullB(Registers.PB);
2558  	if (CheckEmulation())
2559  		Registers.SH = 1;
2560  	Registers.PCw++;
2561  	S9xSetPCBase(Registers.PBPC);
2562  }
2563  
2564  /* JSR/RTS ***************************************************************** */
2565  
2566  static void Op20E0 (void)
2567  {
2568  	uint16	addr = Absolute(JSR);
2569  	AddCycles(ONE_CYCLE);
2570  	PushW(Registers.PCw - 1);
2571  	S9xSetPCBase(ICPU.ShiftedPB + addr);
2572  }
2573  
2574  static void Op20Slow (void)
2575  {
2576  	uint16	addr = AbsoluteSlow(JSR);
2577  
2578  	AddCycles(ONE_CYCLE);
2579  
2580  	if (CheckEmulation())
2581  	{
2582  		PushWE(Registers.PCw - 1);
2583  	}
2584  	else
2585  	{
2586  		PushW(Registers.PCw - 1);
2587  	}
2588  
2589  	S9xSetPCBase(ICPU.ShiftedPB + addr);
2590  }
2591  
2592  static void OpFCE0 (void)
2593  {
2594  	uint16	addr = AbsoluteIndexedIndirect(JSR);
2595  	PushW(Registers.PCw - 1);
2596  	S9xSetPCBase(ICPU.ShiftedPB + addr);
2597  }
2598  
2599  static void OpFCSlow (void)
2600  {
2601  	uint16	addr = AbsoluteIndexedIndirectSlow(JSR);
2602  	PushW(Registers.PCw - 1);
2603  	if (CheckEmulation())
2604  		Registers.SH = 1;
2605  	S9xSetPCBase(ICPU.ShiftedPB + addr);
2606  }
2607  
2608  static void Op60E0 (void)
2609  {
2610  	AddCycles(TWO_CYCLES);
2611  	PullW(Registers.PCw);
2612  	AddCycles(ONE_CYCLE);
2613  	Registers.PCw++;
2614  	S9xSetPCBase(Registers.PBPC);
2615  }
2616  
2617  static void Op60Slow (void)
2618  {
2619  	AddCycles(TWO_CYCLES);
2620  
2621  	if (CheckEmulation())
2622  	{
2623  		PullWE(Registers.PCw);
2624  	}
2625  	else
2626  	{
2627  		PullW(Registers.PCw);
2628  	}
2629  
2630  	AddCycles(ONE_CYCLE);
2631  	Registers.PCw++;
2632  	S9xSetPCBase(Registers.PBPC);
2633  }
2634  
2635  /* MVN/MVP ***************************************************************** */
2636  
2637  static void Op54X1 (void)
2638  {
2639  	uint32	SrcBank;
2640  
2641  	Registers.DB = Immediate8(NONE);
2642  	ICPU.ShiftedDB = Registers.DB << 16;
2643  	OpenBus = SrcBank = Immediate8(NONE);
2644  
2645  	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
2646  
2647  	Registers.XL++;
2648  	Registers.YL++;
2649  	Registers.A.W--;
2650  	if (Registers.A.W != 0xffff)
2651  		Registers.PCw -= 3;
2652  
2653  	AddCycles(TWO_CYCLES);
2654  }
2655  
2656  static void Op54X0 (void)
2657  {
2658  	uint32	SrcBank;
2659  
2660  	Registers.DB = Immediate8(NONE);
2661  	ICPU.ShiftedDB = Registers.DB << 16;
2662  	OpenBus = SrcBank = Immediate8(NONE);
2663  
2664  	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
2665  
2666  	Registers.X.W++;
2667  	Registers.Y.W++;
2668  	Registers.A.W--;
2669  	if (Registers.A.W != 0xffff)
2670  		Registers.PCw -= 3;
2671  
2672  	AddCycles(TWO_CYCLES);
2673  }
2674  
2675  static void Op54Slow (void)
2676  {
2677  	uint32	SrcBank;
2678  
2679  	OpenBus = Registers.DB = Immediate8Slow(NONE);
2680  	ICPU.ShiftedDB = Registers.DB << 16;
2681  	OpenBus = SrcBank = Immediate8Slow(NONE);
2682  
2683  	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
2684  
2685  	if (CheckIndex())
2686  	{
2687  		Registers.XL++;
2688  		Registers.YL++;
2689  	}
2690  	else
2691  	{
2692  		Registers.X.W++;
2693  		Registers.Y.W++;
2694  	}
2695  
2696  	Registers.A.W--;
2697  	if (Registers.A.W != 0xffff)
2698  		Registers.PCw -= 3;
2699  
2700  	AddCycles(TWO_CYCLES);
2701  }
2702  
2703  static void Op44X1 (void)
2704  {
2705  	uint32	SrcBank;
2706  
2707  	Registers.DB = Immediate8(NONE);
2708  	ICPU.ShiftedDB = Registers.DB << 16;
2709  	OpenBus = SrcBank = Immediate8(NONE);
2710  
2711  	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
2712  
2713  	Registers.XL--;
2714  	Registers.YL--;
2715  	Registers.A.W--;
2716  	if (Registers.A.W != 0xffff)
2717  		Registers.PCw -= 3;
2718  
2719  	AddCycles(TWO_CYCLES);
2720  }
2721  
2722  static void Op44X0 (void)
2723  {
2724  	uint32	SrcBank;
2725  
2726  	Registers.DB = Immediate8(NONE);
2727  	ICPU.ShiftedDB = Registers.DB << 16;
2728  	OpenBus = SrcBank = Immediate8(NONE);
2729  
2730  	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
2731  
2732  	Registers.X.W--;
2733  	Registers.Y.W--;
2734  	Registers.A.W--;
2735  	if (Registers.A.W != 0xffff)
2736  		Registers.PCw -= 3;
2737  
2738  	AddCycles(TWO_CYCLES);
2739  }
2740  
2741  static void Op44Slow (void)
2742  {
2743  	uint32	SrcBank;
2744  
2745  	OpenBus = Registers.DB = Immediate8Slow(NONE);
2746  	ICPU.ShiftedDB = Registers.DB << 16;
2747  	OpenBus = SrcBank = Immediate8Slow(NONE);
2748  
2749  	S9xSetByte(OpenBus = S9xGetByte((SrcBank << 16) + Registers.X.W), ICPU.ShiftedDB + Registers.Y.W);
2750  
2751  	if (CheckIndex())
2752  	{
2753  		Registers.XL--;
2754  		Registers.YL--;
2755  	}
2756  	else
2757  	{
2758  		Registers.X.W--;
2759  		Registers.Y.W--;
2760  	}
2761  
2762  	Registers.A.W--;
2763  	if (Registers.A.W != 0xffff)
2764  		Registers.PCw -= 3;
2765  
2766  	AddCycles(TWO_CYCLES);
2767  }
2768  
2769  /* REP/SEP ***************************************************************** */
2770  
2771  static void OpC2 (void)
2772  {
2773  	uint8	Work8 = ~Immediate8(READ);
2774  	Registers.PL &= Work8;
2775  
2776  	AddCycles(ONE_CYCLE);
2777  
2778  	if (CheckEmulation())
2779  	{
2780  		SetFlags(MemoryFlag | IndexFlag);
2781  	}
2782  
2783  	if (CheckIndex())
2784  	{
2785  		Registers.XH = 0;
2786  		Registers.YH = 0;
2787  	}
2788  
2789  	S9xFixCycles();
2790  }
2791  
2792  static void OpC2Slow (void)
2793  {
2794  	uint8	Work8 = ~Immediate8Slow(READ);
2795  	Registers.PL &= Work8;
2796  
2797  	AddCycles(ONE_CYCLE);
2798  
2799  	if (CheckEmulation())
2800  	{
2801  		SetFlags(MemoryFlag | IndexFlag);
2802  	}
2803  
2804  	if (CheckIndex())
2805  	{
2806  		Registers.XH = 0;
2807  		Registers.YH = 0;
2808  	}
2809  
2810  	S9xFixCycles();
2811  }
2812  
2813  static void OpE2 (void)
2814  {
2815  	uint8	Work8 = Immediate8(READ);
2816  	Registers.PL |= Work8;
2817  
2818  	AddCycles(ONE_CYCLE);
2819  
2820  	if (CheckEmulation())
2821  	{
2822  		SetFlags(MemoryFlag | IndexFlag);
2823  	}
2824  
2825  	if (CheckIndex())
2826  	{
2827  		Registers.XH = 0;
2828  		Registers.YH = 0;
2829  	}
2830  
2831  	S9xFixCycles();
2832  }
2833  
2834  static void OpE2Slow (void)
2835  {
2836  	uint8	Work8 = Immediate8Slow(READ);
2837  	Registers.PL |= Work8;
2838  
2839  	AddCycles(ONE_CYCLE);
2840  
2841  	if (CheckEmulation())
2842  	{
2843  		SetFlags(MemoryFlag | IndexFlag);
2844  	}
2845  
2846  	if (CheckIndex())
2847  	{
2848  		Registers.XH = 0;
2849  		Registers.YH = 0;
2850  	}
2851  
2852  	S9xFixCycles();
2853  }
2854  
2855  /* XBA ********************************************************************* */
2856  
2857  static void OpEB (void)
2858  {
2859  	uint8	Work8 = Registers.AL;
2860  	Registers.AL = Registers.AH;
2861  	Registers.AH = Work8;
2862  	SetZN8(Registers.AL);
2863  	AddCycles(TWO_CYCLES);
2864  }
2865  
2866  /* RTI ********************************************************************* */
2867  
2868  static void Op40Slow (void)
2869  {
2870  	AddCycles(TWO_CYCLES);
2871  
2872  	if (!CheckEmulation())
2873  	{
2874  		PullB(Registers.PL);
2875  		PullW(Registers.PCw);
2876  		PullB(Registers.PB);
2877  		OpenBus = Registers.PB;
2878  		ICPU.ShiftedPB = Registers.PB << 16;
2879  	}
2880  	else
2881  	{
2882  		PullBE(Registers.PL);
2883  		PullWE(Registers.PCw);
2884  		OpenBus = Registers.PCh;
2885  		SetFlags(MemoryFlag | IndexFlag);
2886  	}
2887  
2888  	S9xSetPCBase(Registers.PBPC);
2889  
2890  	if (CheckIndex())
2891  	{
2892  		Registers.XH = 0;
2893  		Registers.YH = 0;
2894  	}
2895  
2896  	S9xFixCycles();
2897  }
2898  
2899  /* STP/WAI ***************************************************************** */
2900  
2901  // WAI
2902  static void OpCB (void)
2903  {
2904  	CPU.WaitingForInterrupt = TRUE;
2905  
2906  	Registers.PCw--;
2907  	AddCycles(ONE_CYCLE);
2908  }
2909  
2910  // STP
2911  static void OpDB (void)
2912  {
2913  	Registers.PCw--;
2914  	CPU.Flags |= DEBUG_MODE_FLAG | HALTED_FLAG;
2915  }
2916  
2917  /* WDM (Reserved S9xOpcode) ************************************************ */
2918  
2919  static void Op42 (void)
2920  {
2921  	// Snes9x used this opcode for debugging breakpoints
2922  	// We use it for game hacks (from hacks.h)
2923  
2924  	S9xGetWord(Registers.PBPC);
2925  	Registers.PCw++;
2926  
2927  	#if 0
2928  
2929  	uint32 op = Immediate8Slow(NONE);
2930  
2931  	printf("Op42: Requested 0x%02X\n", op);
2932  
2933  	(*S9xOpcodesSlow[op])();
2934  
2935  	switch (op & 0xF0)
2936  	{
2937      case 0x00: // ???
2938      	return;
2939      case 0x10: // BPL
2940      	return;
2941      case 0x20: // ???
2942      	return;
2943      case 0x30: // BMI
2944      	return;
2945      case 0x40: // ???
2946      	return;
2947      case 0x50: // BVC
2948      	return;
2949      case 0x60: // ???
2950      	return;
2951      case 0x70: // BVS
2952      	return;
2953      case 0x80: // BRA
2954      	return;
2955      case 0x90: // BCC
2956      	return;
2957      case 0xA0: // ???
2958      	return;
2959      case 0xB0: // BCS
2960      	return;
2961      case 0xC0: // ???
2962      	return;
2963      case 0xD0: // BNE
2964      	return;
2965      case 0xF0: // BEQ
2966      	return;
2967  	}
2968  
2969  	#endif
2970  }
2971  
2972  /* CPU-S9xOpcodes Definitions ************************************************/
2973  
2974  const S9xOpcode S9xOpcodesM0X0[256] =
2975  {
2976  	Op00,        Op01E0M0,    Op02,        Op03M0,      Op04M0,
2977  	Op05M0,      Op06M0,      Op07M0,      Op08E0,      Op09M0,
2978  	Op0AM0,      Op0BE0,      Op0CM0,      Op0DM0,      Op0EM0,
2979  	Op0FM0,      Op10E0,      Op11E0M0X0,  Op12E0M0,    Op13M0,
2980  	Op14M0,      Op15E0M0,    Op16E0M0,    Op17M0,      Op18,
2981  	Op19M0X0,    Op1AM0,      Op1B,        Op1CM0,      Op1DM0X0,
2982  	Op1EM0X0,    Op1FM0,      Op20E0,      Op21E0M0,    Op22E0,
2983  	Op23M0,      Op24M0,      Op25M0,      Op26M0,      Op27M0,
2984  	Op28E0,      Op29M0,      Op2AM0,      Op2BE0,      Op2CM0,
2985  	Op2DM0,      Op2EM0,      Op2FM0,      Op30E0,      Op31E0M0X0,
2986  	Op32E0M0,    Op33M0,      Op34E0M0,    Op35E0M0,    Op36E0M0,
2987  	Op37M0,      Op38,        Op39M0X0,    Op3AM0,      Op3B,
2988  	Op3CM0X0,    Op3DM0X0,    Op3EM0X0,    Op3FM0,      Op40Slow,
2989  	Op41E0M0,    Op42,        Op43M0,      Op44X0,      Op45M0,
2990  	Op46M0,      Op47M0,      Op48E0M0,    Op49M0,      Op4AM0,
2991  	Op4BE0,      Op4C,        Op4DM0,      Op4EM0,      Op4FM0,
2992  	Op50E0,      Op51E0M0X0,  Op52E0M0,    Op53M0,      Op54X0,
2993  	Op55E0M0,    Op56E0M0,    Op57M0,      Op58,        Op59M0X0,
2994  	Op5AE0X0,    Op5B,        Op5C,        Op5DM0X0,    Op5EM0X0,
2995  	Op5FM0,      Op60E0,      Op61E0M0,    Op62E0,      Op63M0,
2996  	Op64M0,      Op65M0,      Op66M0,      Op67M0,      Op68E0M0,
2997  	Op69M0,      Op6AM0,      Op6BE0,      Op6C,        Op6DM0,
2998  	Op6EM0,      Op6FM0,      Op70E0,      Op71E0M0X0,  Op72E0M0,
2999  	Op73M0,      Op74E0M0,    Op75E0M0,    Op76E0M0,    Op77M0,
3000  	Op78,        Op79M0X0,    Op7AE0X0,    Op7B,        Op7C,
3001  	Op7DM0X0,    Op7EM0X0,    Op7FM0,      Op80E0,      Op81E0M0,
3002  	Op82,        Op83M0,      Op84X0,      Op85M0,      Op86X0,
3003  	Op87M0,      Op88X0,      Op89M0,      Op8AM0,      Op8BE0,
3004  	Op8CX0,      Op8DM0,      Op8EX0,      Op8FM0,      Op90E0,
3005  	Op91E0M0X0,  Op92E0M0,    Op93M0,      Op94E0X0,    Op95E0M0,
3006  	Op96E0X0,    Op97M0,      Op98M0,      Op99M0X0,    Op9A,
3007  	Op9BX0,      Op9CM0,      Op9DM0X0,    Op9EM0X0,    Op9FM0,
3008  	OpA0X0,      OpA1E0M0,    OpA2X0,      OpA3M0,      OpA4X0,
3009  	OpA5M0,      OpA6X0,      OpA7M0,      OpA8X0,      OpA9M0,
3010  	OpAAX0,      OpABE0,      OpACX0,      OpADM0,      OpAEX0,
3011  	OpAFM0,      OpB0E0,      OpB1E0M0X0,  OpB2E0M0,    OpB3M0,
3012  	OpB4E0X0,    OpB5E0M0,    OpB6E0X0,    OpB7M0,      OpB8,
3013  	OpB9M0X0,    OpBAX0,      OpBBX0,      OpBCX0,      OpBDM0X0,
3014  	OpBEX0,      OpBFM0,      OpC0X0,      OpC1E0M0,    OpC2,
3015  	OpC3M0,      OpC4X0,      OpC5M0,      OpC6M0,      OpC7M0,
3016  	OpC8X0,      OpC9M0,      OpCAX0,      OpCB,        OpCCX0,
3017  	OpCDM0,      OpCEM0,      OpCFM0,      OpD0E0,      OpD1E0M0X0,
3018  	OpD2E0M0,    OpD3M0,      OpD4E0,      OpD5E0M0,    OpD6E0M0,
3019  	OpD7M0,      OpD8,        OpD9M0X0,    OpDAE0X0,    OpDB,
3020  	OpDC,        OpDDM0X0,    OpDEM0X0,    OpDFM0,      OpE0X0,
3021  	OpE1E0M0,    OpE2,        OpE3M0,      OpE4X0,      OpE5M0,
3022  	OpE6M0,      OpE7M0,      OpE8X0,      OpE9M0,      OpEA,
3023  	OpEB,        OpECX0,      OpEDM0,      OpEEM0,      OpEFM0,
3024  	OpF0E0,      OpF1E0M0X0,  OpF2E0M0,    OpF3M0,      OpF4E0,
3025  	OpF5E0M0,    OpF6E0M0,    OpF7M0,      OpF8,        OpF9M0X0,
3026  	OpFAE0X0,    OpFB,        OpFCE0,      OpFDM0X0,    OpFEM0X0,
3027  	OpFFM0
3028  };
3029  
3030  const S9xOpcode S9xOpcodesM0X1[256] =
3031  {
3032  	Op00,        Op01E0M0,    Op02,        Op03M0,      Op04M0,
3033  	Op05M0,      Op06M0,      Op07M0,      Op08E0,      Op09M0,
3034  	Op0AM0,      Op0BE0,      Op0CM0,      Op0DM0,      Op0EM0,
3035  	Op0FM0,      Op10E0,      Op11E0M0X1,  Op12E0M0,    Op13M0,
3036  	Op14M0,      Op15E0M0,    Op16E0M0,    Op17M0,      Op18,
3037  	Op19M0X1,    Op1AM0,      Op1B,        Op1CM0,      Op1DM0X1,
3038  	Op1EM0X1,    Op1FM0,      Op20E0,      Op21E0M0,    Op22E0,
3039  	Op23M0,      Op24M0,      Op25M0,      Op26M0,      Op27M0,
3040  	Op28E0,      Op29M0,      Op2AM0,      Op2BE0,      Op2CM0,
3041  	Op2DM0,      Op2EM0,      Op2FM0,      Op30E0,      Op31E0M0X1,
3042  	Op32E0M0,    Op33M0,      Op34E0M0,    Op35E0M0,    Op36E0M0,
3043  	Op37M0,      Op38,        Op39M0X1,    Op3AM0,      Op3B,
3044  	Op3CM0X1,    Op3DM0X1,    Op3EM0X1,    Op3FM0,      Op40Slow,
3045  	Op41E0M0,    Op42,        Op43M0,      Op44X1,      Op45M0,
3046  	Op46M0,      Op47M0,      Op48E0M0,    Op49M0,      Op4AM0,
3047  	Op4BE0,      Op4C,        Op4DM0,      Op4EM0,      Op4FM0,
3048  	Op50E0,      Op51E0M0X1,  Op52E0M0,    Op53M0,      Op54X1,
3049  	Op55E0M0,    Op56E0M0,    Op57M0,      Op58,        Op59M0X1,
3050  	Op5AE0X1,    Op5B,        Op5C,        Op5DM0X1,    Op5EM0X1,
3051  	Op5FM0,      Op60E0,      Op61E0M0,    Op62E0,      Op63M0,
3052  	Op64M0,      Op65M0,      Op66M0,      Op67M0,      Op68E0M0,
3053  	Op69M0,      Op6AM0,      Op6BE0,      Op6C,        Op6DM0,
3054  	Op6EM0,      Op6FM0,      Op70E0,      Op71E0M0X1,  Op72E0M0,
3055  	Op73M0,      Op74E0M0,    Op75E0M0,    Op76E0M0,    Op77M0,
3056  	Op78,        Op79M0X1,    Op7AE0X1,    Op7B,        Op7C,
3057  	Op7DM0X1,    Op7EM0X1,    Op7FM0,      Op80E0,      Op81E0M0,
3058  	Op82,        Op83M0,      Op84X1,      Op85M0,      Op86X1,
3059  	Op87M0,      Op88X1,      Op89M0,      Op8AM0,      Op8BE0,
3060  	Op8CX1,      Op8DM0,      Op8EX1,      Op8FM0,      Op90E0,
3061  	Op91E0M0X1,  Op92E0M0,    Op93M0,      Op94E0X1,    Op95E0M0,
3062  	Op96E0X1,    Op97M0,      Op98M0,      Op99M0X1,    Op9A,
3063  	Op9BX1,      Op9CM0,      Op9DM0X1,    Op9EM0X1,    Op9FM0,
3064  	OpA0X1,      OpA1E0M0,    OpA2X1,      OpA3M0,      OpA4X1,
3065  	OpA5M0,      OpA6X1,      OpA7M0,      OpA8X1,      OpA9M0,
3066  	OpAAX1,      OpABE0,      OpACX1,      OpADM0,      OpAEX1,
3067  	OpAFM0,      OpB0E0,      OpB1E0M0X1,  OpB2E0M0,    OpB3M0,
3068  	OpB4E0X1,    OpB5E0M0,    OpB6E0X1,    OpB7M0,      OpB8,
3069  	OpB9M0X1,    OpBAX1,      OpBBX1,      OpBCX1,      OpBDM0X1,
3070  	OpBEX1,      OpBFM0,      OpC0X1,      OpC1E0M0,    OpC2,
3071  	OpC3M0,      OpC4X1,      OpC5M0,      OpC6M0,      OpC7M0,
3072  	OpC8X1,      OpC9M0,      OpCAX1,      OpCB,        OpCCX1,
3073  	OpCDM0,      OpCEM0,      OpCFM0,      OpD0E0,      OpD1E0M0X1,
3074  	OpD2E0M0,    OpD3M0,      OpD4E0,      OpD5E0M0,    OpD6E0M0,
3075  	OpD7M0,      OpD8,        OpD9M0X1,    OpDAE0X1,    OpDB,
3076  	OpDC,        OpDDM0X1,    OpDEM0X1,    OpDFM0,      OpE0X1,
3077  	OpE1E0M0,    OpE2,        OpE3M0,      OpE4X1,      OpE5M0,
3078  	OpE6M0,      OpE7M0,      OpE8X1,      OpE9M0,      OpEA,
3079  	OpEB,        OpECX1,      OpEDM0,      OpEEM0,      OpEFM0,
3080  	OpF0E0,      OpF1E0M0X1,  OpF2E0M0,    OpF3M0,      OpF4E0,
3081  	OpF5E0M0,    OpF6E0M0,    OpF7M0,      OpF8,        OpF9M0X1,
3082  	OpFAE0X1,    OpFB,        OpFCE0,      OpFDM0X1,    OpFEM0X1,
3083  	OpFFM0
3084  };
3085  
3086  const S9xOpcode S9xOpcodesM1X0[256] =
3087  {
3088  	Op00,        Op01E0M1,    Op02,        Op03M1,      Op04M1,
3089  	Op05M1,      Op06M1,      Op07M1,      Op08E0,      Op09M1,
3090  	Op0AM1,      Op0BE0,      Op0CM1,      Op0DM1,      Op0EM1,
3091  	Op0FM1,      Op10E0,      Op11E0M1X0,  Op12E0M1,    Op13M1,
3092  	Op14M1,      Op15E0M1,    Op16E0M1,    Op17M1,      Op18,
3093  	Op19M1X0,    Op1AM1,      Op1B,        Op1CM1,      Op1DM1X0,
3094  	Op1EM1X0,    Op1FM1,      Op20E0,      Op21E0M1,    Op22E0,
3095  	Op23M1,      Op24M1,      Op25M1,      Op26M1,      Op27M1,
3096  	Op28E0,      Op29M1,      Op2AM1,      Op2BE0,      Op2CM1,
3097  	Op2DM1,      Op2EM1,      Op2FM1,      Op30E0,      Op31E0M1X0,
3098  	Op32E0M1,    Op33M1,      Op34E0M1,    Op35E0M1,    Op36E0M1,
3099  	Op37M1,      Op38,        Op39M1X0,    Op3AM1,      Op3B,
3100  	Op3CM1X0,    Op3DM1X0,    Op3EM1X0,    Op3FM1,      Op40Slow,
3101  	Op41E0M1,    Op42,        Op43M1,      Op44X0,      Op45M1,
3102  	Op46M1,      Op47M1,      Op48E0M1,    Op49M1,      Op4AM1,
3103  	Op4BE0,      Op4C,        Op4DM1,      Op4EM1,      Op4FM1,
3104  	Op50E0,      Op51E0M1X0,  Op52E0M1,    Op53M1,      Op54X0,
3105  	Op55E0M1,    Op56E0M1,    Op57M1,      Op58,        Op59M1X0,
3106  	Op5AE0X0,    Op5B,        Op5C,        Op5DM1X0,    Op5EM1X0,
3107  	Op5FM1,      Op60E0,      Op61E0M1,    Op62E0,      Op63M1,
3108  	Op64M1,      Op65M1,      Op66M1,      Op67M1,      Op68E0M1,
3109  	Op69M1,      Op6AM1,      Op6BE0,      Op6C,        Op6DM1,
3110  	Op6EM1,      Op6FM1,      Op70E0,      Op71E0M1X0,  Op72E0M1,
3111  	Op73M1,      Op74E0M1,    Op75E0M1,    Op76E0M1,    Op77M1,
3112  	Op78,        Op79M1X0,    Op7AE0X0,    Op7B,        Op7C,
3113  	Op7DM1X0,    Op7EM1X0,    Op7FM1,      Op80E0,      Op81E0M1,
3114  	Op82,        Op83M1,      Op84X0,      Op85M1,      Op86X0,
3115  	Op87M1,      Op88X0,      Op89M1,      Op8AM1,      Op8BE0,
3116  	Op8CX0,      Op8DM1,      Op8EX0,      Op8FM1,      Op90E0,
3117  	Op91E0M1X0,  Op92E0M1,    Op93M1,      Op94E0X0,    Op95E0M1,
3118  	Op96E0X0,    Op97M1,      Op98M1,      Op99M1X0,    Op9A,
3119  	Op9BX0,      Op9CM1,      Op9DM1X0,    Op9EM1X0,    Op9FM1,
3120  	OpA0X0,      OpA1E0M1,    OpA2X0,      OpA3M1,      OpA4X0,
3121  	OpA5M1,      OpA6X0,      OpA7M1,      OpA8X0,      OpA9M1,
3122  	OpAAX0,      OpABE0,      OpACX0,      OpADM1,      OpAEX0,
3123  	OpAFM1,      OpB0E0,      OpB1E0M1X0,  OpB2E0M1,    OpB3M1,
3124  	OpB4E0X0,    OpB5E0M1,    OpB6E0X0,    OpB7M1,      OpB8,
3125  	OpB9M1X0,    OpBAX0,      OpBBX0,      OpBCX0,      OpBDM1X0,
3126  	OpBEX0,      OpBFM1,      OpC0X0,      OpC1E0M1,    OpC2,
3127  	OpC3M1,      OpC4X0,      OpC5M1,      OpC6M1,      OpC7M1,
3128  	OpC8X0,      OpC9M1,      OpCAX0,      OpCB,        OpCCX0,
3129  	OpCDM1,      OpCEM1,      OpCFM1,      OpD0E0,      OpD1E0M1X0,
3130  	OpD2E0M1,    OpD3M1,      OpD4E0,      OpD5E0M1,    OpD6E0M1,
3131  	OpD7M1,      OpD8,        OpD9M1X0,    OpDAE0X0,    OpDB,
3132  	OpDC,        OpDDM1X0,    OpDEM1X0,    OpDFM1,      OpE0X0,
3133  	OpE1E0M1,    OpE2,        OpE3M1,      OpE4X0,      OpE5M1,
3134  	OpE6M1,      OpE7M1,      OpE8X0,      OpE9M1,      OpEA,
3135  	OpEB,        OpECX0,      OpEDM1,      OpEEM1,      OpEFM1,
3136  	OpF0E0,      OpF1E0M1X0,  OpF2E0M1,    OpF3M1,      OpF4E0,
3137  	OpF5E0M1,    OpF6E0M1,    OpF7M1,      OpF8,        OpF9M1X0,
3138  	OpFAE0X0,    OpFB,        OpFCE0,      OpFDM1X0,    OpFEM1X0,
3139  	OpFFM1
3140  };
3141  
3142  const S9xOpcode S9xOpcodesM1X1[256] =
3143  {
3144  	Op00,        Op01E0M1,    Op02,        Op03M1,      Op04M1,
3145  	Op05M1,      Op06M1,      Op07M1,      Op08E0,      Op09M1,
3146  	Op0AM1,      Op0BE0,      Op0CM1,      Op0DM1,      Op0EM1,
3147  	Op0FM1,      Op10E0,      Op11E0M1X1,  Op12E0M1,    Op13M1,
3148  	Op14M1,      Op15E0M1,    Op16E0M1,    Op17M1,      Op18,
3149  	Op19M1X1,    Op1AM1,      Op1B,        Op1CM1,      Op1DM1X1,
3150  	Op1EM1X1,    Op1FM1,      Op20E0,      Op21E0M1,    Op22E0,
3151  	Op23M1,      Op24M1,      Op25M1,      Op26M1,      Op27M1,
3152  	Op28E0,      Op29M1,      Op2AM1,      Op2BE0,      Op2CM1,
3153  	Op2DM1,      Op2EM1,      Op2FM1,      Op30E0,      Op31E0M1X1,
3154  	Op32E0M1,    Op33M1,      Op34E0M1,    Op35E0M1,    Op36E0M1,
3155  	Op37M1,      Op38,        Op39M1X1,    Op3AM1,      Op3B,
3156  	Op3CM1X1,    Op3DM1X1,    Op3EM1X1,    Op3FM1,      Op40Slow,
3157  	Op41E0M1,    Op42,        Op43M1,      Op44X1,      Op45M1,
3158  	Op46M1,      Op47M1,      Op48E0M1,    Op49M1,      Op4AM1,
3159  	Op4BE0,      Op4C,        Op4DM1,      Op4EM1,      Op4FM1,
3160  	Op50E0,      Op51E0M1X1,  Op52E0M1,    Op53M1,      Op54X1,
3161  	Op55E0M1,    Op56E0M1,    Op57M1,      Op58,        Op59M1X1,
3162  	Op5AE0X1,    Op5B,        Op5C,        Op5DM1X1,    Op5EM1X1,
3163  	Op5FM1,      Op60E0,      Op61E0M1,    Op62E0,      Op63M1,
3164  	Op64M1,      Op65M1,      Op66M1,      Op67M1,      Op68E0M1,
3165  	Op69M1,      Op6AM1,      Op6BE0,      Op6C,        Op6DM1,
3166  	Op6EM1,      Op6FM1,      Op70E0,      Op71E0M1X1,  Op72E0M1,
3167  	Op73M1,      Op74E0M1,    Op75E0M1,    Op76E0M1,    Op77M1,
3168  	Op78,        Op79M1X1,    Op7AE0X1,    Op7B,        Op7C,
3169  	Op7DM1X1,    Op7EM1X1,    Op7FM1,      Op80E0,      Op81E0M1,
3170  	Op82,        Op83M1,      Op84X1,      Op85M1,      Op86X1,
3171  	Op87M1,      Op88X1,      Op89M1,      Op8AM1,      Op8BE0,
3172  	Op8CX1,      Op8DM1,      Op8EX1,      Op8FM1,      Op90E0,
3173  	Op91E0M1X1,  Op92E0M1,    Op93M1,      Op94E0X1,    Op95E0M1,
3174  	Op96E0X1,    Op97M1,      Op98M1,      Op99M1X1,    Op9A,
3175  	Op9BX1,      Op9CM1,      Op9DM1X1,    Op9EM1X1,    Op9FM1,
3176  	OpA0X1,      OpA1E0M1,    OpA2X1,      OpA3M1,      OpA4X1,
3177  	OpA5M1,      OpA6X1,      OpA7M1,      OpA8X1,      OpA9M1,
3178  	OpAAX1,      OpABE0,      OpACX1,      OpADM1,      OpAEX1,
3179  	OpAFM1,      OpB0E0,      OpB1E0M1X1,  OpB2E0M1,    OpB3M1,
3180  	OpB4E0X1,    OpB5E0M1,    OpB6E0X1,    OpB7M1,      OpB8,
3181  	OpB9M1X1,    OpBAX1,      OpBBX1,      OpBCX1,      OpBDM1X1,
3182  	OpBEX1,      OpBFM1,      OpC0X1,      OpC1E0M1,    OpC2,
3183  	OpC3M1,      OpC4X1,      OpC5M1,      OpC6M1,      OpC7M1,
3184  	OpC8X1,      OpC9M1,      OpCAX1,      OpCB,        OpCCX1,
3185  	OpCDM1,      OpCEM1,      OpCFM1,      OpD0E0,      OpD1E0M1X1,
3186  	OpD2E0M1,    OpD3M1,      OpD4E0,      OpD5E0M1,    OpD6E0M1,
3187  	OpD7M1,      OpD8,        OpD9M1X1,    OpDAE0X1,    OpDB,
3188  	OpDC,        OpDDM1X1,    OpDEM1X1,    OpDFM1,      OpE0X1,
3189  	OpE1E0M1,    OpE2,        OpE3M1,      OpE4X1,      OpE5M1,
3190  	OpE6M1,      OpE7M1,      OpE8X1,      OpE9M1,      OpEA,
3191  	OpEB,        OpECX1,      OpEDM1,      OpEEM1,      OpEFM1,
3192  	OpF0E0,      OpF1E0M1X1,  OpF2E0M1,    OpF3M1,      OpF4E0,
3193  	OpF5E0M1,    OpF6E0M1,    OpF7M1,      OpF8,        OpF9M1X1,
3194  	OpFAE0X1,    OpFB,        OpFCE0,      OpFDM1X1,    OpFEM1X1,
3195  	OpFFM1
3196  };
3197  
3198  const S9xOpcode S9xOpcodesSlow[256] =
3199  {
3200  	Op00,        Op01Slow,    Op02,        Op03Slow,    Op04Slow,
3201  	Op05Slow,    Op06Slow,    Op07Slow,    Op08Slow,    Op09Slow,
3202  	Op0ASlow,    Op0BSlow,    Op0CSlow,    Op0DSlow,    Op0ESlow,
3203  	Op0FSlow,    Op10Slow,    Op11Slow,    Op12Slow,    Op13Slow,
3204  	Op14Slow,    Op15Slow,    Op16Slow,    Op17Slow,    Op18,
3205  	Op19Slow,    Op1ASlow,    Op1B,        Op1CSlow,    Op1DSlow,
3206  	Op1ESlow,    Op1FSlow,    Op20Slow,    Op21Slow,    Op22Slow,
3207  	Op23Slow,    Op24Slow,    Op25Slow,    Op26Slow,    Op27Slow,
3208  	Op28Slow,    Op29Slow,    Op2ASlow,    Op2BSlow,    Op2CSlow,
3209  	Op2DSlow,    Op2ESlow,    Op2FSlow,    Op30Slow,    Op31Slow,
3210  	Op32Slow,    Op33Slow,    Op34Slow,    Op35Slow,    Op36Slow,
3211  	Op37Slow,    Op38,        Op39Slow,    Op3ASlow,    Op3B,
3212  	Op3CSlow,    Op3DSlow,    Op3ESlow,    Op3FSlow,    Op40Slow,
3213  	Op41Slow,    Op42,        Op43Slow,    Op44Slow,    Op45Slow,
3214  	Op46Slow,    Op47Slow,    Op48Slow,    Op49Slow,    Op4ASlow,
3215  	Op4BSlow,    Op4CSlow,    Op4DSlow,    Op4ESlow,    Op4FSlow,
3216  	Op50Slow,    Op51Slow,    Op52Slow,    Op53Slow,    Op54Slow,
3217  	Op55Slow,    Op56Slow,    Op57Slow,    Op58,        Op59Slow,
3218  	Op5ASlow,    Op5B,        Op5CSlow,    Op5DSlow,    Op5ESlow,
3219  	Op5FSlow,    Op60Slow,    Op61Slow,    Op62Slow,    Op63Slow,
3220  	Op64Slow,    Op65Slow,    Op66Slow,    Op67Slow,    Op68Slow,
3221  	Op69Slow,    Op6ASlow,    Op6BSlow,    Op6CSlow,    Op6DSlow,
3222  	Op6ESlow,    Op6FSlow,    Op70Slow,    Op71Slow,    Op72Slow,
3223  	Op73Slow,    Op74Slow,    Op75Slow,    Op76Slow,    Op77Slow,
3224  	Op78,        Op79Slow,    Op7ASlow,    Op7B,        Op7CSlow,
3225  	Op7DSlow,    Op7ESlow,    Op7FSlow,    Op80Slow,    Op81Slow,
3226  	Op82Slow,    Op83Slow,    Op84Slow,    Op85Slow,    Op86Slow,
3227  	Op87Slow,    Op88Slow,    Op89Slow,    Op8ASlow,    Op8BSlow,
3228  	Op8CSlow,    Op8DSlow,    Op8ESlow,    Op8FSlow,    Op90Slow,
3229  	Op91Slow,    Op92Slow,    Op93Slow,    Op94Slow,    Op95Slow,
3230  	Op96Slow,    Op97Slow,    Op98Slow,    Op99Slow,    Op9A,
3231  	Op9BSlow,    Op9CSlow,    Op9DSlow,    Op9ESlow,    Op9FSlow,
3232  	OpA0Slow,    OpA1Slow,    OpA2Slow,    OpA3Slow,    OpA4Slow,
3233  	OpA5Slow,    OpA6Slow,    OpA7Slow,    OpA8Slow,    OpA9Slow,
3234  	OpAASlow,    OpABSlow,    OpACSlow,    OpADSlow,    OpAESlow,
3235  	OpAFSlow,    OpB0Slow,    OpB1Slow,    OpB2Slow,    OpB3Slow,
3236  	OpB4Slow,    OpB5Slow,    OpB6Slow,    OpB7Slow,    OpB8,
3237  	OpB9Slow,    OpBASlow,    OpBBSlow,    OpBCSlow,    OpBDSlow,
3238  	OpBESlow,    OpBFSlow,    OpC0Slow,    OpC1Slow,    OpC2Slow,
3239  	OpC3Slow,    OpC4Slow,    OpC5Slow,    OpC6Slow,    OpC7Slow,
3240  	OpC8Slow,    OpC9Slow,    OpCASlow,    OpCB,        OpCCSlow,
3241  	OpCDSlow,    OpCESlow,    OpCFSlow,    OpD0Slow,    OpD1Slow,
3242  	OpD2Slow,    OpD3Slow,    OpD4Slow,    OpD5Slow,    OpD6Slow,
3243  	OpD7Slow,    OpD8,        OpD9Slow,    OpDASlow,    OpDB,
3244  	OpDCSlow,    OpDDSlow,    OpDESlow,    OpDFSlow,    OpE0Slow,
3245  	OpE1Slow,    OpE2Slow,    OpE3Slow,    OpE4Slow,    OpE5Slow,
3246  	OpE6Slow,    OpE7Slow,    OpE8Slow,    OpE9Slow,    OpEA,
3247  	OpEB,        OpECSlow,    OpEDSlow,    OpEESlow,    OpEFSlow,
3248  	OpF0Slow,    OpF1Slow,    OpF2Slow,    OpF3Slow,    OpF4Slow,
3249  	OpF5Slow,    OpF6Slow,    OpF7Slow,    OpF8,        OpF9Slow,
3250  	OpFASlow,    OpFB,        OpFCSlow,    OpFDSlow,    OpFESlow,
3251  	OpFFSlow
3252  };