1  library ieee;
  2  use ieee.std_logic_1164.all;
  3  use ieee.std_logic_arith.all;
  4  use ieee.std_logic_unsigned.all;
  5  --
  6  -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
  7  -- http://www.mesanet.com
  8  --
  9  -- This program is is licensed under a disjunctive dual license giving you
 10  -- the choice of one of the two following sets of free software/open source
 11  -- licensing terms:
 12  --
 13  --    * GNU General Public License (GPL), version 2.0 or later
 14  --    * 3-clause BSD License
 15  -- 
 16  --
 17  -- The GNU GPL License:
 18  -- 
 19  --     This program is free software; you can redistribute it and/or modify
 20  --     it under the terms of the GNU General Public License as published by
 21  --     the Free Software Foundation; either version 2 of the License, or
 22  --     (at your option) any later version.
 23  -- 
 24  --     This program is distributed in the hope that it will be useful,
 25  --     but WITHOUT ANY WARRANTY; without even the implied warranty of
 26  --     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 27  --     GNU General Public License for more details.
 28  -- 
 29  --     You should have received a copy of the GNU General Public License
 30  --     along with this program; if not, write to the Free Software
 31  --     Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 32  -- 
 33  -- 
 34  -- The 3-clause BSD License:
 35  -- 
 36  --     Redistribution and use in source and binary forms, with or without
 37  --     modification, are permitted provided that the following conditions
 38  --     are met:
 39  -- 
 40  --         * Redistributions of source code must retain the above copyright
 41  --           notice, this list of conditions and the following disclaimer.
 42  -- 
 43  --         * Redistributions in binary form must reproduce the above
 44  --           copyright notice, this list of conditions and the following
 45  --           disclaimer in the documentation and/or other materials
 46  --           provided with the distribution.
 47  -- 
 48  --         * Neither the name of Mesa Electronics nor the names of its
 49  --           contributors may be used to endorse or promote products
 50  --           derived from this software without specific prior written
 51  --           permission.
 52  -- 
 53  -- 
 54  -- Disclaimer:
 55  -- 
 56  --     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 57  --     "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 58  --     LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 59  --     FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 60  --     COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 61  --     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 62  --     BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 63  --     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 64  --     CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 65  --     LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 66  --     ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 67  --     POSSIBILITY OF SUCH DAMAGE.
 68  -- 
 69  use work.log2.all;
 70  
 71  entity OutputInteg is		-- 8 channel integrator/accumulator with accumlators readable by host
 72      port ( dspdin : in  std_logic_vector (31 downto 0);
 73             dspdout : out  std_logic_vector (31 downto 0);
 74  			  hostdout : out  std_logic_vector (31 downto 0);
 75             dspraddr : in  std_logic_vector (2 downto 0);
 76             dspwaddr : in  std_logic_vector (2 downto 0);
 77             hostaddr : in  std_logic_vector (2 downto 0);
 78             loadvel : in  std_logic;			
 79             loadrate : in  std_logic;
 80             dspread : in  std_logic;
 81             hostread : in  std_logic;
 82  			  testout : out std_logic;
 83  			  clk : in std_logic);
 84  end OutputInteg;
 85  
 86  architecture Behavioral of OutputInteg is
 87  constant divwidth :integer := 16;
 88  constant channels : integer := 8;
 89  constant offset : integer := 8;			-- accumulator runs 256 times faster than host sample rate so sr by 8
 90  constant csize : integer := log2(channels);
 91  constant width : integer := 32;
 92  
 93  signal acca: std_logic_vector(width-1 downto 0);
 94  signal accb: std_logic_vector(width-1 downto 0);
 95  signal accsum: std_logic_vector(width-1 downto 0);
 96  signal rawhostdout: std_logic_vector(width-1 downto 0);
 97  signal rawdspdout: std_logic_vector(width-1 downto 0);
 98  signal offsetdin: std_logic_vector(width-1 downto 0);
 99  signal smaddr: std_logic_vector(log2(channels)-1 downto 0);
100  signal smwrite: std_logic;
101  signal run: std_logic;
102  signal ratereg: std_logic_vector(divwidth-1 downto 0);
103  signal ratediv: std_logic_vector(divwidth-1 downto 0);
104  alias ratedivmsb: std_logic is ratediv(divwidth-1);
105  signal oldratedivmsb: std_logic;
106  
107  begin
108  
109  	inputdpram: entity work.dpram
110  	generic map (
111  		width => width,
112  		depth => channels
113  				)
114  	port map(
115  		addra => dspwaddr,
116  		addrb => smaddr,
117  		clk  => clk,
118  		dina  => offsetdin,
119  --		douta =>	 
120  		doutb => acca,
121  		wea	=> loadvel
122  		); 
123  	
124  	feedbackdpram: entity work.dpram
125  	generic map (
126  		width => width,
127  		depth => channels
128  				)
129  	port map(
130  		addra => smaddr,
131  		addrb => dspraddr,
132  		clk  => clk,
133  		dina  => accsum,
134  		douta => accb,
135  		doutb => rawdspdout,
136  		wea	=> smwrite
137  		); 
138  
139  	outputdpram: entity work.dpram
140  	generic map (
141  		width => width,
142  		depth => channels
143  				)
144  	port map(
145  		addra => smaddr,
146  		addrb => hostaddr,
147  		clk  => clk,
148  		dina  => accsum,
149  --		douta => snugglebunnies,
150  		doutb => rawhostdout,
151  		wea	=> smwrite
152  		); 
153  
154  
155  	accumulator:  process(clk,acca,accb, dspdin, hostread, 
156  								 rawhostdout, dspread, rawdspdout, smwrite)		-- multi channel accumulator
157  	begin
158  		if rising_edge(clk) then
159  			ratediv <= ratediv + ratereg;
160  			if ratedivmsb /= oldratedivmsb then
161  				smaddr <= conv_std_logic_vector(0,csize);
162  				smwrite <= '0';	-- start channel processing at channel 0 read
163  				run <= '1';
164  			end if;	
165  				
166  			if run = '1' then
167  				if smwrite = '1' then -- if write asserted, increment channel
168  					if smaddr = conv_std_logic_vector(channels -1,csize) then 
169  						run <= '0';	-- if last channel stop till next rate req 
170  					else
171  						smaddr <= smaddr +1;
172  					end if;
173  				end if;						
174  				smwrite <= not smwrite;	-- alternate read/write per channel					
175  			end if;
176  		
177  			oldratedivmsb <= ratedivmsb;
178  		
179  			if loadrate = '1' then 
180  				ratereg <= dspdin(divwidth-1 downto 0);
181  			end if;
182  		
183  		end if; -- clk
184  		
185  		accsum <= acca + accb;
186  		
187  		offsetdin(width-offset-1 downto 0) <= dspdin(width-1 downto offset);
188  		if dspdin(width -1) = '1' then -- sign extend
189  			offsetdin(width-1 downto width-offset) <= (others => '1'); 
190  		else
191  			offsetdin(width-1 downto width-offset) <= (others => '0'); 
192  		end if;	
193  			
194  		
195  		hostdout <= (others => 'Z');
196  		if hostread = '1' then	
197  			hostdout <= rawhostdout;
198  		end if;
199  
200  		dspdout <= (others => 'Z');
201  		if dspread = '1' then	
202  			dspdout <= rawdspdout;
203  		end if;
204  		
205  		testout <= smwrite;
206  	end process;	
207  
208  end Behavioral;
209