/ PIN_7I77_7I74_SSI_FANUC_34.vhd
PIN_7I77_7I74_SSI_FANUC_34.vhd
1 library IEEE; 2 use IEEE.std_logic_1164.all; -- defines std_logic types 3 use IEEE.STD_LOGIC_ARITH.ALL; 4 use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 6 -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics 7 -- http://www.mesanet.com 8 -- 9 -- This program is is licensed under a disjunctive dual license giving you 10 -- the choice of one of the two following sets of free software/open source 11 -- licensing terms: 12 -- 13 -- * GNU General Public License (GPL), version 2.0 or later 14 -- * 3-clause BSD License 15 -- 16 -- 17 -- The GNU GPL License: 18 -- 19 -- This program is free software; you can redistribute it and/or modify 20 -- it under the terms of the GNU General Public License as published by 21 -- the Free Software Foundation; either version 2 of the License, or 22 -- (at your option) any later version. 23 -- 24 -- This program is distributed in the hope that it will be useful, 25 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 26 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 -- GNU General Public License for more details. 28 -- 29 -- You should have received a copy of the GNU General Public License 30 -- along with this program; if not, write to the Free Software 31 -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 32 -- 33 -- 34 -- The 3-clause BSD License: 35 -- 36 -- Redistribution and use in source and binary forms, with or without 37 -- modification, are permitted provided that the following conditions 38 -- are met: 39 -- 40 -- * Redistributions of source code must retain the above copyright 41 -- notice, this list of conditions and the following disclaimer. 42 -- 43 -- * Redistributions in binary form must reproduce the above 44 -- copyright notice, this list of conditions and the following 45 -- disclaimer in the documentation and/or other materials 46 -- provided with the distribution. 47 -- 48 -- * Neither the name of Mesa Electronics nor the names of its 49 -- contributors may be used to endorse or promote products 50 -- derived from this software without specific prior written 51 -- permission. 52 -- 53 -- 54 -- Disclaimer: 55 -- 56 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 57 -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 58 -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 59 -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 60 -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 61 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 62 -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 63 -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 64 -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 66 -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 -- POSSIBILITY OF SUCH DAMAGE. 68 -- 69 70 use work.IDROMConst.all; 71 72 package PIN_7I77_7I74_SSI_FANUC_34 is 73 constant ModuleID : ModuleIDType :=( 74 (HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask), 75 (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), 76 (IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), 77 (MuxedQcountTag, MQCRev, ClockLowTag, x"06", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask), 78 (MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"), 79 (FAbsTag, x"00", ClockLowTag, x"02", FAbsDataAddr0&PadT, FAbsNumRegs, x"00", FAbsMPBitMask), 80 (SSSITag, x"00", ClockLowTag, x"04", SSSIDataAddr0&PadT, SSSINumRegs, x"00", SSSIMPBitMask), 81 (SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask), 82 83 (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), 84 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 85 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 86 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 87 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 88 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 89 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 90 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 91 92 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 93 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 94 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 95 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 96 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 97 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 98 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 99 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 100 101 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 102 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 103 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 104 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 105 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 106 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 107 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), 108 (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") 109 ); 110 111 112 constant PinDesc : PinDescType :=( 113 -- Base func sec unit sec func sec pin -- P3 DB25 114 IOPortTag & x"00" & SSerialTag & SSerialTXEN2Pin, -- I/O 00 PIN 1 115 IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 01 PIN 14 116 IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2 117 IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 03 PIN 15 118 IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 04 PIN 3 119 IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 05 PIN 16 120 IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 06 PIN 4 121 IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 07 PIN 17 122 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 08 PIN 5 123 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 09 PIN 6 124 IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 10 PIN 7 125 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 11 PIN 8 126 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 12 PIN 9 127 IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 13 PIN 10 128 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 14 PIN 11 129 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 15 PIN 12 130 IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 16 PIN 13 131 132 -- P2 26 HDR DB25 133 IOPortTag & x"00" & SSSITag & SSSIDataPin, -- I/O 17 PIN 1 PIN 1 134 IOPortTag & x"01" & SSSITag & SSSIDataPin, -- I/O 18 PIN 2 PIN 14 135 IOPortTag & x"02" & SSSITag & SSSIDataPin, -- I/O 19 PIN 3 PIN 2 136 IOPortTag & x"03" & SSSITag & SSSIDataPin, -- I/O 20 PIN 4 PIN 15 137 IOPortTag & x"00" & SSSITag & SSSIClkPin, -- I/O 21 PIN 5 PIN 3 138 IOPortTag & x"01" & SSSITag & SSSIClkPin, -- I/O 22 PIN 6 PIN 16 139 IOPortTag & x"02" & SSSITag & SSSIClkPin, -- I/O 23 PIN 7 PIN 4 140 IOPortTag & x"03" & SSSITag & SSSIClkPin, -- I/O 24 PIN 8 PIN 17 141 IOPortTag & x"00" & FABsTag & FAbsDataPin, -- I/O 25 PIN 9 PIN 5 142 IOPortTag & x"01" & FABsTag & FAbsDataPin, -- I/O 26 PIN 11 PIN 6 143 IOPortTag & x"00" & NullTag & x"00", -- I/O 27 PIN 13 PIN 7 144 IOPortTag & x"00" & NullTag & x"00", -- I/O 28 PIN 15 PIN 8 145 IOPortTag & x"00" & FABsTag & FAbsRQPin, -- I/O 29 PIN 17 PIN 9 146 IOPortTag & x"01" & FABsTag & FAbsRQPin, -- I/O 30 PIN 19 PIN 10 147 IOPortTag & x"00" & HM2DPLLTag & HM2DPLLRefOutPin, -- I/O 31 PIN 21 PIN 11 148 IOPortTag & x"00" & HM2DPLLTag & HM2DPLLTimer1Pin, -- I/O 32 PIN 23 PIN 12 149 IOPortTag & x"00" & SSSITag & SSSIClkEnPin, -- I/O 33 PIN 25 PIN 13 150 151 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25 152 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 153 154 155 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3 156 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 157 158 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 159 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 160 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 161 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 162 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 163 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 164 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 165 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 166 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, 167 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); 168 169 end package PIN_7I77_7I74_SSI_FANUC_34;