/ TopPCIHostMot2.vhd
TopPCIHostMot2.vhd
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 use IEEE.STD_LOGIC_ARITH.ALL; 4 use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 -- 6 -- Copyright (C) 2011, Peter C. Wallace, Mesa Electronics 7 -- http://www.mesanet.com 8 -- 9 -- This program is is licensed under a disjunctive dual license giving you 10 -- the choice of one of the two following sets of free software/open source 11 -- licensing terms: 12 -- 13 -- * GNU General Public License (GPL), version 2.0 or later 14 -- * 3-clause BSD License 15 -- 16 -- 17 -- The GNU GPL License: 18 -- 19 -- This program is free software; you can redistribute it and/or modify 20 -- it under the terms of the GNU General Public License as published by 21 -- the Free Software Foundation; either version 2 of the License, or 22 -- (at your option) any later version. 23 -- 24 -- This program is distributed in the hope that it will be useful, 25 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 26 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 -- GNU General Public License for more details. 28 -- 29 -- You should have received a copy of the GNU General Public License 30 -- along with this program; if not, write to the Free Software 31 -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 32 -- 33 -- 34 -- The 3-clause BSD License: 35 -- 36 -- Redistribution and use in source and binary forms, with or without 37 -- modification, are permitted provided that the following conditions 38 -- are met: 39 -- 40 -- * Redistributions of source code must retain the above copyright 41 -- notice, this list of conditions and the following disclaimer. 42 -- 43 -- * Redistributions in binary form must reproduce the above 44 -- copyright notice, this list of conditions and the following 45 -- disclaimer in the documentation and/or other materials 46 -- provided with the distribution. 47 -- 48 -- * Neither the name of Mesa Electronics nor the names of its 49 -- contributors may be used to endorse or promote products 50 -- derived from this software without specific prior written 51 -- permission. 52 -- 53 -- 54 -- Disclaimer: 55 -- 56 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 57 -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 58 -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 59 -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 60 -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 61 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 62 -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 63 -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 64 -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 66 -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 -- POSSIBILITY OF SUCH DAMAGE. 68 -- 69 Library UNISIM; 70 use UNISIM.vcomponents.all; 71 72 -- dont change these: 73 use work.IDROMConst.all; 74 use work.decodedstrobe2.all; 75 use work.parity.all; 76 use work.FixICap.all; 77 78 -------------------- option selection area ---------------------------- 79 80 81 -------------------- select one card type------------------------------ 82 use work.@Card@.all; 83 --use work.i25_x9card.all; -- needs 5i25.ucf and SP6 x9 144 pin 84 --use work.i74_x9card.all; -- needs 4I74.ucf and SP6 x9 144 pin 85 --use work.Sixi25_x9card.all; -- needs 5i25.ucf and SP6 x9 144 pin 86 --use work.i24_x16card.all; -- needs 5I24.ucf and SP6 x16 256 pin 87 --use work.i24_x25card.all; -- needs 5I24.ucf and SP6 x25 256 pin 88 89 ----------------------------------------------------------------------- 90 91 92 -------------------- select (or add) one pinout ----------------------- 93 use work.@Pin@.all; 94 95 -- 34 I/O pinouts for 5I25, 5I26 and 6I25: 96 97 --use work.PIN_7I76x2_34.all; -- 5i25/6 step config for 2X 7I76 step/dir breakout 98 --use work.PIN_7I76x2R_34.all; -- Reversed 5i25/6 step config for 2X 7I76 step/dir breakout 99 --use work.PIN_G540x2_34.all; -- 5i25/6 step config for 2X Gecko 540 100 --use work.PIN_7I76_7I74_34.all; -- 5i25/6 step config for 7I76 step/dir breakout (P3) and 7I74 SSerial breakout (P2) 101 --use work.PIN_7I74_7I76_34.all; -- 5i25/6 step config for 7I76 step/dir breakout (P2) and 7I74 SSerial breakout (P3) 102 --use work.PIN_7I77x2_34.all; -- 5i25/6 analog servo config for 2X 7I77 analog servo breakout 103 --use work.PIN_7I77x2R_34.all; -- Reversed 5i25/6 analog servo config for 2X 7I77 analog servo breakout 104 --use work.PIN_7I77_7I74_34.all; -- 5i25/6 analog servo config for 7I77 analog servo breakout (P3) and 7I74 SSerial (P2) 105 --use work.PIN_7I74_7I77_34.all; -- 5i25/6 analog servo config for 7I77 analog servo breakout (P2) and 7I74 SSerial (P3) 106 --use work.PIN_7I77_7I76_34.all; -- 5i25/6 analog servo config+ 7i76 step/dir config for 7I77 and 7I76 (7I77 on P3) 107 --use work.PIN_7I76_7I77_34.all; -- 5i25/6 analog servo config+ 7i76 step/dir config for 7I77 and 7I76 (7I76 on P3) 108 --use work.PIN_7I77_7I78_34.all; -- 5i25/6 analog servo config+ 7i78 step/dir config for 7I77 and 7I76 109 --use work.PIN_7I74x2_34.all; -- 5i25/6 config for 2X 7I74 RS-422 SSerial I/O expansion 110 --use work.PIN_7I78x2_34.all; -- 5i25/6 step config for 2x 7I78 step/dir breakout 111 --use work.PIN_7I76_7I78_34.all; -- 5i25/6 step config for 7I76 and 7I78 step/dir breakout 112 --use work.PIN_PROB_RFx2_34.all; -- 5i25/6 step config for Probotix step/dir breakout 113 --use work.PIN_7I85x2_34.all; -- 2x 7I85 encoder + sserial 114 --use work.PIN_7I85Sx2_34.all; -- 2x 7I85S encoder + stepgens + sserial 115 --use work.PIN_7I85SPx2_34.all; -- 2x 7I85S encoder + pwmgens + sserial 116 --use work.PIN_7I76_7I85S_34.all; -- 7I76 and 7I85S 117 --use work.PIN_7I76P_7I85_34.all; -- 7I76 PWM and 7I85 118 --use work.PIN_7I76_7I85_34.all; -- 7I76 and 7I85 119 --use work.PIN_7I85S_7I78_34.all; -- 7I85S and 7I78 120 --use work.PIN_7I77_7I85S_34.all; -- 7I77 +7I85S step/dir config 121 --use work.PIN_7I77_7I85SP_34.all; -- 7I77 +7I85S pwm/dir config 122 --use work.PIN_R990x2_34.all; -- 5i25/6i25 step config for 2x Rutex R990 MB 123 --use work.PIN_DMMBOB1x2_34.all; -- DMM DBM4250 bob step/dir config 124 --use work.PIN_FALLBACK_34.all; -- IO only configuration for fast compiles whilst debugging PCI and fallback config 125 --use work.PIN_MX3660x2_34.all; -- config for Leadshine MX3660 triple step motor drive 126 --use work.PIN_7I77x1_IMS_34.all; -- config for 7I77 with spindle index mask 127 --use work.PIN_7I85SP_7I85_34.all; -- config for PWM/enc on P3 7I85S plus ss and encoder on P2 7I85 128 129 130 --Non standard 131 --use work.PIN_7I77_7I76_micges_34.all; -- 5i25/6 analog servo config+ 7i76 step/dir config for 7I77 and 7I76 132 --use work.PIN_BISSTEST_34.all; -- 8 channel BISS interface test 133 --use work.PIN_UA2_34.all; -- simple UART config for 7I76 SSERIAL device access 134 --use work.PIN_7I76_34.all; -- 5i25/6 step config for 7I76 step/dir breakout 135 --use work.PIN_7I78_34.all; -- 5i25/6 step config for 7I78 step/dir breakout 136 --use work.PIN_SYIL1_34.all; -- Syil stepper config 137 --use work.PIN_STSV6_1_34.all; -- simple pin order six channel step/dir plus PWM +spindle enc 138 --use work.PIN_TORMACH1_34.all; -- 5i25/6i25 step config for Tormach lathe 139 --use work.PIN_TORMACHT_34.all; -- 5i25/6i25 step config for Tormach lathe test 140 --use work.PIN_TORMACH2_34.all; -- 5i25/6i25 step config for Tormach mill 141 --use work.PIN_7I77_7I74_SSI_34.all; -- 7I77 + 7I74 with 8 SSI channels 142 --use work.PIN_7I77_SSI_7I74_34.all; -- 7I77 + 7I74 with 1 SSI on 7I77 exp 143 --use work.PIN_7I77_7I76P_34.all; -- 5i25/6 analog servo config+ 7i76 PWM/DIR config for 7I77 and 7I76 144 --use work.PIN_7I77_7I74_34_toromatic.all; 145 --use work.PIN_7I76x2_ssi_34.all; 146 --use work.PIN_7I76x2_biss_34.all; 147 --use work.PIN_7I76x2ST_34.all; 148 --use work.PIN_G540_7I85S_34.all; 149 --use work.PIN_7I77x2_ssi_34.all; 150 --use work.PIN_SP4_34.all; 151 --use work.PIN_7I77_7I74_SSI_FANUC_34.all; -- 7I77 + 7I74 with 4 SSI channels 2 FAbs and DPLL 152 --use work.PIN_Fritz1_34.all; 153 154 --use work.PIN_PBX_SS1_34.all; 155 156 -- 42 PIN PINOUTS FOR THE 4I74 157 158 --use work.PIN_SVSS8_8_42.all; -- 8 encoder + 8 sserial channels 159 --use work.PIN_SVSI8_8_42.all; -- 8 encoder + 8 SSI channels 160 --use work.PIN_SVBI8_4_42.all; -- 8 encoder + 4 BISS channels 161 --use work.PIN_FALLBACK_42.all; -- IO only configuration 162 163 -- 72 I/O pinouts for the 5I24/6I24 164 165 --use work.PIN_JUSTIO_72.all; 166 --use work.PIN_SVST8_4IM2_72.all; 167 --use work.PIN_SVST8_4_72.all; 168 --use work.PIN_SVST4_8_72.all; 169 --use work.PIN_SVST4_8_ADO_72.all; 170 --use work.PIN_SVST8_8IM2_72.all; 171 --use work.PIN_SVST1_4_7I47S_72.all; 172 --use work.PIN_SVST2_4_7I47_72.all; 173 --use work.PIN_SVST1_5_7I47_72.all; 174 --use work.PIN_2X7I65_72.all; 175 --use work.PIN_ST12_72.all; 176 --use work.PIN_SV12_72.all; 177 --use work.PIN_SVST8_12_2x7I47_72.all; 178 --use work.PIN_SVSP8_6_7I46_72.all; 179 --use work.PIN_24XQCTRONLY_72.all; 180 --use work.PIN_2X7I65_72.all; 181 --use work.PIN_SV12IM_2X7I48_72.all; 182 --use work.PIN_SV6_7I49_72.all; 183 --use work.PIN_SVUA8_4_72.all; 184 --use work.PIN_SVUA8_8_72.all; -- 7I44 pinout UARTS 185 --use work.PIN_DA2_72.all; 186 --use work.PIN_SVST4_8_ADO_72.all; 187 --use work.PIN_SVSS8_8_72.all; 188 --use work.PIN_SSSVST8_8_8_72.all; 189 --use work.PIN_SVSS6_6_72.all; 190 --use work.PIN_SVST6_6_7I52S_72.all; 191 --use work.PIN_SVSSST6_6_12_72.all; 192 --use work.PIN_SVSS6_8_72.all; 193 --use work.PIN_SSSVST8_1_5_7I47_72.all; 194 --use work.PIN_SVSS8_44_72.all; 195 --use work.PIN_RMSVSS6_8_72.all; 196 --use work.PIN_RMSVSS6_12_8_72.all; -- 4i69 5i24 only 197 --use work.PIN_RMSVSS6_10_8_72.all; 198 --use work.PIN_ST8_PLASMA_72.all; 199 --use work.PIN_SV4_7I47S_72.all; 200 --use work.PIN_SVSTUA6_6_6_7I48_72.all; 201 --use work.PIN_SVSTTP6_6_7I39_72.all; 202 --use work.PIN_ST18_72.all; 203 204 -- custom and special 205 --use work.PIN_TORMACH1_34.all; 206 --use work.PIN_FA1_72.all; 207 --use work.PIN_MIKA2_CPR_72.all; 208 --use work.PIN_HARRISON_72.all; 209 --use work.PIN_MAUROPON.all; 210 --use work.PIN_Andy1_72.all; 211 --use work.PIN_BASACKWARDS_SVSS6_8_72.all; 212 --use work.PIN_SVSTTP6_5_7I39_72.all; 213 --use work.PIN_SVFASS6_6_8_72.all; 214 215 entity TopPCIHostMot2 is -- for 5I24,5I25, 5I26, 6I25 PCI target mode 216 generic 217 ( 218 ThePinDesc: PinDescType := PinDesc; 219 TheModuleID: ModuleIDType := ModuleID; 220 PWMRefWidth: integer := 13; -- PWM resolution is PWMRefWidth-1 bits 221 IDROMType: integer := 3; 222 UseStepGenPrescaler : boolean := true; 223 UseIRQLogic: boolean := true; --- note this will pull in PWM ref 224 UseWatchDog: boolean := true; 225 OffsetToModules: integer := 64; 226 OffsetToPinDesc: integer := 448; 227 BusWidth: integer := 32; 228 AddrWidth: integer := 16; 229 InstStride0: integer := 4; -- instance stride 0 = 4 bytes = 1 x 32 bit 230 InstStride1: integer := 64; -- instance stride 1 = 64 bytes = 16 x 32 bit registers !! UARTS need 0x10 231 -- InstStride1: integer := 16; -- instance stride 1 = 64 bytes = 16 x 32 bit registers !! UARTS need 0x10 232 RegStride0: integer := 256; -- register stride 0 = 256 bytes = 64 x 32 bit registers 233 RegStride1: integer := 256; -- register stride 1 = 256 bytes - 64 x 32 bit 234 FallBack: boolean := false -- is this a fallback config? 235 ); 236 port 237 ( 238 AD : inout std_logic_vector (31 downto 0); 239 NCBE : in std_logic_vector (3 downto 0); 240 PAR : inout std_logic; 241 NFRAME : in std_logic; 242 NIRDY : in std_logic; 243 NTRDY : out std_logic; 244 NSTOP : out std_logic; 245 NLOCK : in std_logic; 246 IDSEL : in std_logic; 247 NDEVSEL : inout std_logic; -- inout is kludge 248 NPERR : out std_logic; 249 NSERR : out std_logic; 250 NINTA : out std_logic; 251 NRST : in std_logic; 252 NREQ : out std_logic; 253 PCLK : in std_logic; -- PCI clock 254 IOBITS: inout std_logic_vector (IOWidth -1 downto 0); -- external I/O bits 255 LIOBITS: inout std_logic_vector (LIOWidth -1 downto 0); -- local I/O bits 256 XCLK: in std_logic; -- Xtal clock 257 LEDS: out std_logic_vector(LEDCount -1 downto 0); 258 NINIT: out std_logic; 259 SPICLK : out std_logic; 260 SPIDI : in std_logic; 261 SPIDO : out std_logic; 262 SPICS : out std_logic 263 ); 264 265 end TopPCIHostMot2; 266 267 architecture Behavioral of TopPCIHostMot2 is 268 269 -- PCI constants 270 constant InterruptAck : std_logic_vector(3 downto 0) := x"0"; 271 constant SpecialCycle : std_logic_vector(3 downto 0) := x"1"; 272 constant IORead : std_logic_vector(3 downto 0) := x"2"; 273 constant IOWrite : std_logic_vector(3 downto 0) := x"3"; 274 constant MemRead : std_logic_vector(3 downto 0) := x"6"; 275 constant MemWrite : std_logic_vector(3 downto 0) := x"7"; 276 constant ConfigRead : std_logic_vector(3 downto 0) := x"A"; 277 constant ConfigWrite : std_logic_vector(3 downto 0) := x"B"; 278 constant MemReadMultiple : std_logic_vector(3 downto 0) := x"C"; 279 constant DualAddressCycle : std_logic_vector(3 downto 0) := x"D"; 280 constant MemReadLine : std_logic_vector(3 downto 0) := x"E"; 281 constant MemWriteandInv : std_logic_vector(3 downto 0) := x"F"; 282 283 284 constant DIDVIDAddr : std_logic_vector(7 downto 0) := x"00"; 285 constant StatComAddr : std_logic_vector(7 downto 0) := x"04"; 286 constant ClassRevAddr : std_logic_vector(7 downto 0) := x"08"; 287 constant ClassRev : std_logic_vector(31 downto 0) := x"11000001"; -- data acq & rev 1 288 --constant ClassRev : std_logic_vector(31 downto 0) := x"07010000"; -- parallel port 289 constant MiscAddr : std_logic_vector(7 downto 0) := x"0C"; 290 constant MiscReg : std_logic_vector(31 downto 0) := x"00000000"; 291 constant SSIDAddr : std_logic_vector(7 downto 0) := x"2C"; 292 constant BAR0Addr : std_logic_vector(7 downto 0) := x"10"; 293 constant IntAddr : std_logic_vector(7 downto 0) := x"3C"; 294 295 296 -- Misc global signals -- 297 signal D: std_logic_vector (BusWidth-1 downto 0); -- internal data bus 298 signal A: std_logic_vector (BusWidth-1 downto 0); 299 300 signal DataStrobe: std_logic; 301 signal ReadStb: std_logic; 302 signal WriteStb: std_logic; 303 signal ConfigReadStb: std_logic; 304 signal ConfigWriteStb: std_logic; 305 306 -- PCI bus interface signals 307 signal NFrame1 : std_logic; 308 signal IDevSel : std_logic; 309 signal IDevSel1 : std_logic; 310 signal IDevSel2 : std_logic; 311 signal LIDSel : std_logic; 312 signal Lint : std_logic; 313 signal PerrStb : std_logic; 314 signal PerrStb1 : std_logic; 315 signal PerrStb2 : std_logic; 316 signal StatPerr : std_logic; 317 signal SerrStb : std_logic; 318 signal SerrStb1 : std_logic; 319 --signal SerrStb2 : std_logic; 320 signal StatSerr : std_logic; 321 signal PCIFrame : std_logic; 322 signal ITRDY : std_logic; 323 signal IStop : std_logic; 324 signal Selected : std_logic; 325 signal ConfigSelect : std_logic; 326 signal NormalSelect : std_logic; 327 signal IPar : std_logic; 328 signal CPar : std_logic; 329 signal PAR1 : std_logic; 330 signal BusCmd : std_logic_vector(3 downto 0); 331 signal ADDrive : std_logic; 332 signal ParDrive : std_logic; 333 signal BusRead : std_logic; 334 -- signal BusRead1 : std_logic; 335 -- signal BusRead2 : std_logic; 336 signal BusWrite : std_logic; 337 signal BusWrite1 : std_logic; 338 signal BusWrite2 : std_logic; 339 340 -- PCI configuration space registers 341 signal StatComReg : std_logic_vector(31 downto 0) := x"02000000"; -- medium devsel 342 alias MemEna : std_logic is StatComReg(1); 343 alias ParEna : std_logic is StatComReg(6); 344 alias SerrEna : std_logic is StatComReg(8); 345 alias IntDis : std_logic is StatComReg(10); 346 signal BAR0Reg : std_logic_vector(31 downto 0) := x"00000000"; 347 signal IntReg : std_logic_vector(31 downto 0) := x"00000100"; 348 349 -- debug 350 351 signal ledff0 : std_logic := '0'; 352 signal ledff1 : std_logic := '0'; 353 signal blinkcount : std_logic_vector(23 downto 0); 354 355 -- configuration flash SPI interface 356 357 signal LoadSPIReg : std_logic; 358 signal ReadSPIReg : std_logic; 359 signal LoadSPICS : std_logic; 360 signal ReadSPICS : std_logic; 361 362 -- ICap interface 363 364 signal LoadICap : std_logic; 365 signal ICapI : std_logic_vector(15 downto 0); 366 signal ICapClock : std_logic; 367 signal ICapTimer : std_logic_vector(3 downto 0) := "0000"; 368 369 -- CLK multiplier DCM signals 370 371 signal fclk : std_logic; 372 signal clkfx0: std_logic; 373 signal clk0: std_logic; 374 375 signal clkmed : std_logic; 376 signal clkfx1: std_logic; 377 signal clk1: std_logic; 378 379 begin 380 381 ClockMult0 : DCM -- This takes 100 MHz clkmed an multiplies it to ClockHigh 382 generic map ( 383 CLKDV_DIVIDE => 2.0, 384 CLKFX_DIVIDE => 2, 385 CLKFX_MULTIPLY => 4, -- 4 FOR 200, 5 for 250, 6 for 300, 8 for 400 386 CLKIN_DIVIDE_BY_2 => FALSE, 387 CLKIN_PERIOD => 10.0, 388 CLKOUT_PHASE_SHIFT => "NONE", 389 CLK_FEEDBACK => "1X", 390 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", 391 392 DFS_FREQUENCY_MODE => "LOW", 393 DLL_FREQUENCY_MODE => "LOW", 394 DUTY_CYCLE_CORRECTION => TRUE, 395 FACTORY_JF => X"C080", 396 PHASE_SHIFT => 0, 397 STARTUP_WAIT => FALSE) 398 port map ( 399 400 CLK0 => clk0, -- 401 CLKFB => clk0, -- DCM clock feedback 402 CLKFX => clkfx0, 403 CLKIN => clkmed, -- Clock input (from IBUFG, BUFG or DCM) 404 PSCLK => '0', -- Dynamic phase adjust clock input 405 PSEN => '0', -- Dynamic phase adjust enable input 406 PSINCDEC => '0', -- Dynamic phase adjust increment/decrement 407 RST => '0' -- DCM asynchronous reset input 408 ); 409 410 BUFG_inst0 : BUFG 411 port map ( 412 O => fclk, -- Clock buffer output = clock high 413 I => clkfx0 -- Clock buffer input 414 ); 415 416 -- End of DCM_inst instantiation 417 418 -- CLK multiplier DCM signals 419 420 ClockMult1 : DCM -- This takes 50 MHz XTAL an multiplies it to ClockMed 421 generic map ( 422 CLKDV_DIVIDE => 2.0, 423 CLKFX_DIVIDE => 2, 424 CLKFX_MULTIPLY => 4, -- 4 FOR 100, 5 for 125, 6 for 150, 8 for 200 425 CLKIN_DIVIDE_BY_2 => FALSE, 426 CLKIN_PERIOD => 20.0, 427 CLKOUT_PHASE_SHIFT => "NONE", 428 CLK_FEEDBACK => "1X", 429 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", 430 431 DFS_FREQUENCY_MODE => "LOW", 432 DLL_FREQUENCY_MODE => "LOW", 433 DUTY_CYCLE_CORRECTION => TRUE, 434 FACTORY_JF => X"C080", 435 PHASE_SHIFT => 0, 436 STARTUP_WAIT => FALSE) 437 port map ( 438 439 CLK0 => clk1, -- 440 CLKFB => clk1, -- DCM clock feedback 441 CLKFX => clkfx1, 442 CLKIN => XCLK, -- Clock input (from IBUFG, BUFG or DCM) 443 PSCLK => '0', -- Dynamic phase adjust clock input 444 PSEN => '0', -- Dynamic phase adjust enable input 445 PSINCDEC => '0', -- Dynamic phase adjust increment/decrement 446 RST => '0' -- DCM asynchronous reset input 447 ); 448 449 BUFG_inst1 : BUFG 450 port map ( 451 O => clkmed, -- Clock buffer output - clock med 452 I => clkfx1 -- Clock buffer input 453 ); 454 455 -- End of DCM_inst instantiation 456 457 ICAP_SPARTAN6_inst : ICAP_SPARTAN6 458 generic map ( 459 DEVICE_ID => X"2000093", -- Specifies the pre-programmed Device ID value 460 SIM_CFG_FILE_NAME => "NONE" -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation 461 -- model 462 ) 463 port map ( 464 -- BUSY => BUSY, -- 1-bit output: Busy/Ready output 465 -- O => ICapO, -- 16-bit output: Configuration data output bus 466 CE => '0', -- 1-bit input: Active-Low ICAP Enable input 467 CLK => ICapClock, -- 1-bit input: Clock input ~6 MHz max 468 I => ICapI, -- 16-bit input: Configuration data input bus 469 WRITE => '0' -- 1-bit input: Read/Write control input 1= read 0= write 470 ); 471 ahostmot2: entity work.HostMot2 472 generic map ( 473 thepindesc => ThePinDesc, 474 themoduleid => TheModuleID, 475 idromtype => IDROMType, 476 sepclocks => SepClocks, 477 onews => OneWS, 478 usestepgenprescaler => UseStepGenPrescaler, 479 useirqlogic => UseIRQLogic, 480 pwmrefwidth => PWMRefWidth, 481 usewatchdog => UseWatchDog, 482 offsettomodules => OffsetToModules, 483 offsettopindesc => OffsetToPinDesc, 484 clockhigh => ClockHigh, 485 clockmed => ClockMed, 486 clocklow => ClockLow, 487 boardnamelow => BoardNameLow, 488 boardnamehigh => BoardNameHigh, 489 fpgasize => FPGASize, 490 fpgapins => FPGAPins, 491 ioports => IOPorts, 492 iowidth => IOWidth, 493 liowidth => LIOWidth, 494 portwidth => PortWidth, 495 buswidth => BusWidth, 496 addrwidth => AddrWidth, 497 inststride0 => InstStride0, 498 inststride1 => InstStride1, 499 regstride0 => RegStride0, 500 regstride1 => RegStride1, 501 ledcount => LEDCount ) 502 port map ( 503 ibus => AD, 504 obus => D, 505 addr => A(AddrWidth-1 downto 2), 506 readstb => ReadStb, 507 writestb => WriteStb, 508 clklow => PCLK, -- PCI clock 509 clkmed => clkmed, -- Processor clock 510 clkhigh => fclk, -- High speed clock 511 int => LINT, 512 iobits => IOBITS, 513 leds => LEDS 514 ); 515 516 ADDrivers: process (D,ADDrive) 517 begin 518 if ADDrive ='1' then 519 AD <= D; 520 else 521 AD <= (others => 'Z'); 522 end if; 523 end process ADDrivers; 524 525 BusCycleGen: process (PCLK, NIRDY, DataStrobe, ConfigSelect, PCIFrame, A, 526 IDevSel, IdevSel1, IDevSel2, ITRDY, ISTOP, ParDrive, IPar, CPar, 527 LIDSel, Bar0Reg, BusCmd, LInt, IntReg, ConfigSelect, BusRead,Selected, 528 NCBE, NormalSelect, SerrStb1, PerrStb2, StatComReg, BusWrite1,BusWrite2) -- to do: parity error reporting in status 529 begin 530 if rising_edge(PCLK) then 531 if NFRAME = '0' and Nframe1 = '1' then -- falling edge of NFRAME = start of frame 532 A <= AD; -- so latch address and PCI command 533 BusCmd <= NCBE; 534 PCIFrame <= '1'; 535 SerrStb <= '1'; 536 LIDSel <= IDSEL; 537 else 538 SerrStb <= '0'; 539 end if; 540 541 if PCIFrame = '1' then -- if we are in a PCI frame, check if we are selected 542 if Selected = '1' then 543 IDevSel <= '1'; -- if so assert DEVSEL 544 end if; 545 end if; 546 547 if IDevSel = '1' then 548 if NIRDY = '0' then 549 ITRDY <= '1'; -- note one clock delay for one wait state; 550 end if; 551 if ITRDY = '1' then -- only asserted for one clock 552 ITRDY <= '0'; 553 end if; 554 end if; 555 556 if (NFRAME = '1') then -- any time frame is high end frame 557 PCIFrame <= '0'; 558 if (NIRDY= '0') and (ITRDY = '1') then -- if frame is de-asserted and we have a data transfer, we're done 559 IDevSel <= '0'; 560 end if; 561 end if; 562 563 if (NIRDY = '0') and (ITRDY = '1') and (NCBE /= x"F") then -- increment address after every transfer 564 A <= A + 4; 565 end if; 566 567 IDevSel2 <= IDevSel1; 568 IDevSel1 <= IDevSel; 569 570 -- BusRead2 <= BusRead1; 571 -- BusRead1 <= BusRead; 572 573 BusWrite2 <= BusWrite1; 574 BusWrite1 <= BusWrite; 575 576 PerrStb2 <= PerrStb1; 577 PerrStb1 <= PerrStb; 578 579 -- SerrStb2 <= SerrStb1; 580 SerrStb1 <= SerrStb; 581 582 583 NFrame1 <= NFRAME; 584 PAR1 <= PAR; 585 586 IStop <= '0'; -- for now 587 588 IPar <= parity(AD&NCBE&'0'); -- Parity generation 1 clock behind data (0 is even reminder) 589 CPar <= IPar xor PAR1; -- Parity check 2 clocks behind data (high = error) 590 ParDrive <= ADDrive; -- 1 clock behind AD Tristate 591 592 if NRST = '0' then 593 PCIFrame <= '0'; 594 IDevSel <= '0'; 595 ITRDY <= '0'; 596 end if; 597 end if; -- clk 598 599 600 if NIRDY = '0' and ITRDY = '1' and (NCBE /= x"F") then -- data cycle when IRDY AND TRDY and a least one byte enable 601 DataStrobe <= '1'; 602 else 603 DataStrobe <= '0'; 604 end if; 605 606 if (DataStrobe = '1') and ((BusCmd = MemRead) or (BusCmd = MemReadMultiple)) then 607 ReadStb<= '1'; 608 else 609 ReadStb <= '0'; 610 end if; 611 612 if (DataStrobe = '1') and (BusCmd = MemWrite) then 613 WriteStb <= '1'; 614 else 615 WriteStb <= '0'; 616 end if; 617 618 if DataStrobe = '1' and (BusCmd = ConfigRead) then 619 ConfigReadStb <= '1'; 620 else 621 ConfigReadStb <= '0'; 622 end if; 623 624 if DataStrobe = '1' and (BusCmd = ConfigWrite) then 625 ConfigWriteStb <= '1'; 626 else 627 ConfigWriteStb <= '0'; 628 end if; 629 630 if DataStrobe = '1' and ((BusCmd = MemWrite) or (BusCmd = ConfigWrite)) then 631 PErrStb <= '1'; 632 else 633 PErrStb <= '0'; 634 end if; 635 636 Selected <= (ConfigSelect or (NormalSelect and MemEna)); 637 638 if ((PCIFrame = '1') and (Selected='1')) or (IDevSel= '1') or (IDevSel1 = '1') then -- keep driving NDEVSEL/NTRDY/NSTOP one clock after IDevsel de-sasserted 639 NDEVSEL <= not IDevSel; 640 NTRDY <= not ITRDY; 641 NSTOP <= not IStop; 642 else 643 NDEVSEL <= 'Z'; 644 NTRDY <= 'Z'; 645 NSTOP <= 'Z'; 646 end if; 647 648 if (IdevSel = '1') and (busread = '1') then 649 ADDrive <= '1'; 650 else 651 ADDrive <= '0'; 652 end if; 653 654 if ParDrive = '1' then -- PAR is driven with the AD buffer enable signal but one clock later 655 PAR <= IPar; 656 else 657 PAR <= 'Z'; 658 end if; 659 660 if ((IDevSel1 = '1') or (IdevSel2 = '1')) and ((BusWrite1 = '1') or (BusWrite2 = '1')) then 661 NPERR <= not (CPar and PerrStb2 and ParEna); 662 StatPerr <= (CPar and PerrStb2); 663 else 664 NPERR <= 'Z'; 665 StatPerr <= '0'; 666 end if; 667 668 if ((IDevSel = '1') and (SerrStb1 = '1') and (SerrEna = '1') and (ParEna = '1')) then 669 NSERR <= not CPar; 670 StatSerr <= CPar; 671 else 672 NSERR <= 'Z'; 673 StatSerr <= '0'; 674 675 end if; 676 677 if (LIDSel = '1') and ((BusCmd = ConfigRead) or (BusCmd = ConfigWrite)) then 678 ConfigSelect <= '1'; 679 else 680 ConfigSelect <= '0'; 681 end if; 682 683 if (Bar0Reg(31 downto 16) = A(31 downto 16)) and (MemEna = '1') and ((BusCmd = MemRead) or (BusCmd = MemReadMultiple) or (BusCmd = MemWrite)) then -- hard wired for 64 K select 684 NormalSelect <= '1'; 685 else 686 NormalSelect <= '0'; 687 end if; 688 689 if (BusCmd = MemRead) or (BusCmd = MemReadMultiple) or (BusCmd = ConfigRead) then 690 BusRead <= '1'; 691 else 692 BusRead <= '0'; 693 end if; 694 695 if ((BusCmd = MemWrite) or (BusCmd = ConfigWrite)) then 696 BusWrite <= '1'; 697 else 698 BusWrite <= '0'; 699 end if; 700 701 if (LINT = '0') and IntDis = '0' then 702 NINTA <= '0'; 703 else 704 NINTA <= 'Z'; 705 end if; 706 707 end process BusCycleGen; 708 709 710 PCIConfig : process (PCLK, A, ConfigSelect, BusCmd, LInt, StatComReg, Bar0Reg, IntReg) 711 begin 712 713 -- first the config space reads 714 D <= (others => 'Z'); 715 StatComReg(19) <= not LINT; 716 if (ConfigSelect = '1') and (BusCmd = ConfigRead) then 717 case A(7 downto 0) is 718 when DIDVIDAddr => D <= DIDVID; 719 when StatComAddr => D <= StatComReg; 720 when ClassRevAddr => D <= ClassRev; 721 when MiscAddr => D <= MiscReg; 722 when BAR0Addr => D <= BAR0Reg; 723 when SSIDAddr => D <= SSID; 724 when IntAddr => D <= IntReg; 725 when others => D <= (others => '0'); -- all unused config space reads as 0s 726 end case; 727 end if; 728 729 -- then the config space writes 730 if rising_edge(PCLK) then 731 if StatPerr = '1' then 732 StatComReg(31) <= '1'; -- signal data parity error in status reg 733 end if; 734 if StatSerr = '1' then 735 StatComReg(30) <= '1'; -- signal address parity error in status reg 736 end if; 737 if (ConfigSelect = '1') and (BusCmd = ConfigWrite) and (DataStrobe = '1') then 738 case A(7 downto 0) is 739 when StatComAddr => 740 if NCBE(0) = '0' then 741 StatComReg(1) <= AD(1); -- MemEna 742 StatComReg(6) <= AD(6); -- ParEna 743 end if; 744 if NCBE(1) = '0' then 745 StatComReg(8) <= AD(8); -- SerrEna 746 StatComReg(10) <= AD(10); -- IntDis 747 end if; 748 if NCBE(3) = '0' then 749 StatComReg(27) <= StatComReg(27) and not AD(27); -- status bits cleared when a 1 is written 750 StatComReg(30) <= StatComReg(30) and not AD(30); 751 StatComReg(31) <= StatComReg(31) and not AD(31); 752 end if; 753 when BAR0Addr => -- 64K range so only top 16 bits used 754 if NCBE(2) = '0' then 755 BAR0Reg(23 downto 16) <= AD(23 downto 16); 756 end if; 757 if NCBE(3) = '0' then 758 BAR0Reg(31 downto 24) <= AD(31 downto 24); 759 end if; 760 when IntAddr => -- only R/W byte of int reg supported 761 if NCBE(0) = '0' then 762 IntReg(7 downto 0) <= AD(7 downto 0); 763 end if; 764 when others => null; 765 end case; 766 end if; 767 if NRST = '0' then 768 BAR0Reg(31 downto 16) <= (others => '0'); 769 StatComReg <= x"02000000"; 770 IntReg <= x"00000100"; 771 -- ledff0 <= '0'; 772 -- ledff1 <= '0'; 773 end if; 774 775 end if; -- clk 776 end process PCIConfig; 777 778 ConfigDecode : process(A,ReadStb,WriteStb,NCBE) 779 begin 780 LoadSPICS <= decodedstrobe2(A(15 downto 0),x"0070",WriteStb,not NCBE(0)); 781 ReadSPICS <= decodedstrobe2(A(15 downto 0),x"0070",ReadStb,not NCBE(0)); 782 LoadSPIReg <= decodedstrobe2(A(15 downto 0),x"0074",WriteStb,not NCBE(0)); 783 ReadSPIReg <= decodedstrobe2(A(15 downto 0),x"0074",ReadStb,not NCBE(0)); 784 end process ConfigDecode; 785 786 ICapDecode : process(A,WriteStb,NCBE) 787 begin 788 LoadICap <= decodedstrobe2(A(15 downto 0),x"0078",WriteStb,not (NCBE(0) or NCBE(1))); 789 end process ICAPDecode; 790 791 ICapSupport: process (PCLK,LoadICap) 792 begin 793 if rising_edge(PCLK) then 794 if LoadICap = '1' then 795 ICapI <= FixICap(AD(15 downto 0)); 796 ICapTimer <= "1111"; 797 end if; 798 if ICapTimer /= "0000" then 799 ICapTimer <= ICapTimer -1; 800 end if; 801 ICapClock <= ((not ICapTImer(3)) and ICapTimer(2)); -- 4 counts wide , 8 counts late 802 end if; 803 end process ICapSupport; 804 805 asimplspi: entity work.simplespi8 -- configuration serial EEPROM access SPI port 806 generic map 807 ( 808 buswidth => 8, 809 div => 2, -- for divide by 3 -- 11 MHz 810 bits => 8 811 ) 812 port map 813 ( 814 clk => PCLK, 815 ibus => AD(7 downto 0), 816 obus => D(7 downto 0), 817 loaddata => LoadSPIReg, 818 readdata => ReadSPIReg, 819 loadcs => LoadSPICS, 820 readcs => ReadSPICS, 821 spiclk => SPICLK, 822 spiin => SPIDI, 823 spiout => SPIDO, 824 spics =>SPICS 825 ); 826 827 828 PCILooseEnds : process (PCLK) 829 begin 830 NREQ <= '1'; 831 end process PCILooseEnds; 832 833 dofallback: if fallback generate -- do blinky red light to indicate failure to load primary bitfile 834 Fallbackmode : process(PCLK) 835 begin 836 if rising_edge(PCLK) then 837 blinkcount <= blinkcount +1; 838 end if; 839 NINIT <= blinkcount(23); 840 end process; 841 end generate; 842 843 donormal: if not fallback generate 844 NormalMode : process(PCLK) 845 begin 846 NINIT <= 'Z'; 847 -- NINIT <= not ledff0; 848 end process; 849 end generate; 850 851 end Behavioral;