1  // Copyright 2019 Espressif Systems (Shanghai) PTE LTD
 2  //
 3  // Licensed under the Apache License, Version 2.0 (the "License");
 4  // you may not use this file except in compliance with the License.
 5  // You may obtain a copy of the License at
 6  //
 7  //     http://www.apache.org/licenses/LICENSE-2.0
 8  //
 9  // Unless required by applicable law or agreed to in writing, software
10  // distributed under the License is distributed on an "AS IS" BASIS,
11  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  // See the License for the specific language governing permissions and
13  // limitations under the License.
14  #include <stdbool.h>
15  #include <assert.h>
16  #include "string.h"
17  #include "sdkconfig.h"
18  #include "esp_err.h"
19  #include "esp_log.h"
20  #include "esp32s2/rom/spi_flash.h"
21  #include "soc/efuse_reg.h"
22  #include "soc/spi_reg.h"
23  #include "soc/spi_mem_reg.h"
24  #include "soc/soc_caps.h"
25  #include "flash_qio_mode.h"
26  #include "bootloader_flash_config.h"
27  #include "bootloader_common.h"
28  
29  #define FLASH_IO_MATRIX_DUMMY_40M   0
30  #define FLASH_IO_MATRIX_DUMMY_80M   0
31  
32  #define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM    3
33  
34  void bootloader_flash_update_id()
35  {
36      g_rom_flashchip.device_id = bootloader_read_flash_id();
37  }
38  
39  void bootloader_flash_update_size(uint32_t size)
40  {
41      g_rom_flashchip.chip_size = size;
42  }
43  
44  void IRAM_ATTR bootloader_flash_cs_timing_config()
45  {
46      SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
47      SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
48      SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
49      SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
50      SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
51      SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
52  }
53  
54  void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
55  {
56      uint32_t spi_clk_div = 0;
57      switch (pfhdr->spi_speed) {
58          case ESP_IMAGE_SPI_SPEED_80M:
59              spi_clk_div = 1;
60              break;
61          case ESP_IMAGE_SPI_SPEED_40M:
62              spi_clk_div = 2;
63              break;
64          case ESP_IMAGE_SPI_SPEED_26M:
65              spi_clk_div = 3;
66              break;
67          case ESP_IMAGE_SPI_SPEED_20M:
68              spi_clk_div = 4;
69              break;
70          default:
71              break;
72      }
73      esp_rom_spiflash_config_clk(spi_clk_div, 0);
74      esp_rom_spiflash_config_clk(spi_clk_div, 1);
75  }
76  
77  void IRAM_ATTR bootloader_flash_set_dummy_out(void)
78  {
79      REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
80      REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
81  }
82  
83  void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
84  {
85      bootloader_configure_spi_pins(1);
86      bootloader_flash_set_dummy_out();
87  }