bootloader_random_esp32.c
1 // Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #include "sdkconfig.h" 15 #include "bootloader_random.h" 16 #include "soc/rtc_periph.h" 17 #include "soc/sens_periph.h" 18 #include "soc/syscon_periph.h" 19 #include "soc/dport_reg.h" 20 #include "soc/i2s_periph.h" 21 #include "esp_log.h" 22 #include "soc/io_mux_reg.h" 23 24 #ifndef BOOTLOADER_BUILD 25 #include "driver/periph_ctrl.h" 26 #endif 27 28 void bootloader_random_enable(void) 29 { 30 /* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is 31 never disabled while the CPU is running), this is a "belts and braces" type check. 32 */ 33 #ifdef BOOTLOADER_BUILD 34 DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN); 35 #else 36 periph_module_enable(PERIPH_RNG_MODULE); 37 #endif // BOOTLOADER_BUILD 38 39 /* Enable SAR ADC in test mode to feed ADC readings of the 1.1V 40 reference via I2S into the RNG entropy input. 41 42 Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M) 43 in early bootloader startup must have been made. 44 */ 45 SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S); 46 SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); 47 SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); 48 49 #ifdef BOOTLOADER_BUILD 50 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); 51 #else 52 periph_module_enable(PERIPH_I2S0_MODULE); 53 #endif // BOOTLOADER_BUILD 54 CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP); 55 CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP); 56 57 // Test pattern configuration byte 0xAD: 58 //--[7:4] channel_sel: 10-->en_test 59 //--[3:2] bit_width : 3-->12bit 60 //--[1:0] atten : 1-->3dB attenuation 61 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); 62 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); 63 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); 64 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); 65 SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); 66 SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); 67 SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); 68 69 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX); 70 SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S); 71 SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */ 72 SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S); 73 SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S); 74 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL); 75 CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL); 76 SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S); 77 SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S); 78 79 CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN); 80 SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); 81 SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); 82 SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN); 83 SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); 84 } 85 86 void bootloader_random_disable(void) 87 { 88 /* Reset some i2s configuration (possibly redundant as we reset entire 89 I2S peripheral further down). */ 90 CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); 91 SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET); 92 CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET); 93 CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN); 94 CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); 95 CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN); 96 CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); 97 98 /* Disable i2s clock */ 99 #ifdef BOOTLOADER_BUILD 100 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); 101 #else 102 periph_module_disable(PERIPH_I2S0_MODULE); 103 #endif // BOOTLOADER_BUILD 104 105 /* Restore SYSCON mode registers */ 106 CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); 107 CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); 108 109 /* Restore SAR ADC mode */ 110 CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); 111 CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX 112 | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S); 113 SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); 114 115 SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S); 116 117 /* Reset i2s peripheral */ 118 #ifdef BOOTLOADER_BUILD 119 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); 120 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); 121 #else 122 periph_module_reset(PERIPH_I2S0_MODULE); 123 #endif 124 125 /* Disable pull supply voltage to SAR ADC */ 126 CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); 127 SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S); 128 }