test_timer.c
1 #include <stdio.h> 2 #include "freertos/FreeRTOS.h" 3 #include "freertos/task.h" 4 #include "freertos/queue.h" 5 #include "esp_system.h" 6 #include "unity.h" 7 #include "nvs_flash.h" 8 #include "driver/timer.h" 9 #include "soc/rtc.h" 10 #include "esp_rom_sys.h" 11 12 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) 13 14 #define TIMER_DIVIDER 16 15 #define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) /*!< used to calculate counter value */ 16 #define TIMER_DELTA 0.001 17 static bool alarm_flag; 18 static xQueueHandle timer_queue; 19 20 typedef struct { 21 timer_group_t timer_group; 22 timer_idx_t timer_idx; 23 } timer_info_t; 24 25 typedef struct { 26 timer_autoreload_t type; // the type of timer's event 27 timer_group_t timer_group; 28 timer_idx_t timer_idx; 29 uint64_t timer_counter_value; 30 } timer_event_t; 31 32 #define TIMER_INFO_INIT(TG, TID) {.timer_group = (TG), .timer_idx = (TID),} 33 34 static timer_info_t timer_info[4] = { 35 TIMER_INFO_INIT(TIMER_GROUP_0, TIMER_0), 36 TIMER_INFO_INIT(TIMER_GROUP_0, TIMER_1), 37 TIMER_INFO_INIT(TIMER_GROUP_1, TIMER_0), 38 TIMER_INFO_INIT(TIMER_GROUP_1, TIMER_1), 39 }; 40 41 #define GET_TIMER_INFO(TG, TID) (&timer_info[(TG)*2+(TID)]) 42 43 // timer group interruption handle callback 44 static bool test_timer_group_isr_cb(void *arg) 45 { 46 bool is_awoken = false; 47 timer_info_t* info = (timer_info_t*) arg; 48 const timer_group_t timer_group = info->timer_group; 49 const timer_idx_t timer_idx = info->timer_idx; 50 uint64_t timer_val; 51 double time; 52 uint64_t alarm_value; 53 timer_event_t evt; 54 alarm_flag = true; 55 if (timer_group_get_auto_reload_in_isr(timer_group, timer_idx)) { // For autoreload mode, the counter value has been cleared 56 timer_group_clr_intr_status_in_isr(timer_group, timer_idx); 57 esp_rom_printf("This is TG%d timer[%d] reload-timer alarm!\n", timer_group, timer_idx); 58 timer_get_counter_value(timer_group, timer_idx, &timer_val); 59 timer_get_counter_time_sec(timer_group, timer_idx, &time); 60 evt.type = TIMER_AUTORELOAD_EN; 61 } else { 62 timer_group_clr_intr_status_in_isr(timer_group, timer_idx); 63 esp_rom_printf("This is TG%d timer[%d] count-up-timer alarm!\n", timer_group, timer_idx); 64 timer_get_counter_value(timer_group, timer_idx, &timer_val); 65 timer_get_counter_time_sec(timer_group, timer_idx, &time); 66 timer_get_alarm_value(timer_group, timer_idx, &alarm_value); 67 timer_set_counter_value(timer_group, timer_idx, 0); 68 evt.type = TIMER_AUTORELOAD_DIS; 69 } 70 evt.timer_group = timer_group; 71 evt.timer_idx = timer_idx; 72 evt.timer_counter_value = timer_val; 73 if (timer_queue != NULL) { 74 BaseType_t awoken = pdFALSE; 75 BaseType_t ret = xQueueSendFromISR(timer_queue, &evt, &awoken); 76 TEST_ASSERT_EQUAL(pdTRUE, ret); 77 if (awoken) is_awoken = true; 78 } 79 return is_awoken; 80 } 81 82 // timer group interruption handle 83 static void test_timer_group_isr(void *arg) 84 { 85 if (test_timer_group_isr_cb(arg)) { 86 portYIELD_FROM_ISR(); 87 } 88 } 89 90 // initialize all timer 91 static void all_timer_init(timer_config_t *config, bool expect_init) 92 { 93 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 94 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 95 TEST_ASSERT_EQUAL((expect_init ? ESP_OK : ESP_ERR_INVALID_ARG), timer_init(tg_idx, timer_idx, config)); 96 } 97 } 98 if (timer_queue == NULL) { 99 timer_queue = xQueueCreate(10, sizeof(timer_event_t)); 100 } 101 } 102 103 // deinitialize all timer 104 static void all_timer_deinit(void) 105 { 106 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 107 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 108 TEST_ESP_OK(timer_deinit(tg_idx, timer_idx)); 109 } 110 } 111 if (timer_queue != NULL) { 112 vQueueDelete(timer_queue); 113 timer_queue = NULL; 114 } 115 } 116 117 // start all of timer 118 static void all_timer_start(void) 119 { 120 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 121 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 122 TEST_ESP_OK(timer_start(tg_idx, timer_idx)); 123 } 124 } 125 } 126 127 static void all_timer_set_counter_value(uint64_t set_cnt_val) 128 { 129 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 130 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 131 TEST_ESP_OK(timer_set_counter_value(tg_idx, timer_idx, set_cnt_val)); 132 } 133 } 134 } 135 136 static void all_timer_pause(void) 137 { 138 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 139 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 140 TEST_ESP_OK(timer_pause(tg_idx, timer_idx)); 141 } 142 } 143 } 144 145 static void all_timer_get_counter_value(uint64_t set_cnt_val, bool expect_equal_set_val, 146 uint64_t *actual_cnt_val) 147 { 148 uint64_t current_cnt_val; 149 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 150 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 151 TEST_ESP_OK(timer_get_counter_value(tg_idx, timer_idx, ¤t_cnt_val)); 152 if (expect_equal_set_val) { 153 TEST_ASSERT_EQUAL(set_cnt_val, current_cnt_val); 154 } else { 155 TEST_ASSERT_NOT_EQUAL(set_cnt_val, current_cnt_val); 156 if (actual_cnt_val != NULL) { 157 actual_cnt_val[tg_idx*TIMER_GROUP_MAX + timer_idx] = current_cnt_val; 158 } 159 } 160 } 161 } 162 } 163 164 static void all_timer_get_counter_time_sec(int expect_time) 165 { 166 double time; 167 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 168 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 169 TEST_ESP_OK(timer_get_counter_time_sec(tg_idx, timer_idx, &time)); 170 TEST_ASSERT_FLOAT_WITHIN(TIMER_DELTA, expect_time, time); 171 } 172 } 173 } 174 175 static void all_timer_set_counter_mode(timer_count_dir_t counter_dir) 176 { 177 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 178 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 179 TEST_ESP_OK(timer_set_counter_mode(tg_idx, timer_idx, counter_dir)); 180 } 181 } 182 } 183 184 static void all_timer_set_divider(uint32_t divider) 185 { 186 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 187 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 188 TEST_ESP_OK(timer_set_divider(tg_idx, timer_idx, divider)); 189 } 190 } 191 } 192 193 static void all_timer_set_alarm_value(uint64_t alarm_cnt_val) 194 { 195 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 196 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 197 TEST_ESP_OK(timer_set_alarm_value(tg_idx, timer_idx, alarm_cnt_val)); 198 } 199 } 200 } 201 202 static void all_timer_isr_reg(void) 203 { 204 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 205 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 206 TEST_ESP_OK(timer_isr_register(tg_idx, timer_idx, test_timer_group_isr, 207 GET_TIMER_INFO(tg_idx, timer_idx), ESP_INTR_FLAG_LOWMED, NULL)); 208 } 209 } 210 } 211 212 // enable interrupt and start timer 213 static void timer_intr_enable_and_start(int timer_group, int timer_idx, double alarm_time) 214 { 215 TEST_ESP_OK(timer_pause(timer_group, timer_idx)); 216 TEST_ESP_OK(timer_set_counter_value(timer_group, timer_idx, 0x0)); 217 TEST_ESP_OK(timer_set_alarm_value(timer_group, timer_idx, alarm_time * TIMER_SCALE)); 218 TEST_ESP_OK(timer_enable_intr(timer_group, timer_idx)); 219 TEST_ESP_OK(timer_start(timer_group, timer_idx)); 220 } 221 222 static void timer_isr_check(timer_group_t group_num, timer_idx_t timer_num, timer_autoreload_t autoreload, uint64_t alarm_cnt_val) 223 { 224 timer_event_t evt; 225 TEST_ASSERT_EQUAL(pdTRUE, xQueueReceive(timer_queue, &evt, 3000 / portTICK_PERIOD_MS)); 226 TEST_ASSERT_EQUAL(autoreload, evt.type); 227 TEST_ASSERT_EQUAL(group_num, evt.timer_group); 228 TEST_ASSERT_EQUAL(timer_num, evt.timer_idx); 229 TEST_ASSERT_EQUAL((uint32_t)(alarm_cnt_val >> 32), (uint32_t)(evt.timer_counter_value >> 32)); 230 TEST_ASSERT_UINT32_WITHIN(1000, (uint32_t)(alarm_cnt_val), (uint32_t)(evt.timer_counter_value)); 231 } 232 233 static void timer_intr_enable_disable_test(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_cnt_val) 234 { 235 alarm_flag = false; 236 TEST_ESP_OK(timer_set_counter_value(group_num, timer_num, 0)); 237 TEST_ESP_OK(timer_set_alarm(group_num, timer_num, TIMER_ALARM_EN)); 238 TEST_ESP_OK(timer_enable_intr(group_num, timer_num)); 239 TEST_ESP_OK(timer_start(group_num, timer_num)); 240 timer_isr_check(group_num, timer_num, TIMER_AUTORELOAD_DIS, alarm_cnt_val); 241 TEST_ASSERT_EQUAL(true, alarm_flag); 242 243 // disable interrupt of tg0_timer0 244 alarm_flag = false; 245 TEST_ESP_OK(timer_pause(group_num, timer_num)); 246 TEST_ESP_OK(timer_set_counter_value(group_num, timer_num, 0)); 247 TEST_ESP_OK(timer_disable_intr(group_num, timer_num)); 248 TEST_ESP_OK(timer_start(group_num, timer_num)); 249 vTaskDelay(2000 / portTICK_PERIOD_MS); 250 TEST_ASSERT_EQUAL(false, alarm_flag); 251 } 252 253 TEST_CASE("Timer init", "[hw_timer]") 254 { 255 // Test init 1:config parameter 256 // empty parameter 257 timer_config_t config0 = { }; 258 all_timer_init(&config0, false); 259 260 // only one parameter 261 timer_config_t config1 = { 262 .auto_reload = TIMER_AUTORELOAD_EN 263 }; 264 all_timer_init(&config1, false); 265 266 // lack one parameter 267 timer_config_t config2 = { 268 .auto_reload = TIMER_AUTORELOAD_EN, 269 .counter_dir = TIMER_COUNT_UP, 270 .divider = TIMER_DIVIDER, 271 .counter_en = TIMER_START, 272 .intr_type = TIMER_INTR_LEVEL 273 }; 274 all_timer_init(&config2, true); 275 276 config2.counter_en = TIMER_PAUSE; 277 all_timer_init(&config2, true); 278 279 // error config parameter 280 timer_config_t config3 = { 281 .alarm_en = 3, //error parameter 282 .auto_reload = TIMER_AUTORELOAD_EN, 283 .counter_dir = TIMER_COUNT_UP, 284 .divider = TIMER_DIVIDER, 285 .counter_en = TIMER_START, 286 .intr_type = TIMER_INTR_LEVEL 287 }; 288 all_timer_init(&config3, true); 289 timer_config_t get_config; 290 TEST_ESP_OK(timer_get_config(TIMER_GROUP_1, TIMER_1, &get_config)); 291 printf("Error config alarm_en is %d\n", get_config.alarm_en); 292 TEST_ASSERT_NOT_EQUAL(config3.alarm_en, get_config.alarm_en); 293 294 // Test init 2: init 295 uint64_t set_timer_val = 0x0; 296 timer_config_t config = { 297 .alarm_en = TIMER_ALARM_DIS, 298 .auto_reload = TIMER_AUTORELOAD_EN, 299 .counter_dir = TIMER_COUNT_UP, 300 .divider = TIMER_DIVIDER, 301 .counter_en = TIMER_START, 302 .intr_type = TIMER_INTR_LEVEL 303 }; 304 305 // judge get config parameters 306 TEST_ESP_OK(timer_init(TIMER_GROUP_0, TIMER_0, &config)); 307 TEST_ESP_OK(timer_get_config(TIMER_GROUP_0, TIMER_0, &get_config)); 308 TEST_ASSERT_EQUAL(config.alarm_en, get_config.alarm_en); 309 TEST_ASSERT_EQUAL(config.auto_reload, get_config.auto_reload); 310 TEST_ASSERT_EQUAL(config.counter_dir, get_config.counter_dir); 311 TEST_ASSERT_EQUAL(config.counter_en, get_config.counter_en); 312 TEST_ASSERT_EQUAL(config.intr_type, get_config.intr_type); 313 TEST_ASSERT_EQUAL(config.divider, get_config.divider); 314 315 all_timer_init(&config, true); 316 all_timer_pause(); 317 all_timer_set_counter_value(set_timer_val); 318 all_timer_start(); 319 all_timer_get_counter_value(set_timer_val, false, NULL); 320 321 // Test init 3: wrong parameter 322 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(-1, TIMER_1, &config)); 323 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(TIMER_GROUP_1, 2, &config)); 324 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(TIMER_GROUP_1, -1, &config)); 325 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_init(2, TIMER_1, &config)); 326 all_timer_deinit(); 327 } 328 329 /** 330 * read count case: 331 * 1. start timer compare value 332 * 2. pause timer compare value 333 * 3. delay some time */ 334 TEST_CASE("Timer read counter value", "[hw_timer]") 335 { 336 timer_config_t config = { 337 .alarm_en = TIMER_ALARM_EN, 338 .auto_reload = TIMER_AUTORELOAD_EN, 339 .counter_dir = TIMER_COUNT_UP, 340 .divider = TIMER_DIVIDER, 341 .counter_en = TIMER_START, 342 .intr_type = TIMER_INTR_LEVEL 343 }; 344 uint64_t set_timer_val = 0x0; 345 346 all_timer_init(&config, true); 347 348 // Test read value 1: start timer get counter value 349 all_timer_set_counter_value(set_timer_val); 350 all_timer_start(); 351 all_timer_get_counter_value(set_timer_val, false, NULL); 352 353 // Test read value 2: pause timer get counter value 354 all_timer_pause(); 355 set_timer_val = 0x30405000ULL; 356 all_timer_set_counter_value(set_timer_val); 357 all_timer_get_counter_value(set_timer_val, true, NULL); 358 359 // Test read value 3:delay 1s get counter value 360 set_timer_val = 0x0; 361 all_timer_set_counter_value(set_timer_val); 362 all_timer_start(); 363 vTaskDelay(1000 / portTICK_PERIOD_MS); 364 all_timer_get_counter_time_sec(1); 365 all_timer_deinit(); 366 } 367 368 /** 369 * start timer case: 370 * 1. normal start 371 * 2. error start parameter 372 * */ 373 TEST_CASE("Timer start", "[hw_timer]") 374 { 375 timer_config_t config = { 376 .alarm_en = TIMER_ALARM_EN, 377 .auto_reload = TIMER_AUTORELOAD_EN, 378 .counter_dir = TIMER_COUNT_UP, 379 .divider = TIMER_DIVIDER, 380 .counter_en = TIMER_START, 381 .intr_type = TIMER_INTR_LEVEL 382 }; 383 uint64_t set_timer_val = 0x0; 384 all_timer_init(&config, true); 385 386 //Test start 1: normal start 387 all_timer_start(); 388 all_timer_set_counter_value(set_timer_val); 389 all_timer_get_counter_value(set_timer_val, false, NULL); 390 391 //Test start 2:wrong parameter 392 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(2, TIMER_1)); 393 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(-1, TIMER_1)); 394 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(TIMER_GROUP_1, 2)); 395 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_start(TIMER_GROUP_1, -1)); 396 all_timer_deinit(); 397 } 398 399 /** 400 * pause timer case: 401 * 1. normal pause, read value 402 * 2. error pause error 403 */ 404 TEST_CASE("Timer pause", "[hw_timer]") 405 { 406 timer_config_t config = { 407 .alarm_en = TIMER_ALARM_EN, 408 .auto_reload = TIMER_AUTORELOAD_EN, 409 .counter_dir = TIMER_COUNT_UP, 410 .divider = TIMER_DIVIDER, 411 .counter_en = TIMER_START, 412 .intr_type = TIMER_INTR_LEVEL 413 }; 414 uint64_t set_timer_val = 0x0; 415 all_timer_init(&config, true); 416 417 //Test pause 1: right parameter 418 all_timer_pause(); 419 all_timer_set_counter_value(set_timer_val); 420 all_timer_get_counter_value(set_timer_val, true, NULL); 421 422 //Test pause 2: wrong parameter 423 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_pause(-1, TIMER_0)); 424 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_pause(TIMER_GROUP_0, -1)); 425 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_pause(2, TIMER_0)); 426 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_pause(TIMER_GROUP_1, 2)); 427 all_timer_deinit(); 428 } 429 430 // positive mode and negative mode 431 TEST_CASE("Timer counter mode (up / down)", "[hw_timer]") 432 { 433 timer_config_t config = { 434 .alarm_en = TIMER_ALARM_EN, 435 .auto_reload = TIMER_AUTORELOAD_EN, 436 .counter_dir = TIMER_COUNT_UP, 437 .divider = TIMER_DIVIDER, 438 .counter_en = TIMER_START, 439 .intr_type = TIMER_INTR_LEVEL 440 }; 441 uint64_t set_timer_val = 0x0; 442 all_timer_init(&config, true); 443 all_timer_pause(); 444 445 // Test counter mode 1: TIMER_COUNT_UP 446 all_timer_set_counter_mode(TIMER_COUNT_UP); 447 all_timer_set_counter_value(set_timer_val); 448 all_timer_start(); 449 vTaskDelay(1000 / portTICK_PERIOD_MS); 450 all_timer_get_counter_time_sec(1); 451 452 // Test counter mode 2: TIMER_COUNT_DOWN 453 all_timer_pause(); 454 set_timer_val = 0x00E4E1C0ULL; // 3s clock counter value 455 all_timer_set_counter_mode(TIMER_COUNT_DOWN); 456 all_timer_set_counter_value(set_timer_val); 457 all_timer_start(); 458 vTaskDelay(1000 / portTICK_PERIOD_MS); 459 all_timer_get_counter_time_sec(2); 460 461 // Test counter mode 3 : wrong parameter 462 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_counter_mode(TIMER_GROUP_0, TIMER_0, -1)); 463 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_counter_mode(TIMER_GROUP_0, TIMER_0, 2)); 464 all_timer_deinit(); 465 } 466 467 /** 468 * divider case: 469 * 1. different divider, read value 470 * Note: divide 0 = divide max, divide 1 = divide 2 471 * 2. error parameter 472 * 473 * the frequency(timer counts in one sec): 474 * 80M/divider = 800*100000 475 * max divider value is 65536, its frequency is 1220 (nearly about 1KHz) 476 */ 477 TEST_CASE("Timer divider", "[hw_timer]") 478 { 479 int i; 480 timer_config_t config = { 481 .alarm_en = TIMER_ALARM_EN, 482 .auto_reload = TIMER_AUTORELOAD_EN, 483 .counter_dir = TIMER_COUNT_UP, 484 .divider = TIMER_DIVIDER, 485 .counter_en = TIMER_START, 486 .intr_type = TIMER_INTR_LEVEL 487 }; 488 uint64_t set_timer_val = 0; 489 uint64_t time_val[4]; 490 uint64_t comp_time_val[4]; 491 all_timer_init(&config, true); 492 493 all_timer_pause(); 494 all_timer_set_counter_value(set_timer_val); 495 496 all_timer_start(); 497 vTaskDelay(1000 / portTICK_PERIOD_MS); 498 all_timer_get_counter_value(set_timer_val, false, time_val); 499 500 // compare divider 16 and 8, value should be double 501 all_timer_pause(); 502 all_timer_set_divider(8); 503 all_timer_set_counter_value(set_timer_val); 504 505 all_timer_start(); 506 vTaskDelay(1000 / portTICK_PERIOD_MS); //delay the same time 507 all_timer_get_counter_value(set_timer_val, false, comp_time_val); 508 for (i = 0; i < 4; i++) { 509 TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]); 510 TEST_ASSERT_INT_WITHIN(10000, 10000000, comp_time_val[i]); 511 } 512 513 // divider is 256, value should be 2^4 514 all_timer_pause(); 515 all_timer_set_divider(256); 516 all_timer_set_counter_value(set_timer_val); 517 all_timer_start(); 518 vTaskDelay(1000 / portTICK_PERIOD_MS); //delay the same time 519 all_timer_get_counter_value(set_timer_val, false, comp_time_val); 520 for (i = 0; i < 4; i++) { 521 TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]); 522 TEST_ASSERT_INT_WITHIN(3126, 312500, comp_time_val[i]); 523 } 524 525 // extrem value test 526 all_timer_pause(); 527 all_timer_set_divider(2); 528 all_timer_set_counter_value(set_timer_val); 529 all_timer_start(); 530 vTaskDelay(1000 / portTICK_PERIOD_MS); 531 all_timer_get_counter_value(set_timer_val, false, comp_time_val); 532 for (i = 0; i < 4; i++) { 533 TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]); 534 TEST_ASSERT_INT_WITHIN(40000 , 40000000, comp_time_val[i]); 535 } 536 537 all_timer_pause(); 538 all_timer_set_divider(65536); 539 all_timer_set_counter_value(set_timer_val); 540 all_timer_start(); 541 vTaskDelay(1000 / portTICK_PERIOD_MS); //delay the same time 542 all_timer_get_counter_value(set_timer_val, false, comp_time_val); 543 for (i = 0; i < 4; i++) { 544 TEST_ASSERT_INT_WITHIN(5000, 5000000, time_val[i]); 545 TEST_ASSERT_INT_WITHIN(2 , 1220, comp_time_val[i]); 546 } 547 548 // divider is 1 should be equal with 2 549 all_timer_pause(); 550 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_0, TIMER_0, 1)); 551 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_1, TIMER_0, 1)); 552 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_0, TIMER_1, 1)); 553 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_1, TIMER_1, 1)); 554 555 all_timer_pause(); 556 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_0, TIMER_0, 65537)); 557 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_1, TIMER_0, 65537)); 558 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_0, TIMER_1, 65537)); 559 TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, timer_set_divider(TIMER_GROUP_1, TIMER_1, 65537)); 560 all_timer_deinit(); 561 } 562 563 /** 564 * enable alarm case: 565 * 1. enable alarm ,set alarm value and get value 566 * 2. disable alarm ,set alarm value and get value 567 */ 568 TEST_CASE("Timer enable alarm", "[hw_timer]") 569 { 570 timer_config_t config_test = { 571 .alarm_en = TIMER_ALARM_DIS, 572 .auto_reload = TIMER_AUTORELOAD_DIS, 573 .counter_dir = TIMER_COUNT_UP, 574 .divider = TIMER_DIVIDER, 575 .counter_en = TIMER_PAUSE, 576 .intr_type = TIMER_INTR_LEVEL 577 }; 578 all_timer_init(&config_test, true); 579 all_timer_isr_reg(); 580 581 // enable alarm of tg0_timer1 582 alarm_flag = false; 583 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_1, TIMER_ALARM_EN)); 584 timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 1.2); 585 timer_isr_check(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE); 586 TEST_ASSERT_EQUAL(true, alarm_flag); 587 588 // disable alarm of tg0_timer1 589 alarm_flag = false; 590 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_1, TIMER_ALARM_DIS)); 591 timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 1.2); 592 vTaskDelay(2000 / portTICK_PERIOD_MS); 593 TEST_ASSERT_EQUAL(false, alarm_flag); 594 595 // enable alarm of tg1_timer0 596 alarm_flag = false; 597 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_0, TIMER_ALARM_EN)); 598 timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.2); 599 timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE); 600 TEST_ASSERT_EQUAL(true, alarm_flag); 601 602 // disable alarm of tg1_timer0 603 alarm_flag = false; 604 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_0, TIMER_ALARM_DIS)); 605 timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.2); 606 vTaskDelay(2000 / portTICK_PERIOD_MS); 607 TEST_ASSERT_EQUAL(false, alarm_flag); 608 all_timer_deinit(); 609 } 610 611 /** 612 * alarm value case: 613 * 1. set alarm value and get value 614 * 2. interrupt test time 615 */ 616 TEST_CASE("Timer set alarm value", "[hw_timer]") 617 { 618 int i; 619 uint64_t alarm_val[4]; 620 timer_config_t config = { 621 .alarm_en = TIMER_ALARM_EN, 622 .auto_reload = TIMER_AUTORELOAD_DIS, 623 .counter_dir = TIMER_COUNT_UP, 624 .divider = TIMER_DIVIDER, 625 .counter_en = TIMER_PAUSE, 626 .intr_type = TIMER_INTR_LEVEL 627 }; 628 all_timer_init(&config, true); 629 all_timer_isr_reg(); 630 631 // set and get alarm value 632 all_timer_set_alarm_value(3 * TIMER_SCALE); 633 TEST_ESP_OK(timer_get_alarm_value(TIMER_GROUP_0, TIMER_0, &alarm_val[0])); 634 TEST_ESP_OK(timer_get_alarm_value(TIMER_GROUP_0, TIMER_1, &alarm_val[1])); 635 TEST_ESP_OK(timer_get_alarm_value(TIMER_GROUP_1, TIMER_0, &alarm_val[2])); 636 TEST_ESP_OK(timer_get_alarm_value(TIMER_GROUP_1, TIMER_1, &alarm_val[3])); 637 for (i = 0; i < 4; i++) { 638 TEST_ASSERT_EQUAL_UINT32(3 * TIMER_SCALE, (uint32_t)alarm_val[i]); 639 } 640 641 // set interrupt read alarm value 642 timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 2.4); 643 timer_isr_check(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_DIS, 2.4 * TIMER_SCALE); 644 timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.4); 645 timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_DIS, 1.4 * TIMER_SCALE); 646 all_timer_deinit(); 647 } 648 649 /** 650 * auto reload case: 651 * 1. no reload 652 * 2. auto reload 653 */ 654 TEST_CASE("Timer auto reload", "[hw_timer]") 655 { 656 timer_config_t config = { 657 .alarm_en = TIMER_ALARM_EN, 658 .auto_reload = TIMER_AUTORELOAD_DIS, 659 .counter_dir = TIMER_COUNT_UP, 660 .divider = TIMER_DIVIDER, 661 .counter_en = TIMER_PAUSE, 662 .intr_type = TIMER_INTR_LEVEL 663 }; 664 all_timer_init(&config, true); 665 all_timer_isr_reg(); 666 667 // test disable auto_reload 668 timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 1.14); 669 timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_DIS, 1.14 * TIMER_SCALE); 670 timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_1, 1.14); 671 timer_isr_check(TIMER_GROUP_1, TIMER_1, TIMER_AUTORELOAD_DIS, 1.14 * TIMER_SCALE); 672 673 //test enable auto_reload 674 TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_EN)); 675 timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 1.4); 676 timer_isr_check(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_EN, 0); 677 TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_EN)); 678 timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 1.4); 679 timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_EN, 0); 680 all_timer_deinit(); 681 } 682 683 /** 684 * timer_enable_intr case: 685 * 1. enable timer_intr 686 * 2. disable timer_intr 687 */ 688 TEST_CASE("Timer enable timer interrupt", "[hw_timer]") 689 { 690 timer_config_t config = { 691 .alarm_en = TIMER_ALARM_DIS, 692 .counter_dir = TIMER_COUNT_UP, 693 .auto_reload = TIMER_AUTORELOAD_DIS, 694 .divider = TIMER_DIVIDER, 695 .counter_en = TIMER_PAUSE, 696 .intr_type = TIMER_INTR_LEVEL 697 }; 698 699 all_timer_init(&config, true); 700 all_timer_pause(); 701 all_timer_set_alarm_value(1.2 * TIMER_SCALE); 702 all_timer_set_counter_value(0); 703 all_timer_isr_reg(); 704 timer_intr_enable_disable_test(TIMER_GROUP_0, TIMER_0, 1.2 * TIMER_SCALE); 705 timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_1, 1.2 * TIMER_SCALE); 706 707 // enable interrupt of tg1_timer1 again 708 alarm_flag = false; 709 TEST_ESP_OK(timer_pause(TIMER_GROUP_1, TIMER_1)); 710 TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_1, TIMER_1, 0)); 711 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_1, TIMER_ALARM_EN)); 712 TEST_ESP_OK(timer_enable_intr(TIMER_GROUP_1, TIMER_1)); 713 TEST_ESP_OK(timer_start(TIMER_GROUP_1, TIMER_1)); 714 timer_isr_check(TIMER_GROUP_1, TIMER_1, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE); 715 TEST_ASSERT_EQUAL(true, alarm_flag); 716 all_timer_deinit(); 717 } 718 719 /** 720 * enable timer group case: 721 * 1. enable timer group 722 * 2. disable timer group 723 */ 724 TEST_CASE("Timer enable timer group interrupt", "[hw_timer][ignore]") 725 { 726 alarm_flag = false; 727 timer_config_t config = { 728 .alarm_en = TIMER_ALARM_EN, 729 .auto_reload = TIMER_AUTORELOAD_DIS, 730 .counter_dir = TIMER_COUNT_UP, 731 .divider = TIMER_DIVIDER, 732 .counter_en = TIMER_PAUSE, 733 .intr_type = TIMER_INTR_LEVEL 734 }; 735 uint64_t set_timer_val = 0x0; 736 all_timer_init(&config, true); 737 all_timer_pause(); 738 all_timer_set_counter_value(set_timer_val); 739 all_timer_set_alarm_value(1.2 * TIMER_SCALE); 740 741 // enable interrupt of tg0_timer0 742 TEST_ESP_OK(timer_group_intr_enable(TIMER_GROUP_0, TIMER_INTR_T0)); 743 TEST_ESP_OK(timer_isr_register(TIMER_GROUP_0, TIMER_0, test_timer_group_isr, 744 GET_TIMER_INFO(TIMER_GROUP_0, TIMER_0), ESP_INTR_FLAG_LOWMED, NULL)); 745 TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_0)); 746 timer_isr_check(TIMER_GROUP_0, TIMER_0, TIMER_AUTORELOAD_DIS, 1.2 * TIMER_SCALE); 747 TEST_ASSERT_EQUAL(true, alarm_flag); 748 749 // disable interrupt of tg0_timer0 750 alarm_flag = false; 751 TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_0, TIMER_0, set_timer_val)); 752 TEST_ESP_OK(timer_group_intr_disable(TIMER_GROUP_0, TIMER_INTR_T0)); 753 TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_0)); 754 vTaskDelay(2000 / portTICK_PERIOD_MS); 755 TEST_ASSERT_EQUAL(false, alarm_flag); 756 } 757 758 /** 759 * isr_register case: 760 * Cycle register 15 times, compare the heap size to ensure no memory leaks 761 */ 762 TEST_CASE("Timer interrupt register", "[hw_timer][leaks=200]") 763 { 764 timer_config_t config = { 765 .alarm_en = TIMER_ALARM_DIS, 766 .auto_reload = TIMER_AUTORELOAD_DIS, 767 .counter_dir = TIMER_COUNT_UP, 768 .divider = TIMER_DIVIDER, 769 .counter_en = TIMER_PAUSE, 770 .intr_type = TIMER_INTR_LEVEL 771 }; 772 773 for (int i = 0; i < 15; i++) { 774 all_timer_init(&config, true); 775 timer_isr_handle_t timer_isr_handle[TIMER_GROUP_MAX * TIMER_MAX]; 776 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 777 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 778 TEST_ESP_OK(timer_isr_register(tg_idx, timer_idx, test_timer_group_isr, 779 GET_TIMER_INFO(tg_idx, timer_idx), ESP_INTR_FLAG_LOWMED, &timer_isr_handle[tg_idx * TIMER_GROUP_MAX + timer_idx])); 780 } 781 } 782 783 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_0, TIMER_ALARM_EN)); 784 timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_0, 0.54); 785 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_1, TIMER_ALARM_EN)); 786 timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_1, 0.34); 787 788 TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_EN)); 789 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_0, TIMER_1, TIMER_ALARM_EN)); 790 timer_intr_enable_and_start(TIMER_GROUP_0, TIMER_1, 0.4); 791 TEST_ESP_OK(timer_set_auto_reload(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_EN)); 792 TEST_ESP_OK(timer_set_alarm(TIMER_GROUP_1, TIMER_0, TIMER_ALARM_EN)); 793 timer_intr_enable_and_start(TIMER_GROUP_1, TIMER_0, 0.6); 794 vTaskDelay(1000 / portTICK_PERIOD_MS); 795 796 // ISR hanlde function should be free before next ISR register. 797 for (uint32_t tg_idx=0; tg_idx<TIMER_GROUP_MAX; tg_idx++) { 798 for (uint32_t timer_idx=0; timer_idx<TIMER_MAX; timer_idx++) { 799 TEST_ESP_OK(esp_intr_free(timer_isr_handle[tg_idx * TIMER_GROUP_MAX + timer_idx])); 800 } 801 } 802 all_timer_deinit(); 803 } 804 } 805 806 #ifdef TIMER_GROUP_SUPPORTS_XTAL_CLOCK 807 /** 808 * Timer clock source: 809 * 1. configure clock source as APB clock, and enable timer interrupt 810 * 2. configure clock source as XTAL clock, adn enable timer interrupt 811 */ 812 TEST_CASE("Timer clock source", "[hw_timer]") 813 { 814 // configure clock source as APB clock 815 uint32_t timer_scale = rtc_clk_apb_freq_get() / TIMER_DIVIDER; 816 timer_config_t config = { 817 .alarm_en = TIMER_ALARM_DIS, 818 .auto_reload = TIMER_AUTORELOAD_DIS, 819 .counter_dir = TIMER_COUNT_UP, 820 .divider = TIMER_DIVIDER, 821 .counter_en = TIMER_PAUSE, 822 .intr_type = TIMER_INTR_LEVEL, 823 .clk_src = TIMER_SRC_CLK_APB 824 }; 825 all_timer_init(&config, true); 826 all_timer_pause(); 827 all_timer_set_alarm_value(1.2 * timer_scale); 828 all_timer_set_counter_value(0); 829 all_timer_isr_reg(); 830 831 timer_intr_enable_disable_test(TIMER_GROUP_0, TIMER_0, 1.2 * timer_scale); 832 timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_1, 1.2 * timer_scale ); 833 834 // configure clock source as XTAL clock 835 all_timer_pause(); 836 timer_scale = rtc_clk_xtal_freq_get() * 1000000 / TIMER_DIVIDER; 837 config.clk_src = TIMER_SRC_CLK_XTAL; 838 all_timer_init(&config, true); 839 all_timer_set_alarm_value(1.2 * timer_scale); 840 841 timer_intr_enable_disable_test(TIMER_GROUP_0, TIMER_0, 1.2 * timer_scale); 842 timer_intr_enable_disable_test(TIMER_GROUP_1, TIMER_1, 1.2 * timer_scale ); 843 844 all_timer_deinit(); 845 } 846 #endif 847 848 /** 849 * Timer ISR callback test 850 */ 851 TEST_CASE("Timer ISR callback", "[hw_timer]") 852 { 853 alarm_flag = false; 854 timer_config_t config = { 855 .alarm_en = TIMER_ALARM_EN, 856 .auto_reload = TIMER_AUTORELOAD_DIS, 857 .counter_dir = TIMER_COUNT_UP, 858 .divider = TIMER_DIVIDER, 859 .counter_en = TIMER_PAUSE, 860 .intr_type = TIMER_INTR_LEVEL, 861 }; 862 uint32_t timer_scale = rtc_clk_apb_freq_get() / TIMER_DIVIDER; 863 uint64_t alarm_cnt_val = 1.2 * timer_scale; 864 uint64_t set_timer_val = 0x0; 865 all_timer_init(&config, true); 866 all_timer_pause(); 867 all_timer_set_alarm_value(alarm_cnt_val); 868 all_timer_set_counter_value(set_timer_val); 869 870 // add isr callback for tg0_timer1 871 TEST_ESP_OK(timer_isr_callback_add(TIMER_GROUP_0, TIMER_1, test_timer_group_isr_cb, 872 GET_TIMER_INFO(TIMER_GROUP_0, TIMER_1), ESP_INTR_FLAG_LOWMED)); 873 TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_0, TIMER_1, set_timer_val)); 874 TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_1)); 875 timer_isr_check(TIMER_GROUP_0, TIMER_1, TIMER_AUTORELOAD_DIS, alarm_cnt_val); 876 TEST_ASSERT_EQUAL(true, alarm_flag); 877 878 // remove isr callback for tg0_timer1 879 TEST_ESP_OK(timer_pause(TIMER_GROUP_0, TIMER_1)); 880 TEST_ESP_OK(timer_isr_callback_remove(TIMER_GROUP_0, TIMER_1)); 881 alarm_flag = false; 882 TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_0, TIMER_1, set_timer_val)); 883 TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_1)); 884 vTaskDelay(2000 / portTICK_PERIOD_MS); 885 TEST_ASSERT_EQUAL(false, alarm_flag); 886 887 // add isr callback for tg1_timer0 888 TEST_ESP_OK(timer_pause(TIMER_GROUP_1, TIMER_0)); 889 TEST_ESP_OK(timer_isr_callback_add(TIMER_GROUP_1, TIMER_0, test_timer_group_isr_cb, 890 GET_TIMER_INFO(TIMER_GROUP_1, TIMER_0), ESP_INTR_FLAG_LOWMED)); 891 TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_1, TIMER_0, set_timer_val)); 892 TEST_ESP_OK(timer_start(TIMER_GROUP_1, TIMER_0)); 893 timer_isr_check(TIMER_GROUP_1, TIMER_0, TIMER_AUTORELOAD_DIS, alarm_cnt_val); 894 TEST_ASSERT_EQUAL(true, alarm_flag); 895 896 // remove isr callback for tg1_timer0 897 TEST_ESP_OK(timer_pause(TIMER_GROUP_1, TIMER_0)); 898 TEST_ESP_OK(timer_isr_callback_remove(TIMER_GROUP_1, TIMER_0)); 899 alarm_flag = false; 900 TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_1, TIMER_0, set_timer_val)); 901 TEST_ESP_OK(timer_start(TIMER_GROUP_1, TIMER_0)); 902 vTaskDelay(2000 / portTICK_PERIOD_MS); 903 TEST_ASSERT_EQUAL(false, alarm_flag); 904 all_timer_deinit(); 905 } 906 907 /** 908 * Timer memory test 909 */ 910 TEST_CASE("Timer memory test", "[hw_timer][leaks=100]") 911 { 912 timer_config_t config = { 913 .alarm_en = TIMER_ALARM_EN, 914 .auto_reload = TIMER_AUTORELOAD_EN, 915 .counter_dir = TIMER_COUNT_UP, 916 .divider = TIMER_DIVIDER, 917 .counter_en = TIMER_PAUSE, 918 .intr_type = TIMER_INTR_LEVEL, 919 }; 920 for(uint32_t i=0; i<100; i++) { 921 all_timer_init(&config, true); 922 all_timer_deinit(); 923 } 924 } 925 926 // The following test cases are used to check if the timer_group fix works. 927 // Some applications use a software reset, at the reset time, timer_group happens to generate an interrupt. 928 // but software reset does not clear interrupt status, this is not safe for application when enable the interrupt of timer_group. 929 // This case will check under this fix, whether the interrupt status is cleared after timer_group initialization. 930 static void timer_group_test_init(void) 931 { 932 static const uint32_t time_ms = 100; //Alarm value 100ms. 933 static const uint16_t timer_div = 10; //Timer prescaler 934 static const uint32_t ste_val = time_ms * (TIMER_BASE_CLK / timer_div / 1000); 935 timer_config_t config = { 936 .divider = timer_div, 937 .counter_dir = TIMER_COUNT_UP, 938 .counter_en = TIMER_PAUSE, 939 .alarm_en = TIMER_ALARM_EN, 940 .intr_type = TIMER_INTR_LEVEL, 941 .auto_reload = TIMER_AUTORELOAD_EN, 942 }; 943 TEST_ESP_OK(timer_init(TIMER_GROUP_0, TIMER_0, &config)); 944 TEST_ESP_OK(timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL)); 945 TEST_ESP_OK(timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, ste_val)); 946 //Now the timer is ready. 947 //We only need to check the interrupt status and don't have to register a interrupt routine. 948 } 949 950 static void timer_group_test_first_stage(void) 951 { 952 static uint8_t loop_cnt = 0; 953 timer_group_test_init(); 954 //Start timer 955 TEST_ESP_OK(timer_enable_intr(TIMER_GROUP_0, TIMER_0)); 956 TEST_ESP_OK(timer_start(TIMER_GROUP_0, TIMER_0)); 957 //Waiting for timer_group to generate an interrupt 958 while( !(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) && 959 loop_cnt++ < 100) { 960 vTaskDelay(200); 961 } 962 TEST_ASSERT_EQUAL(TIMER_INTR_T0, timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0); 963 esp_restart(); 964 } 965 966 static void timer_group_test_second_stage(void) 967 { 968 TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason()); 969 timer_group_test_init(); 970 //After the timer_group is initialized, TIMERG0.int_raw.t0 should be cleared. 971 TEST_ASSERT_EQUAL(0, timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0); 972 } 973 974 TEST_CASE_MULTIPLE_STAGES("timer_group software reset test", 975 "[intr_status][intr_status = 0]", 976 timer_group_test_first_stage, 977 timer_group_test_second_stage); 978 979 #endif