1  /* ESP32S2 Linker Script Memory Layout
  2  
  3     This file describes the memory layout (memory blocks) by virtual memory addresses.
  4  
  5     This linker script is passed through the C preprocessor to include configuration options.
  6  
  7     Please use preprocessor features sparingly!
  8     Restrict to simple macros with numeric values, and/or #if/#endif blocks.
  9  */
 10  #include "sdkconfig.h"
 11  
 12  #ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
 13  #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
 14  #elif defined(CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP)
 15  #define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
 16  #else
 17  #define ESP_BOOTLOADER_RESERVE_RTC 0
 18  #endif
 19  
 20  #ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
 21  #define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x2000
 22  #else
 23  #define CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE 0x4000
 24  #endif
 25  
 26  #ifdef CONFIG_ESP32S2_DATA_CACHE_0KB
 27  #define CONFIG_ESP32S2_DATA_CACHE_SIZE 0
 28  #elif defined CONFIG_ESP32S2_DATA_CACHE_8KB
 29  #define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x2000
 30  #else
 31  #define CONFIG_ESP32S2_DATA_CACHE_SIZE 0x4000
 32  #endif
 33  
 34  #define RAM_IRAM_START    0x40020000
 35  #define RAM_DRAM_START    0x3FFB0000
 36  
 37  #define DATA_RAM_END      0x3FFE0000  /* 2nd stage bootloader iram_loader_seg starts at SRAM block 14 (reclaimed after app boots) */
 38  
 39  #define IRAM_ORG    (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
 40                                      + CONFIG_ESP32S2_DATA_CACHE_SIZE)
 41  
 42  #define DRAM_ORG    (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
 43                                      + CONFIG_ESP32S2_DATA_CACHE_SIZE)
 44  
 45  #define I_D_RAM_SIZE   DATA_RAM_END - DRAM_ORG
 46  
 47  #if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE)
 48  
 49  ASSERT((CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE <= I_D_RAM_SIZE),
 50            "Fixed static ram data does not fit.")
 51  
 52  #define STATIC_RAM_SIZE CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE
 53  
 54  #else
 55  #define STATIC_RAM_SIZE 0
 56  #endif
 57  
 58  MEMORY
 59  {
 60    /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
 61    of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
 62    are connected to the data port of the CPU and eg allow bytewise access. */
 63  
 64    /* IRAM for CPU.*/
 65    iram0_0_seg (RX) :                 org = IRAM_ORG, len = I_D_RAM_SIZE
 66  
 67  #ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 68    /* Even though the segment name is iram, it is actually mapped to flash
 69    */
 70    iram0_2_seg (RX) :                 org = 0x40080020, len = 0x780000-0x20
 71  
 72    /*
 73      (0x20 offset above is a convenience for the app binary image generation.
 74      Flash cache has 64KB pages. The .bin file which is flashed to the chip
 75      has a 0x18 byte file header, and each segment has a 0x08 byte segment
 76      header. Setting this offset makes it simple to meet the flash cache MMU's
 77      constraint that (paddr % 64KB == vaddr % 64KB).)
 78    */
 79  #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 80  
 81  
 82    /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */
 83    dram0_0_seg (RW) :                 org = DRAM_ORG, len = I_D_RAM_SIZE - STATIC_RAM_SIZE
 84  
 85  #ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 86    /* Flash mapped constant data */
 87    drom0_0_seg (R) :                  org = 0x3F000020, len = 0x3f0000-0x20
 88  
 89    /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
 90  #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 91  
 92    /* RTC fast memory (executable). Persists over deep sleep.
 93     */
 94    rtc_iram_seg(RWX) :                org = 0x40070000, len = 0x2000
 95  
 96    /* RTC slow memory (data accessible). Persists over deep sleep.
 97  
 98       Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
 99    */
100    rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,
101                                       len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
102  
103    /* RTC fast memory (same block as above), viewed from data bus */
104    rtc_data_seg(RW) :                 org = 0x3ff9e000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC
105  }
106  
107  #if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE)
108  /* static data ends at defined address */
109  _static_data_end = DRAM_ORG + STATIC_RAM_SIZE;
110  #else
111  _static_data_end = _bss_end;
112  #endif
113  
114  _heap_end = 0x40000000;
115  
116  _data_seg_org = ORIGIN(rtc_data_seg);
117  
118  /* The lines below define location alias for .rtc.data section based on Kconfig option.
119     When the option is not defined then use slow memory segment
120     else the data will be placed in fast memory segment
121     TODO: check whether the rtc_data_location is correct for esp32s2 - IDF-761 */
122  #ifndef CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM
123  REGION_ALIAS("rtc_data_location", rtc_slow_seg );
124  #else
125  REGION_ALIAS("rtc_data_location", rtc_data_seg );
126  #endif
127  
128  #ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
129    REGION_ALIAS("default_code_seg", iram0_2_seg);
130  #else
131    REGION_ALIAS("default_code_seg", iram0_0_seg);
132  #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
133  
134  #ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
135    REGION_ALIAS("default_rodata_seg", drom0_0_seg);
136  #else
137    REGION_ALIAS("default_rodata_seg", dram0_0_seg);
138  #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS