spiram_psram.c
1 /* 2 Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip). 3 */ 4 5 // Copyright 2013-2017 Espressif Systems (Shanghai) PTE LTD 6 // 7 // Licensed under the Apache License, Version 2.0 (the "License"); 8 // you may not use this file except in compliance with the License. 9 // You may obtain a copy of the License at 10 // 11 // http://www.apache.org/licenses/LICENSE-2.0 12 // 13 // Unless required by applicable law or agreed to in writing, software 14 // distributed under the License is distributed on an "AS IS" BASIS, 15 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 // See the License for the specific language governing permissions and 17 // limitations under the License. 18 19 20 #include "sdkconfig.h" 21 #include "string.h" 22 #include "esp_attr.h" 23 #include "esp_err.h" 24 #include "esp_types.h" 25 #include "esp_log.h" 26 #include "spiram_psram.h" 27 #include "esp32s2/rom/spi_flash.h" 28 #include "esp32s2/rom/opi_flash.h" 29 #include "esp32s2/rom/cache.h" 30 #include "esp32s2/rom/efuse.h" 31 #include "esp_rom_efuse.h" 32 #include "soc/dport_reg.h" 33 #include "soc/efuse_periph.h" 34 #include "soc/soc_caps.h" 35 #include "soc/io_mux_reg.h" 36 #include "soc/apb_ctrl_reg.h" 37 #include "soc/efuse_reg.h" 38 #include "soc/soc.h" 39 #include "driver/gpio.h" 40 #include "driver/spi_common_internal.h" 41 #include "driver/spi_common.h" 42 #include "driver/periph_ctrl.h" 43 #include "bootloader_common.h" 44 45 #if CONFIG_SPIRAM 46 #include "soc/rtc.h" 47 48 static const char* TAG = "psram"; 49 50 //Commands for PSRAM chip 51 #define PSRAM_READ 0x03 52 #define PSRAM_FAST_READ 0x0B 53 #define PSRAM_FAST_READ_DUMMY 0x3 54 #define PSRAM_FAST_READ_QUAD 0xEB 55 #define PSRAM_FAST_READ_QUAD_DUMMY 0x5 56 #define PSRAM_WRITE 0x02 57 #define PSRAM_QUAD_WRITE 0x38 58 #define PSRAM_ENTER_QMODE 0x35 59 #define PSRAM_EXIT_QMODE 0xF5 60 #define PSRAM_RESET_EN 0x66 61 #define PSRAM_RESET 0x99 62 #define PSRAM_SET_BURST_LEN 0xC0 63 #define PSRAM_DEVICE_ID 0x9F 64 // ID 65 #define PSRAM_ID_KGD_M 0xff 66 #define PSRAM_ID_KGD_S 8 67 #define PSRAM_ID_KGD 0x5d 68 #define PSRAM_ID_EID_M 0xff 69 #define PSRAM_ID_EID_S 16 70 71 // Use the [7:5](bit7~bit5) of EID to distinguish the psram size: 72 // 73 // BIT7 | BIT6 | BIT5 | SIZE(MBIT) 74 // ------------------------------------- 75 // 0 | 0 | 0 | 16 76 // 0 | 0 | 1 | 32 77 // 0 | 1 | 0 | 64 78 #define PSRAM_EID_SIZE_M 0x07 79 #define PSRAM_EID_SIZE_S 5 80 81 #define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) 82 #define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) 83 #define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M) 84 #define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) 85 86 // For the old version 32Mbit psram, using the spicial driver */ 87 #define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20) 88 #define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26) 89 90 // IO-pins for PSRAM. 91 // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines 92 // hardcode the flash pins as well, making this code incompatible with either a setup 93 // that has the flash on non-standard pins or ESP32s with built-in flash. 94 #define FLASH_CLK_IO SPI_CLK_GPIO_NUM 95 #define FLASH_CS_IO SPI_CS0_GPIO_NUM 96 // PSRAM clock and cs IO should be configured based on hardware design. 97 #define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 98 #define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 99 #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM 100 #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM 101 #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM 102 #define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM 103 104 #define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M 105 #define CS_FLASH_SEL SPI_MEM_CS0_DIS_M 106 107 #define PSRAM_IO_MATRIX_DUMMY_20M 0 108 #define PSRAM_IO_MATRIX_DUMMY_40M 0 109 #define PSRAM_IO_MATRIX_DUMMY_80M 0 110 #define _SPI_CACHE_PORT 0 111 #define _SPI_FLASH_PORT 1 112 #define _SPI_80M_CLK_DIV 1 113 #define _SPI_40M_CLK_DIV 2 114 #define _SPI_20M_CLK_DIV 4 115 116 typedef enum { 117 PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */ 118 PSRAM_CLK_MODE_A1C, /*!< ONE extra clock cycles after CS is set high level */ 119 PSRAM_CLK_MODE_A2C, /*!< Two extra clock cycles after CS is set high level */ 120 PSRAM_CLK_MODE_ALON, /*!< clock always on */ 121 PSRAM_CLK_MODE_MAX, 122 } psram_clk_mode_t; 123 124 125 typedef enum { 126 PSRAM_EID_SIZE_16MBITS = 0, 127 PSRAM_EID_SIZE_32MBITS = 1, 128 PSRAM_EID_SIZE_64MBITS = 2, 129 } psram_eid_size_t; 130 131 typedef struct { 132 uint8_t flash_clk_io; 133 uint8_t flash_cs_io; 134 uint8_t psram_clk_io; 135 uint8_t psram_cs_io; 136 uint8_t psram_spiq_sd0_io; 137 uint8_t psram_spid_sd1_io; 138 uint8_t psram_spiwp_sd3_io; 139 uint8_t psram_spihd_sd2_io; 140 } psram_io_t; 141 142 #define PSRAM_IO_CONF_DEFAULT() { \ 143 .flash_clk_io = FLASH_CLK_IO, \ 144 .flash_cs_io = FLASH_CS_IO, \ 145 .psram_clk_io = PSRAM_CLK_IO, \ 146 .psram_cs_io = PSRAM_CS_IO, \ 147 .psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO, \ 148 .psram_spid_sd1_io = PSRAM_SPID_SD1_IO, \ 149 .psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO, \ 150 .psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \ 151 } 152 153 typedef enum { 154 PSRAM_SPI_1 = 0x1, 155 /* PSRAM_SPI_2, */ 156 /* PSRAM_SPI_3, */ 157 PSRAM_SPI_MAX , 158 } psram_spi_num_t; 159 160 typedef enum { 161 PSRAM_CMD_QPI, 162 PSRAM_CMD_SPI, 163 } psram_cmd_mode_t; 164 165 typedef esp_rom_spi_cmd_t psram_cmd_t; 166 167 static uint32_t s_psram_id = 0; 168 static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode); 169 extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); 170 171 static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode) 172 { 173 if (mode == PSRAM_CMD_QPI) { 174 esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE); 175 SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); 176 } else if (mode == PSRAM_CMD_SPI) { 177 esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE); 178 } 179 } 180 static void _psram_exec_cmd(int spi_num, 181 uint32_t cmd, int cmd_bit_len, 182 uint32_t addr, int addr_bit_len, 183 int dummy_bits, 184 uint8_t* mosi_data, int mosi_bit_len, 185 uint8_t* miso_data, int miso_bit_len) 186 { 187 esp_rom_spi_cmd_t conf; 188 uint32_t _addr = addr; 189 conf.addr = &_addr; 190 conf.addrBitLen = addr_bit_len; 191 conf.cmd = cmd; 192 conf.cmdBitLen = cmd_bit_len; 193 conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723 194 conf.txData = (uint32_t*) mosi_data; 195 conf.txDataBitLen = mosi_bit_len; 196 conf.rxData = (uint32_t*) miso_data; 197 conf.rxDataBitLen = miso_bit_len; 198 esp_rom_spi_cmd_config(spi_num, &conf); 199 } 200 201 void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, 202 uint32_t cmd, int cmd_bit_len, 203 uint32_t addr, int addr_bit_len, 204 int dummy_bits, 205 uint8_t* mosi_data, int mosi_bit_len, 206 uint8_t* miso_data, int miso_bit_len, 207 uint32_t cs_mask, 208 bool is_write_erase_operation) 209 { 210 uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); 211 uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); 212 uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); 213 uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); 214 psram_set_op_mode(spi_num, mode); 215 _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len, 216 dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len); 217 esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation); 218 219 WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); 220 WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1); 221 WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2); 222 WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl); 223 } 224 225 //exit QPI mode(set back to SPI mode) 226 static void psram_disable_qio_mode(int spi_num) 227 { 228 psram_exec_cmd(spi_num, PSRAM_CMD_QPI, 229 PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ 230 0, 0, /* address and address bit len*/ 231 0, /* dummy bit len */ 232 NULL, 0, /* tx data and tx bit len*/ 233 NULL, 0, /* rx data and rx bit len*/ 234 CS_PSRAM_SEL, /* cs bit mask*/ 235 false); /* whether is program/erase operation */ 236 } 237 238 //switch psram burst length(32 bytes or 1024 bytes) 239 //datasheet says it should be 1024 bytes by default 240 static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode) 241 { 242 psram_exec_cmd(spi_num, mode, 243 PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ 244 0, 0, /* address and address bit len*/ 245 0, /* dummy bit len */ 246 NULL, 0, /* tx data and tx bit len*/ 247 NULL, 0, /* rx data and rx bit len*/ 248 CS_PSRAM_SEL, /* cs bit mask*/ 249 false); /* whether is program/erase operation */ 250 } 251 252 //send reset command to psram, in spi mode 253 static void psram_reset_mode(int spi_num) 254 { 255 psram_exec_cmd(spi_num, PSRAM_CMD_SPI, 256 PSRAM_RESET_EN, 8, /* command and command bit len*/ 257 0, 0, /* address and address bit len*/ 258 0, /* dummy bit len */ 259 NULL, 0, /* tx data and tx bit len*/ 260 NULL, 0, /* rx data and rx bit len*/ 261 CS_PSRAM_SEL, /* cs bit mask*/ 262 false); /* whether is program/erase operation */ 263 264 psram_exec_cmd(spi_num, PSRAM_CMD_SPI, 265 PSRAM_RESET, 8, /* command and command bit len*/ 266 0, 0, /* address and address bit len*/ 267 0, /* dummy bit len */ 268 NULL, 0, /* tx data and tx bit len*/ 269 NULL, 0, /* rx data and rx bit len*/ 270 CS_PSRAM_SEL, /* cs bit mask*/ 271 false); /* whether is program/erase operation */ 272 } 273 274 esp_err_t psram_enable_wrap(uint32_t wrap_size) 275 { 276 static int current_wrap_size = 0; 277 if (current_wrap_size == wrap_size) { 278 return ESP_OK; 279 } 280 switch (wrap_size) { 281 case 32: 282 case 0: 283 psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI); 284 current_wrap_size = wrap_size; 285 return ESP_OK; 286 case 16: 287 case 64: 288 default: 289 return ESP_FAIL; 290 } 291 } 292 293 bool psram_support_wrap_size(uint32_t wrap_size) 294 { 295 switch (wrap_size) { 296 case 0: 297 case 32: 298 return true; 299 case 16: 300 case 64: 301 default: 302 return false; 303 } 304 305 } 306 307 //read psram id, should issue `psram_disable_qio_mode` before calling this 308 static void psram_read_id(int spi_num, uint32_t* dev_id) 309 { 310 psram_exec_cmd(spi_num, PSRAM_CMD_SPI, 311 PSRAM_DEVICE_ID, 8, /* command and command bit len*/ 312 0, 24, /* address and address bit len*/ 313 0, /* dummy bit len */ 314 NULL, 0, /* tx data and tx bit len*/ 315 (uint8_t*) dev_id, 24, /* rx data and rx bit len*/ 316 CS_PSRAM_SEL, /* cs bit mask*/ 317 false); /* whether is program/erase operation */ 318 } 319 320 //enter QPI mode 321 static void IRAM_ATTR psram_enable_qio_mode(int spi_num) 322 { 323 psram_exec_cmd(spi_num, PSRAM_CMD_SPI, 324 PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ 325 0, 0, /* address and address bit len*/ 326 0, /* dummy bit len */ 327 NULL, 0, /* tx data and tx bit len*/ 328 NULL, 0, /* rx data and rx bit len*/ 329 CS_PSRAM_SEL, /* cs bit mask*/ 330 false); /* whether is program/erase operation */ 331 } 332 333 static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode) 334 { 335 if (clk_mode == PSRAM_CLK_MODE_NORM) { 336 // SPI1 Flash Operation port 337 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S); 338 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); 339 SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); 340 } else { 341 SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); 342 } 343 } 344 345 static void psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode) 346 { 347 if (clk_mode == PSRAM_CLK_MODE_NORM) { 348 // SPI0 SRAM Cache port 349 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 1, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); 350 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); 351 SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M); 352 // SPI0 Flash Cache port 353 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); 354 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); 355 SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); 356 } else { 357 CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_CS_HOLD_M | SPI_CS_SETUP_M); 358 } 359 } 360 361 //psram gpio init , different working frequency we have different solutions 362 static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) 363 { 364 psram_io_t psram_io = PSRAM_IO_CONF_DEFAULT(); 365 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); 366 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { 367 /* FLASH pins(except wp / hd) are all configured via IO_MUX in rom. */ 368 } else { 369 // FLASH pins are all configured via GPIO matrix in ROM. 370 psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig); 371 psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig); 372 psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig); 373 psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig); 374 psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig); 375 psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio(); 376 } 377 esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig); 378 } 379 380 psram_size_t psram_get_size(void) 381 { 382 if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) { 383 return PSRAM_SIZE_64MBITS; 384 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) { 385 return PSRAM_SIZE_32MBITS; 386 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) { 387 return PSRAM_SIZE_16MBITS; 388 } else { 389 return PSRAM_SIZE_MAX; 390 } 391 return PSRAM_SIZE_MAX; 392 } 393 394 //used in UT only 395 bool psram_is_32mbit_ver0(void) 396 { 397 return PSRAM_IS_32MBIT_VER0(s_psram_id); 398 } 399 400 static void psram_set_clk_mode(int spi_num, psram_clk_mode_t clk_mode) 401 { 402 if (spi_num == _SPI_CACHE_PORT) { 403 REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, clk_mode); 404 } else if (spi_num == _SPI_FLASH_PORT) { 405 REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, clk_mode); 406 } 407 } 408 409 /* 410 * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA. 411 * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode. 412 */ 413 esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init 414 { 415 assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now."); 416 // GPIO related settings 417 psram_gpio_config(mode); 418 419 /* SPI1: set spi1 clk mode, in order to send commands on SPI1 */ 420 /* SPI1: set cs timing(hold time) in order to send commands on SPI1 */ 421 psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C); 422 psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C); 423 424 int spi_num = PSRAM_SPI_1; 425 psram_disable_qio_mode(spi_num); 426 psram_read_id(spi_num, &s_psram_id); 427 if (!PSRAM_IS_VALID(s_psram_id)) { 428 /* 16Mbit psram ID read error workaround: 429 * treat the first read id as a dummy one as the pre-condition, 430 * Send Read ID command again 431 */ 432 psram_read_id(spi_num, &s_psram_id); 433 if (!PSRAM_IS_VALID(s_psram_id)) { 434 ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id); 435 return ESP_FAIL; 436 } 437 } 438 439 psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX; 440 if (psram_is_32mbit_ver0()) { 441 clk_mode = PSRAM_CLK_MODE_A1C; 442 // SPI1: keep clock mode and cs timing for spi1 443 } else { 444 // For other psram, we don't need any extra clock cycles after cs get back to high level 445 clk_mode = PSRAM_CLK_MODE_NORM; 446 // SPI1: set clock mode and cs timing to normal mode 447 psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); 448 psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); 449 } 450 451 /* SPI1: send psram reset command */ 452 /* SPI1: send QPI enable command */ 453 psram_reset_mode(PSRAM_SPI_1); 454 psram_enable_qio_mode(PSRAM_SPI_1); 455 456 // after sending commands, set spi1 clock mode and cs timing to normal mode. 457 // since all the operations are sent via SPI0 Cache 458 /* SPI1: set clock mode to normal mode. */ 459 /* SPI1: set cs timing to normal */ 460 psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM); 461 psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM); 462 463 /* SPI0: set spi0 clock mode */ 464 /* SPI0: set spi0 flash/cache cs timing */ 465 psram_set_clk_mode(_SPI_CACHE_PORT, clk_mode); 466 psram_set_spi0_cache_cs_timing(clk_mode); 467 468 // SPI0: init SPI commands for Cache 469 psram_cache_init(mode, vaddrmode); 470 471 return ESP_OK; 472 } 473 474 static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv) 475 { 476 uint32_t freqbits; 477 if (1 >= freqdiv) { 478 WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK); 479 } else { 480 freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S); 481 WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits); 482 } 483 } 484 485 //register initialization for sram cache params and r/w commands 486 static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode) 487 { 488 int extra_dummy = 0; 489 switch (psram_cache_mode) { 490 case PSRAM_CACHE_S80M: 491 psram_clock_set(0, 1); 492 extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M; 493 break; 494 case PSRAM_CACHE_S40M: 495 psram_clock_set(0, 2); 496 extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M; 497 break; 498 case PSRAM_CACHE_S26M: 499 psram_clock_set(0, 3); 500 extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M; 501 break; 502 case PSRAM_CACHE_S20M: 503 psram_clock_set(0, 4); 504 extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M; 505 break; 506 default: 507 psram_clock_set(0, 2); 508 break; 509 } 510 511 CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command 512 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command 513 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command 514 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command 515 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S); //write address for cache command. 516 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy 517 518 //config sram cache r/w command 519 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, 520 SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S); 521 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, 522 SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38 523 SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, 524 SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S); 525 SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, 526 SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b 527 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy, 528 SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy 529 530 #if !CONFIG_FREERTOS_UNICORE 531 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT); 532 DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT); 533 if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) { 534 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL); 535 DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL); 536 } else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) { 537 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT); 538 DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT); 539 } 540 #endif 541 542 CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) 543 } 544 #endif // CONFIG_SPIRAM