1  // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 2  //
 3  // Licensed under the Apache License, Version 2.0 (the "License");
 4  // you may not use this file except in compliance with the License.
 5  // You may obtain a copy of the License at
 6  //
 7  //     http://www.apache.org/licenses/LICENSE-2.0
 8  //
 9  // Unless required by applicable law or agreed to in writing, software
10  // distributed under the License is distributed on an "AS IS" BASIS,
11  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  // See the License for the specific language governing permissions and
13  // limitations under the License.
14  
15  /**
16   * @file cache_err_int.c
17   * @brief The cache has an interrupt that can be raised as soon as an access to a cached
18   *        region (Flash, PSRAM) is done without the cache being enabled.
19   *        We use that here to panic the CPU, which from a debugging perspective,
20   *        is better than grabbing bad data from the bus.
21   */
22  
23  #include <stdint.h>
24  #include "sdkconfig.h"
25  #include "esp_err.h"
26  #include "esp_attr.h"
27  #include "esp_intr_alloc.h"
28  #include "soc/soc.h"
29  #include "soc/extmem_reg.h"
30  #include "soc/periph_defs.h"
31  #include "hal/cpu_hal.h"
32  #include "esp32s3/dport_access.h"
33  #include "esp32s3/rom/ets_sys.h"
34  
35  void esp_cache_err_int_init(void)
36  {
37      uint32_t core_id = cpu_hal_get_core_id();
38      ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
39  
40      // We do not register a handler for the interrupt because it is interrupt
41      // level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
42      // a call to the panic handler for this interrupt.
43      intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
44  
45      // Enable invalid cache access interrupt when the cache is disabled.
46      // When the interrupt happens, we can not determine the CPU where the
47      // invalid cache access has occurred. We enable the interrupt to catch
48      // invalid access on both CPUs, but the interrupt is connected to the
49      // CPU which happens to call this function.
50      // For this reason, panic handler backtrace will not be correct if the
51      // interrupt is connected to PRO CPU and invalid access happens on the APP CPU.
52  
53      SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG,
54                        EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
55                        EXTMEM_DCACHE_WRITE_FLASH_INT_CLR |
56                        EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR |
57                        EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR |
58                        EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR |
59                        EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR);
60      SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG,
61                        EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
62                        EXTMEM_DCACHE_WRITE_FLASH_INT_ENA |
63                        EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA |
64                        EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA |
65                        EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA |
66                        EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);
67  
68      ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
69  }
70  
71  int IRAM_ATTR esp_cache_err_get_cpuid(void)
72  {
73      // FIXME
74      return -1;
75  }