1  // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
 2  //
 3  // Licensed under the Apache License, Version 2.0 (the "License");
 4  // you may not use this file except in compliance with the License.
 5  // You may obtain a copy of the License at
 6  //
 7  //     http://www.apache.org/licenses/LICENSE-2.0
 8  //
 9  // Unless required by applicable law or agreed to in writing, software
10  // distributed under the License is distributed on an "AS IS" BASIS,
11  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  // See the License for the specific language governing permissions and
13  // limitations under the License.
14  
15  #include "esp_attr.h"
16  #include "soc/cpu.h"
17  #include "soc/soc.h"
18  #include "soc/rtc_periph.h"
19  #include "sdkconfig.h"
20  
21  #include "hal/cpu_hal.h"
22  #include "esp_debug_helpers.h"
23  #include "hal/cpu_types.h"
24  
25  #include "hal/soc_hal.h"
26  #include "soc/soc_caps.h"
27  
28  #include "sdkconfig.h"
29  
30  void IRAM_ATTR esp_cpu_stall(int cpu_id)
31  {
32  #if SOC_CPU_CORES_NUM > 1
33      soc_hal_stall_core(cpu_id);
34  #endif
35  }
36  
37  void IRAM_ATTR esp_cpu_unstall(int cpu_id)
38  {
39  #if SOC_CPU_CORES_NUM > 1
40      soc_hal_unstall_core(cpu_id);
41  #endif
42  }
43  
44  void IRAM_ATTR esp_cpu_reset(int cpu_id)
45  {
46      soc_hal_reset_core(cpu_id);
47  }
48  
49  esp_err_t IRAM_ATTR esp_set_watchpoint(int no, void *adr, int size, int flags)
50  {
51      watchpoint_trigger_t trigger;
52  
53      switch (flags)
54      {
55      case ESP_WATCHPOINT_LOAD:
56          trigger = WATCHPOINT_TRIGGER_ON_RO;
57          break;
58      case ESP_WATCHPOINT_STORE:
59          trigger = WATCHPOINT_TRIGGER_ON_WO;
60          break;
61      case ESP_WATCHPOINT_ACCESS:
62          trigger = WATCHPOINT_TRIGGER_ON_RW;
63          break;
64      default:
65          return ESP_ERR_INVALID_ARG;
66      }
67  
68      cpu_hal_set_watchpoint(no, adr, size, trigger);
69      return ESP_OK;
70  }
71  
72  void IRAM_ATTR esp_clear_watchpoint(int no)
73  {
74      cpu_hal_clear_watchpoint(no);
75  }
76  
77  bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
78  {
79  #if (CONFIG_ESP32_DEBUG_OCDAWARE == 1) || \
80      (CONFIG_ESP32S2_DEBUG_OCDAWARE == 1)
81      return cpu_ll_is_debugger_attached();
82  #else
83      return false; // Always return false if "OCD aware" is disabled
84  #endif
85  }
86  
87  void IRAM_ATTR esp_set_breakpoint_if_jtag(void *fn)
88  {
89      if (esp_cpu_in_ocd_debug_mode()) {
90          cpu_hal_set_breakpoint(0, fn);
91      }
92  }