xtensa_perfmon_masks.c
1 // Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Descriptions have been adapted from the comments in xt_perf_const.h, 4 // licensed under MIT license and copyright by Tensilica Inc. 5 // 6 // Licensed under the Apache License, Version 2.0 (the "License"); 7 // you may not use this file except in compliance with the License. 8 // You may obtain a copy of the License at 9 // 10 // http://www.apache.org/licenses/LICENSE-2.0 11 // 12 // Unless required by applicable law or agreed to in writing, software 13 // distributed under the License is distributed on an "AS IS" BASIS, 14 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 // See the License for the specific language governing permissions and 16 // limitations under the License. 17 18 #include "xtensa_perfmon_masks.h" 19 20 const xtensa_perfmon_select_t xtensa_perfmon_select_table[] = { 21 // select, description 22 {XTPERF_CNT_CYCLES, "Counts cycles"}, 23 {XTPERF_CNT_OVERFLOW, "Overflow of counter"}, 24 {XTPERF_CNT_INSN, "Successfully Retired Instructions"}, 25 {XTPERF_CNT_D_STALL, "Data-related GlobalStall cycles"}, 26 {XTPERF_CNT_I_STALL, "Instruction-related and Other GlobalStall cycles"}, 27 {XTPERF_CNT_EXR, "Exceptions and Pipeline Replays"}, 28 {XTPERF_CNT_BUBBLES, "Hold and Other Bubble cycles"}, 29 {XTPERF_CNT_I_TLB, "Instruction TLB Accesses (per instruction retiring)"}, 30 {XTPERF_CNT_I_MEM, "Instruction Memory Accesses (per instruction retiring)"}, 31 {XTPERF_CNT_D_TLB, "Data TLB Accesses"}, 32 {XTPERF_CNT_D_LOAD_U1, "Load Instruction (Data Memory)"}, 33 {XTPERF_CNT_D_LOAD_U2, "Load Instruction (Data Memory)"}, 34 {XTPERF_CNT_D_LOAD_U3, "Load Instruction (Data Memory)"}, 35 {XTPERF_CNT_D_STORE_U1, "Store Instruction (Data Memory)"}, 36 {XTPERF_CNT_D_STORE_U2, "Store Instruction (Data Memory)"}, 37 {XTPERF_CNT_D_STORE_U3, "Store Instruction (Data Memory)"}, 38 {XTPERF_CNT_D_ACCESS_U1, "Accesses to Data Memory (Load, Store, S32C1I, ...)"}, 39 {XTPERF_CNT_D_ACCESS_U2, "Accesses to Data Memory (Load, Store, S32C1I, ...)"}, 40 {XTPERF_CNT_D_ACCESS_U3, "Accesses to Data Memory (Load, Store, S32C1I, ...)"}, 41 {XTPERF_CNT_MULTIPLE_LS, "Multiple Load/Store"}, 42 {XTPERF_CNT_OUTBOUND_PIF, "Outbound PIF"}, 43 {XTPERF_CNT_INBOUND_PIF, "Inbound PIF"}, 44 {XTPERF_CNT_PREFETCH, "Prefetch"}, 45 #if XCHAL_HW_VERSION >= 270004 46 {XTPERF_CNT_IDMA, "iDMA"}, 47 {XTPERF_CNT_INSN_LENGTH, "Length of Instructions"}, 48 #endif 49 {-1, ""}, 50 }; 51 52 const xtensa_perfmon_masks_t xtensa_perfmon_masks_table[] = { 53 // select, mask, description 54 {XTPERF_CNT_CYCLES, 1, "Amount of cycles"}, 55 {XTPERF_CNT_OVERFLOW, 1, "Overflow counter"}, 56 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_JX, "JX instructions"}, 57 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_CALLX, "CALLXn instructions"}, 58 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_RET, "return instructions (RET, RETW, ...)"}, 59 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_RF, "supervisor return instructions (RFDE, RFE, RFI, RFWO, RFWU)"}, 60 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, "Conditional branch instructions where execution"}, 61 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, "transfers to the target (aka. taken branch),"}, 62 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, " or loopgtz/loopnez instr where execution skips"}, 63 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, " the loop (aka. not-taken loop)"}, 64 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_J, "J instr"}, 65 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_CALL, "CALLn instr"}, 66 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_NOT_TAKEN, "Conditional branch instr where execution"}, 67 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_NOT_TAKEN, " falls through (aka. not-taken branch)"}, 68 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_TAKEN, "Loop instr where execution falls into loop (aka. taken loop)"}, 69 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_BEG, "Last inst of loop and execution transfers"}, 70 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_BEG, " to LBEG (aka. loopback taken)"}, 71 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_END, "Last inst of loop and execution falls "}, 72 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_END, " through to LEND (aka. loopback fallthrough)"}, 73 {XTPERF_CNT_INSN, XTPERF_MASK_INSN_NON_BRANCH, "Non-branch instr (aka. non-CTI)"}, 74 {XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_STORE_BUF_FULL, "Store buffer full stall"}, 75 {XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT, "Store buffer conflict stall"}, 76 {XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_CACHE_MISS, "Data Cache-miss stall (unused)"}, 77 {XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_BUSY, "Data RAM/ROM/XLMI busy stall"}, 78 {XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_IN_PIF, "Data inbound-PIF request stall (includes s32c1i)"}, 79 {XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_MHT_LOOKUP, "MHT lookup stall"}, 80 {XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_UNCACHED_LOAD, "Uncached load stall (included in MHT lookup stall below)"}, 81 {XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_BANK_CONFLICT, "Bank-conflict stall"}, 82 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_CACHE_MISS, "ICache-miss stall"}, 83 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_BUSY, "Instruction RAM/ROM busy stall"}, 84 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_IN_PIF, "Instruction RAM inbound-PIF request stall"}, 85 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_TIE_PORT, "TIE port stall"}, 86 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL, "External RunStall signal status"}, 87 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_UNCACHED_FETCH, "Uncached fetch stall"}, 88 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_FAST_L32R, "FastL32R stall"}, 89 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_ITERATIVE_MUL, "Iterative multiply stall"}, 90 {XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_ITERATIVE_DIV, "Iterative divide stall"}, 91 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_REPLAYS, "Other Pipeline Replay (i.e. excludes cache miss etc.)"}, 92 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_LEVEL1_INT, "Level-1 interrupt"}, 93 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_LEVELH_INT, "Greater-than-level-1 interrupt"}, 94 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_DEBUG, "Debug exception"}, 95 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_NMI, "NMI"}, 96 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_WINDOW, "Window exception"}, 97 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_ALLOCA, "Allocate exception"}, 98 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_OTHER, "Other exceptions"}, 99 {XTPERF_CNT_EXR, XTPERF_MASK_EXR_MEM_ERR, "HW-corrected memory error"}, 100 {XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_PSO, "Processor domain PSO bubble"}, 101 {XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS, "R hold caused by Data Cache miss(unused)"}, 102 {XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE, "R hold caused by Store release"}, 103 {XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP, "R hold caused by register dependency"}, 104 {XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_WAIT, "R hold caused by MEMW, EXTW or EXCW"}, 105 {XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_HALT, "R hold caused by Halt instruction (TX only)"}, 106 {XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_CTI, "CTI bubble (e.g. branch delay slot)"}, 107 {XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_WAITI, "WAITI bubble i.e. a cycle spent in WaitI power down mode."}, 108 {XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_HITS, "ITLB Hit"}, 109 {XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_REPLAYS, "Replay of instruction due to ITLB miss"}, 110 {XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_REFILLS, "HW-assisted TLB Refill completes"}, 111 {XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_MISSES, "ITLB Miss Exception"}, 112 {XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_CACHE_HITS, "Instruction Cache Hit"}, 113 {XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_CACHE_MISSES, "Instruction Cache Miss"}, 114 {XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_IRAM, "All InstRAM or InstROM accesses"}, 115 {XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_BYPASS, "Bypass (i.e. uncached) fetch"}, 116 {XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_HITS, "DTLB Hit"}, 117 {XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_REPLAYS, "Replay of load/store due to DTLB miss"}, 118 {XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_REFILLS, "HW-assisted TLB Refill completes"}, 119 {XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_MISSES, "DTLB Miss Exception"}, 120 {XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_CACHE_HITS, "Data Cache Hit(unused)"}, 121 {XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_CACHE_MISSES, "Data Cache Miss(unused)"}, 122 {XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_LOCAL_MEM, "Load from local memory i.e. DataRAM, DataROM, InstRAM, InstROM"}, 123 {XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_BYPASS, "Bypass (i.e. uncached) load"}, 124 {XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_CACHE_HITS, "Data Cache Hit(unused)"}, 125 {XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_CACHE_MISSES, "Data Cache Miss(unused)"}, 126 {XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_LOCAL_MEM, "Load from local memory i.e. DataRAM, DataROM, InstRAM, InstROM"}, 127 {XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_BYPASS, "Bypass (i.e. uncached) load"}, 128 {XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_CACHE_HITS, "Data Cache Hit (unused)"}, 129 {XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_CACHE_MISSES, "Data Cache Miss (unused)"}, 130 {XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_LOCAL_MEM, "Load from local memory i.e. DataRAM, DataROM, InstRAM, InstROM"}, 131 {XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_BYPASS, "Bypass (i.e. uncached) load"}, 132 {XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_CACHE_HITS, "Data Cache Hit (unused)"}, 133 {XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_CACHE_MISSES, "Data Cache Miss (unused)"}, 134 {XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_LOCAL_MEM, "Store to local memory i.e. DataRAM, InstRAM"}, 135 {XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_PIF, "PIF Store"}, 136 {XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_CACHE_HITS, "Data Cache Hit(unused)"}, 137 {XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_CACHE_MISSES, "Data Cache Miss(unused)"}, 138 {XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_LOCAL_MEM, "Store to local memory i.e. DataRAM, InstRAM"}, 139 {XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_PIF, "PIF Store"}, 140 {XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_CACHE_HITS, "Data Cache Hit (unused)"}, 141 {XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_CACHE_MISSES, "Data Cache Miss (unused)"}, 142 {XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_LOCAL_MEM, "Store to local memory i.e. DataRAM, InstRAM"}, 143 {XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_PIF, "PIF Store"}, 144 {XTPERF_CNT_D_ACCESS_U1, XTPERF_MASK_D_ACCESS_CACHE_MISSES, "Cache Miss"}, 145 {XTPERF_CNT_D_ACCESS_U2, XTPERF_MASK_D_ACCESS_CACHE_MISSES, "Cache Miss"}, 146 {XTPERF_CNT_D_ACCESS_U3, XTPERF_MASK_D_ACCESS_CACHE_MISSES, "Cache Miss"}, 147 {XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_0L, "0 stores and 0 loads"}, 148 {XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_1L, "0 stores and 1 loads"}, 149 {XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_1S_0L, "1 stores and 0 loads"}, 150 {XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_1S_1L, "1 stores and 1 loads"}, 151 {XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_2L, "0 stores and 2 loads"}, 152 {XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_2S_0L, "2 stores and 0 loads"}, 153 {XTPERF_CNT_OUTBOUND_PIF, XTPERF_MASK_OUTBOUND_PIF_CASTOUT, "Castout"}, 154 {XTPERF_CNT_OUTBOUND_PIF, XTPERF_MASK_OUTBOUND_PIF_PREFETCH, "Prefetch"}, 155 {XTPERF_CNT_INBOUND_PIF, XTPERF_MASK_INBOUND_PIF_I_DMA, "Data DMA"}, 156 {XTPERF_CNT_INBOUND_PIF, XTPERF_MASK_INBOUND_PIF_D_DMA, "Instruction DMA"}, 157 {XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_HIT, "I prefetch-buffer-lookup hit"}, 158 {XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_HIT, "D prefetch-buffer-lookup hit"}, 159 {XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_MISS, "I prefetch-buffer-lookup miss"}, 160 {XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_MISS, "D prefetch-buffer-lookup miss"}, 161 {XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_L1_FILL, "Direct fill to (L1) Data Cache (unused)"}, 162 #if XCHAL_HW_VERSION >= 270004 163 {XTPERF_CNT_IDMA, XTPERF_MASK_IDMA_ACTIVE_CYCLES, "active cycles"}, 164 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_16, "16-bit"}, 165 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_24, "24-bit"}, 166 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_32, "32-bit"}, 167 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_40, "40-bit"}, 168 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_48, "48-bit"}, 169 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_56, "56-bit"}, 170 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_64, "64-bit"}, 171 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_72, "72-bit"}, 172 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_80, "80-bit"}, 173 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_88, "88-bit"}, 174 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_96, "96-bit"}, 175 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_104, "104-bit"}, 176 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_112, "112-bit"}, 177 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_120, "120-bit"}, 178 {XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_128, "128-bit"}, 179 #endif 180 {-1, 0, ""}, 181 }; 182 183 // All availible combinations 184 const uint32_t xtensa_perfmon_select_mask_all[MAX_PERFMON_EVENTS * 2] = { 185 XTPERF_CNT_CYCLES, XTPERF_MASK_CYCLES, 186 XTPERF_CNT_OVERFLOW, XTPERF_MASK_OVERFLOW, 187 XTPERF_CNT_INSN, XTPERF_MASK_INSN_JX, 188 XTPERF_CNT_INSN, XTPERF_MASK_INSN_CALLX, 189 XTPERF_CNT_INSN, XTPERF_MASK_INSN_RET, 190 XTPERF_CNT_INSN, XTPERF_MASK_INSN_RF, 191 XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_TAKEN, 192 XTPERF_CNT_INSN, XTPERF_MASK_INSN_J, 193 XTPERF_CNT_INSN, XTPERF_MASK_INSN_CALL, 194 XTPERF_CNT_INSN, XTPERF_MASK_INSN_BRANCH_NOT_TAKEN, 195 XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_TAKEN, 196 XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_BEG, 197 XTPERF_CNT_INSN, XTPERF_MASK_INSN_LOOP_END, 198 XTPERF_CNT_INSN, XTPERF_MASK_INSN_NON_BRANCH, 199 XTPERF_CNT_INSN, XTPERF_MASK_INSN_ALL, 200 XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_STORE_BUF_FULL, 201 XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT, 202 XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_CACHE_MISS, 203 XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_BUSY, 204 XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_IN_PIF, 205 XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_MHT_LOOKUP, 206 XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_UNCACHED_LOAD, 207 XTPERF_CNT_D_STALL, XTPERF_MASK_D_STALL_BANK_CONFLICT, 208 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_CACHE_MISS, 209 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_BUSY, 210 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_IN_PIF, 211 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_TIE_PORT, 212 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL, 213 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_UNCACHED_FETCH, 214 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_FAST_L32R, 215 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_ITERATIVE_MUL, 216 XTPERF_CNT_I_STALL, XTPERF_MASK_I_STALL_ITERATIVE_DIV, 217 XTPERF_CNT_EXR, XTPERF_MASK_EXR_REPLAYS, 218 XTPERF_CNT_EXR, XTPERF_MASK_EXR_LEVEL1_INT, 219 XTPERF_CNT_EXR, XTPERF_MASK_EXR_LEVELH_INT, 220 XTPERF_CNT_EXR, XTPERF_MASK_EXR_DEBUG, 221 XTPERF_CNT_EXR, XTPERF_MASK_EXR_NMI, 222 XTPERF_CNT_EXR, XTPERF_MASK_EXR_WINDOW, 223 XTPERF_CNT_EXR, XTPERF_MASK_EXR_ALLOCA, 224 XTPERF_CNT_EXR, XTPERF_MASK_EXR_OTHER, 225 XTPERF_CNT_EXR, XTPERF_MASK_EXR_MEM_ERR, 226 XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_PSO, 227 XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS, 228 XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE, 229 XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP, 230 XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_WAIT, 231 XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_R_HOLD_HALT, 232 XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_CTI, 233 XTPERF_CNT_BUBBLES, XTPERF_MASK_BUBBLES_WAITI, 234 XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_HITS, 235 XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_REPLAYS, 236 XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_REFILLS, 237 XTPERF_CNT_I_TLB, XTPERF_MASK_I_TLB_MISSES, 238 XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_CACHE_HITS, 239 XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_CACHE_MISSES, 240 XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_IRAM, 241 XTPERF_CNT_I_MEM, XTPERF_MASK_I_MEM_BYPASS, 242 XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_HITS, 243 XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_REPLAYS, 244 XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_REFILLS, 245 XTPERF_CNT_D_TLB, XTPERF_MASK_D_TLB_MISSES, 246 XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_CACHE_HITS, 247 XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_CACHE_MISSES, 248 XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_LOCAL_MEM, 249 XTPERF_CNT_D_LOAD_U1, XTPERF_MASK_D_LOAD_BYPASS, 250 XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_CACHE_HITS, 251 XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_CACHE_MISSES, 252 XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_LOCAL_MEM, 253 XTPERF_CNT_D_LOAD_U2, XTPERF_MASK_D_LOAD_BYPASS, 254 XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_CACHE_HITS, 255 XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_CACHE_MISSES, 256 XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_LOCAL_MEM, 257 XTPERF_CNT_D_LOAD_U3, XTPERF_MASK_D_LOAD_BYPASS, 258 XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_CACHE_HITS, 259 XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_CACHE_MISSES, 260 XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_LOCAL_MEM, 261 XTPERF_CNT_D_STORE_U1, XTPERF_MASK_D_STORE_PIF, 262 XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_CACHE_HITS, 263 XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_CACHE_MISSES, 264 XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_LOCAL_MEM, 265 XTPERF_CNT_D_STORE_U2, XTPERF_MASK_D_STORE_PIF, 266 XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_CACHE_HITS, 267 XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_CACHE_MISSES, 268 XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_LOCAL_MEM, 269 XTPERF_CNT_D_STORE_U3, XTPERF_MASK_D_STORE_PIF, 270 XTPERF_CNT_D_ACCESS_U1, XTPERF_MASK_D_ACCESS_CACHE_MISSES, 271 XTPERF_CNT_D_ACCESS_U2, XTPERF_MASK_D_ACCESS_CACHE_MISSES, 272 XTPERF_CNT_D_ACCESS_U3, XTPERF_MASK_D_ACCESS_CACHE_MISSES, 273 XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_0L, 274 XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_1L, 275 XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_1S_0L, 276 XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_1S_1L, 277 XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_0S_2L, 278 XTPERF_CNT_MULTIPLE_LS, XTPERF_MASK_MULTIPLE_LS_2S_0L, 279 XTPERF_CNT_OUTBOUND_PIF, XTPERF_MASK_OUTBOUND_PIF_CASTOUT, 280 XTPERF_CNT_OUTBOUND_PIF, XTPERF_MASK_OUTBOUND_PIF_PREFETCH, 281 XTPERF_CNT_INBOUND_PIF, XTPERF_MASK_INBOUND_PIF_I_DMA, 282 XTPERF_CNT_INBOUND_PIF, XTPERF_MASK_INBOUND_PIF_D_DMA, 283 XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_HIT, 284 XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_HIT, 285 XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_MISS, 286 XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_MISS, 287 XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_L1_FILL, 288 #if XCHAL_HW_VERSION >= 270004 289 XTPERF_CNT_IDMA, XTPERF_MASK_IDMA_ALL, 290 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_16, 291 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_24, 292 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_32, 293 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_40, 294 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_48, 295 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_56, 296 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_64, 297 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_72, 298 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_80, 299 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_88, 300 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_96, 301 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_104, 302 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_112, 303 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_120, 304 XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_128 305 #endif 306 };