spi_flash_rom_patch.c
1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #include "sdkconfig.h" 15 #include "esp32/rom/spi_flash.h" 16 #include "soc/spi_periph.h" 17 18 19 #define SPI_IDX 1 20 #define OTH_IDX 0 21 22 23 extern esp_rom_spiflash_chip_t g_rom_spiflash_chip; 24 25 static inline bool is_issi_chip(const esp_rom_spiflash_chip_t* chip) 26 { 27 return (((chip->device_id >> 16)&0xff) == 0x9D); 28 } 29 30 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi) 31 { 32 uint32_t status; 33 #if CONFIG_IDF_TARGET_ESP32 34 //wait for spi control ready 35 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) { 36 } 37 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) { 38 } 39 #elif CONFIG_IDF_TARGET_ESP32S2 40 while ((REG_READ(SPI_MEM_FSM_REG(1)) & SPI_MEM_ST)) { 41 } 42 while ((REG_READ(SPI_MEM_FSM_REG(0)) & SPI_MEM_ST)) { 43 } 44 #endif 45 //wait for flash status ready 46 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_status(spi, &status)) { 47 return ESP_ROM_SPIFLASH_RESULT_ERR; 48 } 49 return ESP_ROM_SPIFLASH_RESULT_OK; 50 } 51 52 53 /* Modified version of esp_rom_spiflash_unlock() that replaces version in ROM. 54 55 This works around a bug where esp_rom_spiflash_unlock sometimes reads the wrong 56 high status byte (RDSR2 result) and then copies it back to the 57 flash status, which can cause the CMP bit or Status Register 58 Protect bit to become set. 59 60 Like other ROM SPI functions, this function is not designed to be 61 called directly from an RTOS environment without taking precautions 62 about interrupts, CPU coordination, flash mapping. However some of 63 the functions in esp_spi_flash.c call it. 64 */ 65 esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void) 66 { 67 uint32_t status; 68 uint32_t new_status; 69 70 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip); 71 72 if (is_issi_chip(&g_rom_spiflash_chip)) { 73 // ISSI chips have different QE position 74 75 if (esp_rom_spiflash_read_status(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) { 76 return ESP_ROM_SPIFLASH_RESULT_ERR; 77 } 78 79 /* Clear all bits in the mask. 80 (This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.) 81 */ 82 new_status = status & (~ESP_ROM_SPIFLASH_BP_MASK_ISSI); 83 // Skip if nothing needs to be cleared. Otherwise will waste time waiting for the flash to clear nothing. 84 if (new_status == status) return ESP_ROM_SPIFLASH_RESULT_OK; 85 86 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B); 87 } else { 88 if (esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) { 89 return ESP_ROM_SPIFLASH_RESULT_ERR; 90 } 91 92 /* Clear all bits except QE, if it is set. 93 (This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.) 94 */ 95 new_status = status & ESP_ROM_SPIFLASH_QE; 96 SET_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B); 97 } 98 99 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip); 100 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WREN); 101 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) { 102 } 103 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip); 104 esp_rom_spiflash_result_t ret = esp_rom_spiflash_write_status(&g_rom_spiflash_chip, new_status); 105 // WEL bit should be cleared after operations regardless of writing succeed or not. 106 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip); 107 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WRDI); 108 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) { 109 } 110 return ret; 111 } 112 113 #if CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 114 115 extern uint8_t g_rom_spiflash_dummy_len_plus[]; 116 117 118 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi); 119 120 //only support spi1 121 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip_internal(esp_rom_spiflash_chip_t *spi) 122 { 123 esp_rom_spiflash_wait_idle(spi); 124 125 // Chip erase. 126 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE); 127 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); 128 129 // check erase is finished. 130 esp_rom_spiflash_wait_idle(spi); 131 132 return ESP_ROM_SPIFLASH_RESULT_OK; 133 } 134 135 //only support spi1 136 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr) 137 { 138 //check if addr is 4k alignment 139 if (0 != (addr & 0xfff)) { 140 return ESP_ROM_SPIFLASH_RESULT_ERR; 141 } 142 143 esp_rom_spiflash_wait_idle(spi); 144 145 // sector erase 4Kbytes erase is sector erase. 146 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff); 147 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE); 148 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); 149 150 esp_rom_spiflash_wait_idle(spi); 151 152 return ESP_ROM_SPIFLASH_RESULT_OK; 153 } 154 155 //only support spi1 156 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_block_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr) 157 { 158 esp_rom_spiflash_wait_idle(spi); 159 160 // sector erase 4Kbytes erase is sector erase. 161 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff); 162 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE); 163 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); 164 165 esp_rom_spiflash_wait_idle(spi); 166 167 return ESP_ROM_SPIFLASH_RESULT_OK; 168 } 169 170 //only support spi1 171 static esp_rom_spiflash_result_t esp_rom_spiflash_program_page_internal(esp_rom_spiflash_chip_t *spi, uint32_t spi_addr, 172 uint32_t *addr_source, int32_t byte_length) 173 { 174 uint32_t temp_addr; 175 int32_t temp_bl; 176 uint8_t i; 177 uint8_t remain_word_num; 178 179 //check 4byte alignment 180 if (0 != (byte_length & 0x3)) { 181 return ESP_ROM_SPIFLASH_RESULT_ERR; 182 } 183 184 //check if write in one page 185 if ((spi->page_size) < ((spi_addr % (spi->page_size)) + byte_length)) { 186 return ESP_ROM_SPIFLASH_RESULT_ERR; 187 } 188 189 esp_rom_spiflash_wait_idle(spi); 190 191 temp_addr = spi_addr; 192 temp_bl = byte_length; 193 194 while (temp_bl > 0 ) { 195 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) { 196 return ESP_ROM_SPIFLASH_RESULT_ERR; 197 } 198 if ( temp_bl >= ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM ) { 199 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | ( ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM << ESP_ROM_SPIFLASH_BYTES_LEN )); // 32 byte a block 200 201 for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM >> 2); i++) { 202 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++); 203 } 204 temp_bl = temp_bl - 32; 205 temp_addr = temp_addr + 32; 206 } else { 207 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | (temp_bl << ESP_ROM_SPIFLASH_BYTES_LEN )); 208 209 remain_word_num = (0 == (temp_bl & 0x3)) ? (temp_bl >> 2) : (temp_bl >> 2) + 1; 210 for (i = 0; i < remain_word_num; i++) { 211 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++); 212 temp_bl = temp_bl - 4; 213 } 214 temp_bl = 0; 215 } 216 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP); 217 while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 ); 218 219 esp_rom_spiflash_wait_idle(spi); 220 } 221 222 return ESP_ROM_SPIFLASH_RESULT_OK; 223 } 224 225 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status) 226 { 227 uint32_t status_value = ESP_ROM_SPIFLASH_BUSY_FLAG; 228 229 if (g_rom_spiflash_dummy_len_plus[1] == 0) { 230 while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) { 231 WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter 232 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_RDSR); 233 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); 234 235 status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask); 236 } 237 } else { 238 while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) { 239 esp_rom_spiflash_read_user_cmd(&status_value, 0x05); 240 } 241 } 242 *status = status_value; 243 244 return ESP_ROM_SPIFLASH_RESULT_OK; 245 } 246 247 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status) 248 { 249 esp_rom_spiflash_result_t ret; 250 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip); 251 ret = esp_rom_spiflash_read_user_cmd(status, 0x35); 252 *status = *status << 8; 253 return ret; 254 } 255 256 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value) 257 { 258 esp_rom_spiflash_wait_idle(spi); 259 260 // update status value by status_value 261 WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, status_value); // write status regisrter 262 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WRSR); 263 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); 264 esp_rom_spiflash_wait_idle(spi); 265 266 return ESP_ROM_SPIFLASH_RESULT_OK; 267 } 268 269 //only support spi1 270 static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chip_t *spi, uint32_t flash_addr, 271 uint32_t *addr_dest, int32_t byte_length) 272 { 273 uint32_t temp_addr; 274 int32_t temp_length; 275 uint8_t i; 276 uint8_t remain_word_num; 277 278 //address range check 279 if ((flash_addr + byte_length) > (spi->chip_size)) { 280 return ESP_ROM_SPIFLASH_RESULT_ERR; 281 } 282 283 temp_addr = flash_addr; 284 temp_length = byte_length; 285 286 esp_rom_spiflash_wait_idle(spi); 287 288 while (temp_length > 0) { 289 if (temp_length >= ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM) { 290 //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << ESP_ROM_SPIFLASH_BYTES_LEN)); 291 REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S); 292 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8); 293 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR); 294 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0); 295 296 for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM >> 2); i++) { 297 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4); 298 } 299 temp_length = temp_length - ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM; 300 temp_addr = temp_addr + ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM; 301 } else { 302 //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(temp_length << ESP_ROM_SPIFLASH_BYTES_LEN )); 303 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8); 304 REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S); 305 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR); 306 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0); 307 308 remain_word_num = (0 == (temp_length & 0x3)) ? (temp_length >> 2) : (temp_length >> 2) + 1; 309 for (i = 0; i < remain_word_num; i++) { 310 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4); 311 } 312 temp_length = 0; 313 } 314 } 315 316 return ESP_ROM_SPIFLASH_RESULT_OK; 317 } 318 319 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi) 320 { 321 uint32_t flash_status = 0; 322 323 esp_rom_spiflash_wait_idle(spi); 324 325 //enable write 326 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WREN); // enable write operation 327 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); 328 329 // make sure the flash is ready for writing 330 while (ESP_ROM_SPIFLASH_WRENABLE_FLAG != (flash_status & ESP_ROM_SPIFLASH_WRENABLE_FLAG)) { 331 esp_rom_spiflash_read_status(spi, &flash_status); 332 } 333 334 return ESP_ROM_SPIFLASH_RESULT_OK; 335 } 336 337 static void spi_cache_mode_switch(uint32_t modebit) 338 { 339 if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) { 340 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); 341 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); 342 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_QIO_ADDR_BITSLEN); 343 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); 344 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xEB); 345 } else if (modebit & SPI_FASTRD_MODE) { 346 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); 347 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); 348 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_FAST_ADDR_BITSLEN); 349 if ((modebit & SPI_FREAD_QUAD)) { 350 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B); 351 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); 352 } else if ((modebit & SPI_FREAD_DIO)) { 353 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_DIO_ADDR_BITSLEN); 354 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); 355 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB); 356 } else if ((modebit & SPI_FREAD_DUAL)) { 357 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); 358 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x3B); 359 } else { 360 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]); 361 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x0B); 362 } 363 } else { 364 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); 365 if (g_rom_spiflash_dummy_len_plus[0] == 0) { 366 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_DUMMY); 367 } else { 368 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_DUMMY); 369 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[0] - 1); 370 } 371 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_ADDR); 372 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_SIO_ADDR_BITSLEN); 373 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x03); 374 } 375 } 376 377 esp_rom_spiflash_result_t esp_rom_spiflash_lock(void) 378 { 379 uint32_t status; 380 381 //read QE bit, not write if not QE 382 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status)) { 383 return ESP_ROM_SPIFLASH_RESULT_ERR; 384 } 385 //enable 2 byte status writing 386 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN); 387 388 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) { 389 return ESP_ROM_SPIFLASH_RESULT_ERR; 390 } 391 392 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(&g_rom_spiflash_chip, status | ESP_ROM_SPIFLASH_WR_PROTECT)) { 393 return ESP_ROM_SPIFLASH_RESULT_ERR; 394 } 395 396 return ESP_ROM_SPIFLASH_RESULT_OK; 397 } 398 399 400 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode) 401 { 402 uint32_t modebit; 403 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) { 404 } 405 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) { 406 } 407 //clear old mode bit 408 CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE); 409 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(0), SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE); 410 //configure read mode 411 switch (mode) { 412 case ESP_ROM_SPIFLASH_QIO_MODE : modebit = SPI_FREAD_QIO | SPI_FASTRD_MODE; break; 413 case ESP_ROM_SPIFLASH_QOUT_MODE : modebit = SPI_FREAD_QUAD | SPI_FASTRD_MODE; break; 414 case ESP_ROM_SPIFLASH_DIO_MODE : modebit = SPI_FREAD_DIO | SPI_FASTRD_MODE; break; 415 case ESP_ROM_SPIFLASH_DOUT_MODE : modebit = SPI_FREAD_DUAL | SPI_FASTRD_MODE; break; 416 case ESP_ROM_SPIFLASH_FASTRD_MODE: modebit = SPI_FASTRD_MODE; break; 417 case ESP_ROM_SPIFLASH_SLOWRD_MODE: modebit = 0; break; 418 default : modebit = 0; 419 } 420 421 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, modebit); 422 SET_PERI_REG_MASK(SPI_CTRL_REG(0), modebit); 423 spi_cache_mode_switch(modebit); 424 425 return ESP_ROM_SPIFLASH_RESULT_OK; 426 } 427 428 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void) 429 { 430 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) { 431 return ESP_ROM_SPIFLASH_RESULT_ERR; 432 } 433 434 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_chip_internal(&g_rom_spiflash_chip)) { 435 return ESP_ROM_SPIFLASH_RESULT_ERR; 436 } 437 438 return ESP_ROM_SPIFLASH_RESULT_OK; 439 } 440 441 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num) 442 { 443 // flash write is always 1 line currently 444 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); 445 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN); 446 //check program size 447 if (block_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.block_size))) { 448 return ESP_ROM_SPIFLASH_RESULT_ERR; 449 } 450 451 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) { 452 return ESP_ROM_SPIFLASH_RESULT_ERR; 453 } 454 455 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block_internal(&g_rom_spiflash_chip, block_num * (g_rom_spiflash_chip.block_size))) { 456 return ESP_ROM_SPIFLASH_RESULT_ERR; 457 } 458 return ESP_ROM_SPIFLASH_RESULT_OK; 459 } 460 461 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num) 462 { 463 // flash write is always 1 line currently 464 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); 465 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN); 466 //check program size 467 if (sector_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.sector_size))) { 468 return ESP_ROM_SPIFLASH_RESULT_ERR; 469 } 470 471 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) { 472 return ESP_ROM_SPIFLASH_RESULT_ERR; 473 } 474 475 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector_internal(&g_rom_spiflash_chip, sector_num * (g_rom_spiflash_chip.sector_size))) { 476 return ESP_ROM_SPIFLASH_RESULT_ERR; 477 } 478 479 return ESP_ROM_SPIFLASH_RESULT_OK; 480 } 481 482 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t target, const uint32_t *src_addr, int32_t len) 483 { 484 uint32_t page_size; 485 uint32_t pgm_len, pgm_num; 486 uint8_t i; 487 488 // flash write is always 1 line currently 489 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); 490 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN); 491 //check program size 492 if ( (target + len) > (g_rom_spiflash_chip.chip_size)) { 493 return ESP_ROM_SPIFLASH_RESULT_ERR; 494 } 495 496 page_size = g_rom_spiflash_chip.page_size; 497 pgm_len = page_size - (target % page_size); 498 if (len < pgm_len) { 499 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip, 500 target, (uint32_t *)src_addr, len)) { 501 return ESP_ROM_SPIFLASH_RESULT_ERR; 502 } 503 } else { 504 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip, 505 target, (uint32_t *)src_addr, pgm_len)) { 506 return ESP_ROM_SPIFLASH_RESULT_ERR; 507 } 508 509 //whole page program 510 pgm_num = (len - pgm_len) / page_size; 511 for (i = 0; i < pgm_num; i++) { 512 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip, 513 target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), page_size)) { 514 return ESP_ROM_SPIFLASH_RESULT_ERR; 515 } 516 pgm_len += page_size; 517 } 518 519 //remain parts to program 520 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip, 521 target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), len - pgm_len)) { 522 return ESP_ROM_SPIFLASH_RESULT_ERR; 523 } 524 } 525 return ESP_ROM_SPIFLASH_RESULT_OK; 526 } 527 528 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len) 529 { 530 esp_rom_spiflash_result_t ret = ESP_ROM_SPIFLASH_RESULT_OK; 531 uint32_t i; 532 533 if ((flash_addr & 0x1f) || (len & 0x1f)) { //check 32 byte alignment 534 return ESP_ROM_SPIFLASH_RESULT_ERR; 535 } 536 537 esp_rom_spiflash_write_encrypted_enable(); 538 539 for (i = 0; i < (len >> 5); i++) { 540 if ((ret = esp_rom_spiflash_prepare_encrypted_data(flash_addr + (i << 5), data + (i << 3))) != ESP_ROM_SPIFLASH_RESULT_OK) { 541 break; 542 } 543 544 if ((ret = esp_rom_spiflash_write(flash_addr + (i << 5), data, 32)) != ESP_ROM_SPIFLASH_RESULT_OK) { 545 break; 546 } 547 } 548 549 esp_rom_spiflash_write_encrypted_disable(); 550 551 return ret; 552 } 553 554 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_addr, int32_t len) 555 { 556 // QIO or SIO, non-QIO regard as SIO 557 uint32_t modebit; 558 modebit = READ_PERI_REG(PERIPHS_SPI_FLASH_CTRL); 559 if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) { 560 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI); 561 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); 562 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_QIO_ADDR_BITSLEN); 563 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]); 564 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xEB); 565 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xEB); 566 } else if (modebit & SPI_FASTRD_MODE) { 567 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI); 568 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR); 569 if (modebit & SPI_FREAD_DIO) { 570 if (g_rom_spiflash_dummy_len_plus[1] == 0) { 571 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); 572 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN); 573 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xBB); 574 } else { 575 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); 576 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN); 577 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1); 578 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xBB); 579 } 580 } else { 581 if ((modebit & SPI_FREAD_QUAD)) { 582 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x6B); 583 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x6B); 584 } else if ((modebit & SPI_FREAD_DUAL)) { 585 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x3B); 586 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x3B); 587 } else { 588 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x0B); 589 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x0B); 590 } 591 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); 592 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_FAST_ADDR_BITSLEN); 593 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]); 594 } 595 } else { 596 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI); 597 if (g_rom_spiflash_dummy_len_plus[1] == 0) { 598 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); 599 } else { 600 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); 601 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1); 602 } 603 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR); 604 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_SIO_ADDR_BITSLEN); 605 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x03); 606 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x03); 607 } 608 609 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_data(&g_rom_spiflash_chip, target, dest_addr, len)) { 610 return ESP_ROM_SPIFLASH_RESULT_ERR; 611 } 612 return ESP_ROM_SPIFLASH_RESULT_OK; 613 } 614 615 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len) 616 { 617 int32_t total_sector_num; 618 int32_t head_sector_num; 619 uint32_t sector_no; 620 uint32_t sector_num_per_block; 621 622 //set read mode to Fastmode ,not QDIO mode for erase 623 // 624 // TODO: this is probably a bug as it doesn't re-enable QIO mode, not serious as this 625 // function is not used in IDF. 626 esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE); 627 628 //check if area is oversize of flash 629 if ((start_addr + area_len) > g_rom_spiflash_chip.chip_size) { 630 return ESP_ROM_SPIFLASH_RESULT_ERR; 631 } 632 633 //start_addr is aligned as sector boundary 634 if (0 != (start_addr % g_rom_spiflash_chip.sector_size)) { 635 return ESP_ROM_SPIFLASH_RESULT_ERR; 636 } 637 638 //Unlock flash to enable erase 639 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_unlock(/*&g_rom_spiflash_chip*/)) { 640 return ESP_ROM_SPIFLASH_RESULT_ERR; 641 } 642 643 sector_no = start_addr / g_rom_spiflash_chip.sector_size; 644 sector_num_per_block = g_rom_spiflash_chip.block_size / g_rom_spiflash_chip.sector_size; 645 total_sector_num = (0 == (area_len % g_rom_spiflash_chip.sector_size)) ? area_len / g_rom_spiflash_chip.sector_size : 646 1 + (area_len / g_rom_spiflash_chip.sector_size); 647 648 //check if erase area reach over block boundary 649 head_sector_num = sector_num_per_block - (sector_no % sector_num_per_block); 650 651 head_sector_num = (head_sector_num >= total_sector_num) ? total_sector_num : head_sector_num; 652 653 //JJJ, BUG of 6.0 erase 654 //middle part of area is aligned by blocks 655 total_sector_num -= head_sector_num; 656 657 //head part of area is erased 658 while (0 != head_sector_num) { 659 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) { 660 return ESP_ROM_SPIFLASH_RESULT_ERR; 661 } 662 sector_no++; 663 head_sector_num--; 664 } 665 while (total_sector_num > sector_num_per_block) { 666 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block(sector_no / sector_num_per_block)) { 667 return ESP_ROM_SPIFLASH_RESULT_ERR; 668 } 669 sector_no += sector_num_per_block; 670 total_sector_num -= sector_num_per_block; 671 } 672 673 //tail part of area burn 674 while (0 < total_sector_num) { 675 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) { 676 return ESP_ROM_SPIFLASH_RESULT_ERR; 677 } 678 sector_no++; 679 total_sector_num--; 680 } 681 682 return ESP_ROM_SPIFLASH_RESULT_OK; 683 } 684 685 #endif