1  // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
  2  //
  3  // Licensed under the Apache License, Version 2.0 (the "License");
  4  // you may not use this file except in compliance with the License.
  5  // You may obtain a copy of the License at
  6  //
  7  //     http://www.apache.org/licenses/LICENSE-2.0
  8  //
  9  // Unless required by applicable law or agreed to in writing, software
 10  // distributed under the License is distributed on an "AS IS" BASIS,
 11  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 12  // See the License for the specific language governing permissions and
 13  // limitations under the License.
 14  
 15  #include <stdarg.h>
 16  #include <sys/param.h>  //For max/min
 17  #include "esp_attr.h"
 18  #include "esp_spi_flash.h"   //for ``g_flash_guard_default_ops``
 19  #include "esp_flash.h"
 20  #include "esp_flash_partitions.h"
 21  #include "freertos/FreeRTOS.h"
 22  #include "freertos/task.h"
 23  #include "hal/spi_types.h"
 24  #include "sdkconfig.h"
 25  #include "esp_log.h"
 26  
 27  #include "esp_rom_sys.h"
 28  
 29  #include "driver/spi_common_internal.h"
 30  
 31  static const char TAG[] = "spi_flash";
 32  
 33  /*
 34   * OS functions providing delay service and arbitration among chips, and with the cache.
 35   *
 36   * The cache needs to be disabled when chips on the SPI1 bus is under operation, hence these functions need to be put
 37   * into the IRAM,and their data should be put into the DRAM.
 38   */
 39  
 40  typedef struct {
 41      spi_bus_lock_dev_handle_t dev_lock;
 42  } app_func_arg_t;
 43  
 44  typedef struct {
 45      app_func_arg_t common_arg; //shared args, must be the first item
 46      bool no_protect;    //to decide whether to check protected region (for the main chip) or not.
 47  } spi1_app_func_arg_t;
 48  
 49  IRAM_ATTR static void cache_enable(void* arg)
 50  {
 51      g_flash_guard_default_ops.end();
 52  }
 53  
 54  IRAM_ATTR static void cache_disable(void* arg)
 55  {
 56      g_flash_guard_default_ops.start();
 57  }
 58  
 59  static IRAM_ATTR esp_err_t spi_start(void *arg)
 60  {
 61      spi_bus_lock_dev_handle_t dev_lock = ((app_func_arg_t *)arg)->dev_lock;
 62  
 63      // wait for other devices (or cache) to finish their operation
 64      esp_err_t ret = spi_bus_lock_acquire_start(dev_lock, portMAX_DELAY);
 65      if (ret != ESP_OK) {
 66          return ret;
 67      }
 68      spi_bus_lock_touch(dev_lock);
 69      return ESP_OK;
 70  }
 71  
 72  static IRAM_ATTR esp_err_t spi_end(void *arg)
 73  {
 74      return spi_bus_lock_acquire_end(((app_func_arg_t *)arg)->dev_lock);
 75  }
 76  
 77  static IRAM_ATTR esp_err_t spi1_start(void *arg)
 78  {
 79  #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
 80      //use the lock to disable the cache and interrupts before using the SPI bus
 81      return spi_start(arg);
 82  #else
 83      //directly disable the cache and interrupts when lock is not used
 84      cache_disable(NULL);
 85  #endif
 86      return ESP_OK;
 87  }
 88  
 89  static IRAM_ATTR esp_err_t spi1_end(void *arg)
 90  {
 91  #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
 92      return spi_end(arg);
 93  #else
 94      cache_enable(NULL);
 95      return ESP_OK;
 96  #endif
 97  }
 98  
 99  static IRAM_ATTR esp_err_t delay_us(void *arg, uint32_t us)
100  {
101      esp_rom_delay_us(us);
102      return ESP_OK;
103  }
104  static IRAM_ATTR esp_err_t spi_flash_os_yield(void *arg)
105  {
106  #ifdef CONFIG_SPI_FLASH_YIELD_DURING_ERASE
107      vTaskDelay(CONFIG_SPI_FLASH_ERASE_YIELD_TICKS);
108  #endif
109      return ESP_OK;
110  }
111  
112  static IRAM_ATTR void* get_buffer_malloc(void* arg, size_t reqest_size, size_t* out_size)
113  {
114      /* Allocate temporary internal buffer to use for the actual read. If the preferred size
115          doesn't fit in free internal memory, allocate the largest available free block.
116  
117          (May need to shrink read_chunk_size and retry due to race conditions with other tasks
118          also allocating from the heap.)
119      */
120      void* ret = NULL;
121      unsigned retries = 5;
122      size_t read_chunk_size = reqest_size;
123      while(ret == NULL && retries--) {
124          read_chunk_size = MIN(read_chunk_size, heap_caps_get_largest_free_block(MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT));
125          read_chunk_size = (read_chunk_size + 3) & ~3;
126          ret = heap_caps_malloc(read_chunk_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
127      }
128      ESP_LOGV(TAG, "allocate temp buffer: %p (%d)", ret, read_chunk_size);
129      *out_size = (ret != NULL? read_chunk_size: 0);
130      return ret;
131  }
132  
133  static IRAM_ATTR void release_buffer_malloc(void* arg, void *temp_buf)
134  {
135      free(temp_buf);
136  }
137  
138  static IRAM_ATTR esp_err_t main_flash_region_protected(void* arg, size_t start_addr, size_t size)
139  {
140      if (((spi1_app_func_arg_t*)arg)->no_protect || esp_partition_main_flash_region_safe(start_addr, size)) {
141          //ESP_OK = 0, also means protected==0
142          return ESP_OK;
143      } else {
144          return ESP_ERR_NOT_SUPPORTED;
145      }
146  }
147  
148  static DRAM_ATTR spi1_app_func_arg_t main_flash_arg = {};
149  
150  //for SPI1, we have to disable the cache and interrupts before using the SPI bus
151  static const DRAM_ATTR esp_flash_os_functions_t esp_flash_spi1_default_os_functions = {
152      .start = spi1_start,
153      .end = spi1_end,
154      .region_protected = main_flash_region_protected,
155      .delay_us = delay_us,
156      .get_temp_buffer = get_buffer_malloc,
157      .release_temp_buffer = release_buffer_malloc,
158      .yield = spi_flash_os_yield,
159  };
160  
161  static const esp_flash_os_functions_t esp_flash_spi23_default_os_functions = {
162      .start = spi_start,
163      .end = spi_end,
164      .delay_us = delay_us,
165      .get_temp_buffer = get_buffer_malloc,
166      .release_temp_buffer = release_buffer_malloc,
167      .yield = spi_flash_os_yield
168  };
169  
170  static spi_bus_lock_dev_handle_t register_dev(int host_id)
171  {
172      spi_bus_lock_handle_t lock = spi_bus_lock_get_by_id(host_id);
173      spi_bus_lock_dev_handle_t dev_handle;
174      spi_bus_lock_dev_config_t config = {.flags = SPI_BUS_LOCK_DEV_FLAG_CS_REQUIRED};
175      esp_err_t err = spi_bus_lock_register_dev(lock, &config, &dev_handle);
176      if (err != ESP_OK) {
177          return NULL;
178      }
179      return dev_handle;
180  }
181  
182  esp_err_t esp_flash_init_os_functions(esp_flash_t *chip, int host_id, int* out_dev_id)
183  {
184      spi_bus_lock_dev_handle_t dev_handle = NULL;
185  
186      // Skip initializing the bus lock when the bus is SPI1 and the bus is not shared with SPI Master
187      // driver, leaving dev_handle = NULL
188      bool skip_register_dev = (host_id == SPI_HOST);
189  #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
190      skip_register_dev = false;
191  #endif
192      if (!skip_register_dev) {
193          dev_handle = register_dev(host_id);
194      }
195  
196      if (host_id == SPI1_HOST) {
197          //SPI1
198          chip->os_func = &esp_flash_spi1_default_os_functions;
199          chip->os_func_data = heap_caps_malloc(sizeof(spi1_app_func_arg_t),
200                                           MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
201          if (chip->os_func_data == NULL) {
202              return ESP_ERR_NO_MEM;
203          }
204          *(spi1_app_func_arg_t*) chip->os_func_data = (spi1_app_func_arg_t) {
205              .common_arg = {
206                  .dev_lock = dev_handle,
207              },
208              .no_protect = true,
209          };
210      } else if (host_id == SPI2_HOST || host_id == SPI3_HOST) {
211          //SPI2, SPI3
212          chip->os_func = &esp_flash_spi23_default_os_functions;
213          chip->os_func_data = heap_caps_malloc(sizeof(app_func_arg_t),
214                                           MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
215          if (chip->os_func_data == NULL) {
216              return ESP_ERR_NO_MEM;
217          }
218          *(app_func_arg_t*) chip->os_func_data = (app_func_arg_t) {
219                  .dev_lock = dev_handle,
220          };
221      } else {
222          return ESP_ERR_INVALID_ARG;
223      }
224  
225      // Bus lock not initialized, the device ID should be directly given by application.
226      if (dev_handle) {
227          *out_dev_id = spi_bus_lock_get_dev_id(dev_handle);
228      }
229  
230      return ESP_OK;
231  }
232  
233  esp_err_t esp_flash_deinit_os_functions(esp_flash_t* chip)
234  {
235      if (chip->os_func_data) {
236          spi_bus_lock_dev_handle_t dev_lock = ((app_func_arg_t*)chip->os_func_data)->dev_lock;
237          // SPI bus lock is possible not used on SPI1 bus
238          if (dev_lock) {
239              spi_bus_lock_unregister_dev(dev_lock);
240          }
241          free(chip->os_func_data);
242      }
243      chip->os_func = NULL;
244      chip->os_func_data = NULL;
245      return ESP_OK;
246  }
247  
248  esp_err_t esp_flash_init_main_bus_lock(void)
249  {
250      spi_bus_lock_init_main_bus();
251      spi_bus_lock_set_bg_control(g_main_spi_bus_lock, cache_enable, cache_disable, NULL);
252  
253      esp_err_t err = spi_bus_lock_init_main_dev();
254      if (err != ESP_OK) {
255          return err;
256      }
257      return ESP_OK;
258  }
259  
260  esp_err_t esp_flash_app_enable_os_functions(esp_flash_t* chip)
261  {
262      main_flash_arg = (spi1_app_func_arg_t) {
263          .common_arg = {
264              .dev_lock = g_spi_lock_main_flash_dev,   //for SPI1,
265          },
266          .no_protect = false,
267      };
268      chip->os_func = &esp_flash_spi1_default_os_functions;
269      chip->os_func_data = &main_flash_arg;
270      return ESP_OK;
271  }