ulp.c
1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #include <stdio.h> 16 #include <string.h> 17 #include <stdlib.h> 18 #include "sdkconfig.h" 19 #include "esp_attr.h" 20 #include "esp_err.h" 21 #include "esp_log.h" 22 #if CONFIG_IDF_TARGET_ESP32 23 #include "esp32/clk.h" 24 #include "esp32/ulp.h" 25 #elif CONFIG_IDF_TARGET_ESP32S2 26 #include "esp32s2/clk.h" 27 #include "esp32s2/ulp.h" 28 #elif CONFIG_IDF_TARGET_ESP32S3 29 #include "esp32s3/clk.h" 30 #include "esp32s3/ulp.h" 31 #endif 32 33 #include "soc/soc.h" 34 #include "soc/rtc.h" 35 #include "soc/rtc_cntl_reg.h" 36 #include "soc/sens_reg.h" 37 38 #include "ulp_private.h" 39 #include "esp_rom_sys.h" 40 41 typedef struct { 42 uint32_t magic; 43 uint16_t text_offset; 44 uint16_t text_size; 45 uint16_t data_size; 46 uint16_t bss_size; 47 } ulp_binary_header_t; 48 49 #define ULP_BINARY_MAGIC_ESP32 (0x00706c75) 50 51 static const char* TAG = "ulp"; 52 53 esp_err_t ulp_run(uint32_t entry_point) 54 { 55 #if CONFIG_IDF_TARGET_ESP32 56 // disable ULP timer 57 CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); 58 // wait for at least 1 RTC_SLOW_CLK cycle 59 esp_rom_delay_us(10); 60 // set entry point 61 REG_SET_FIELD(SENS_SAR_START_FORCE_REG, SENS_PC_INIT, entry_point); 62 // disable force start 63 CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP_M); 64 // set time until wakeup is allowed to the smallest possible 65 REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN); 66 // make sure voltage is raised when RTC 8MCLK is enabled 67 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M); 68 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M); 69 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M); 70 // enable ULP timer 71 SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); 72 #elif defined CONFIG_IDF_TARGET_ESP32S2 73 // disable ULP timer 74 CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); 75 // wait for at least 1 RTC_SLOW_CLK cycle 76 esp_rom_delay_us(10); 77 // set entry point 78 REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_PC_INIT, entry_point); 79 SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL); // Select ULP_TIMER trigger target for ULP. 80 // start ULP clock gate. 81 SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG ,RTC_CNTL_ULP_CP_CLK_FO); 82 // ULP FSM sends the DONE signal. 83 CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE); 84 /* Set the number of cycles of ULP_TIMER sleep, the wait time required to start ULP */ 85 REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE, 100); 86 /* Clear interrupt COCPU status */ 87 REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR | RTC_CNTL_COCPU_TRAP_INT_CLR | RTC_CNTL_ULP_CP_INT_CLR); 88 // 1: start with timer. wait ULP_TIMER cnt timer. 89 CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); // Select ULP_TIMER timer as COCPU trigger source 90 SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); // Software to turn on the ULP_TIMER timer 91 #endif 92 return ESP_OK; 93 } 94 95 esp_err_t ulp_load_binary(uint32_t load_addr, const uint8_t* program_binary, size_t program_size) 96 { 97 size_t program_size_bytes = program_size * sizeof(uint32_t); 98 size_t load_addr_bytes = load_addr * sizeof(uint32_t); 99 100 if (program_size_bytes < sizeof(ulp_binary_header_t)) { 101 return ESP_ERR_INVALID_SIZE; 102 } 103 if (load_addr_bytes > ULP_RESERVE_MEM) { 104 return ESP_ERR_INVALID_ARG; 105 } 106 if (load_addr_bytes + program_size_bytes > ULP_RESERVE_MEM) { 107 return ESP_ERR_INVALID_SIZE; 108 } 109 110 // Make a copy of a header in case program_binary isn't aligned 111 ulp_binary_header_t header; 112 memcpy(&header, program_binary, sizeof(header)); 113 114 if (header.magic != ULP_BINARY_MAGIC_ESP32) { 115 return ESP_ERR_NOT_SUPPORTED; 116 } 117 118 size_t total_size = (size_t) header.text_offset + (size_t) header.text_size + 119 (size_t) header.data_size; 120 121 ESP_LOGD(TAG, "program_size_bytes: %d total_size: %d offset: %d .text: %d, .data: %d, .bss: %d", 122 program_size_bytes, total_size, header.text_offset, 123 header.text_size, header.data_size, header.bss_size); 124 125 if (total_size != program_size_bytes) { 126 return ESP_ERR_INVALID_SIZE; 127 } 128 129 size_t text_data_size = header.text_size + header.data_size; 130 uint8_t* base = (uint8_t*) RTC_SLOW_MEM; 131 132 memcpy(base + load_addr_bytes, program_binary + header.text_offset, text_data_size); 133 memset(base + load_addr_bytes + text_data_size, 0, header.bss_size); 134 135 return ESP_OK; 136 } 137 138 esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us) 139 { 140 #if CONFIG_IDF_TARGET_ESP32 141 if (period_index > 4) { 142 return ESP_ERR_INVALID_ARG; 143 } 144 uint64_t period_us_64 = period_us; 145 uint64_t period_cycles = (period_us_64 << RTC_CLK_CAL_FRACT) / esp_clk_slowclk_cal_get(); 146 uint64_t min_sleep_period_cycles = ULP_FSM_PREPARE_SLEEP_CYCLES 147 + ULP_FSM_WAKEUP_SLEEP_CYCLES 148 + REG_GET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT); 149 if (period_cycles < min_sleep_period_cycles) { 150 period_cycles = 0; 151 ESP_LOGW(TAG, "Sleep period clipped to minimum of %d cycles", (uint32_t) min_sleep_period_cycles); 152 } else { 153 period_cycles -= min_sleep_period_cycles; 154 } 155 REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t), 156 SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles); 157 #elif defined CONFIG_IDF_TARGET_ESP32S2 158 if (period_index > 4) { 159 return ESP_ERR_INVALID_ARG; 160 } 161 162 uint64_t period_us_64 = period_us; 163 164 rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get(); 165 rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL; 166 rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256; 167 rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; 168 if (slow_clk_freq == (rtc_slow_freq_x32k)) { 169 cal_clk = RTC_CAL_32K_XTAL; 170 } else if (slow_clk_freq == rtc_slow_freq_8MD256) { 171 cal_clk = RTC_CAL_8MD256; 172 } 173 uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100); 174 uint64_t period_cycles = rtc_time_us_to_slowclk(period_us_64, slow_clk_period); 175 176 REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_1_REG, RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE, ((uint32_t)period_cycles)); 177 #endif 178 return ESP_OK; 179 }