csr_address.py
1 from collections.abc import Set 2 from amaranth.lib.enum import IntEnum, unique 3 4 __all__ = [ 5 "CSRAddress", 6 "MstatusFieldOffsets", 7 "MenvcfgFieldOffsets", 8 "CounterEnableFieldOffsets", 9 "sstatus_field_subset", 10 "senvcfg_field_subset", 11 ] 12 13 14 @unique 15 class CSRAddress(IntEnum, shape=12): 16 # Unprivileged Floating-Point CSRs 17 FFLAGS = 0x001 # Floating-Point Accrued Exceptions 18 FRM = 0x002 # Floating-Point Dynamic Rounding Mode 19 FCSR = 0x003 # Floating-Point Control and Status Register (`frm` +`fflags`) 20 21 # Unprivileged Zicfiss extension CSR 22 SSP = 0x011 # Shadow Stack Pointer 23 24 # Unprivileged Counter/Timers 25 CYCLE = 0xC00 # Cycle counter for RDCYCLE instruction 26 TIME = 0xC01 # Timer for RDTIME instruction 27 INSTRET = 0xC02 # Instructions-retired counter for RDINSTRET instruction 28 HPMCOUNTER3 = 0xC03 # Performance-monitoring counter 29 HPMCOUNTER4 = 0xC04 # Performance-monitoring counter 30 HPMCOUNTER5 = 0xC05 # Performance-monitoring counter 31 HPMCOUNTER6 = 0xC06 # Performance-monitoring counter 32 HPMCOUNTER7 = 0xC07 # Performance-monitoring counter 33 HPMCOUNTER8 = 0xC08 # Performance-monitoring counter 34 HPMCOUNTER9 = 0xC09 # Performance-monitoring counter 35 HPMCOUNTER10 = 0xC0A # Performance-monitoring counter 36 HPMCOUNTER11 = 0xC0B # Performance-monitoring counter 37 HPMCOUNTER12 = 0xC0C # Performance-monitoring counter 38 HPMCOUNTER13 = 0xC0D # Performance-monitoring counter 39 HPMCOUNTER14 = 0xC0E # Performance-monitoring counter 40 HPMCOUNTER15 = 0xC0F # Performance-monitoring counter 41 HPMCOUNTER16 = 0xC10 # Performance-monitoring counter 42 HPMCOUNTER17 = 0xC11 # Performance-monitoring counter 43 HPMCOUNTER18 = 0xC12 # Performance-monitoring counter 44 HPMCOUNTER19 = 0xC13 # Performance-monitoring counter 45 HPMCOUNTER20 = 0xC14 # Performance-monitoring counter 46 HPMCOUNTER21 = 0xC15 # Performance-monitoring counter 47 HPMCOUNTER22 = 0xC16 # Performance-monitoring counter 48 HPMCOUNTER23 = 0xC17 # Performance-monitoring counter 49 HPMCOUNTER24 = 0xC18 # Performance-monitoring counter 50 HPMCOUNTER25 = 0xC19 # Performance-monitoring counter 51 HPMCOUNTER26 = 0xC1A # Performance-monitoring counter 52 HPMCOUNTER27 = 0xC1B # Performance-monitoring counter 53 HPMCOUNTER28 = 0xC1C # Performance-monitoring counter 54 HPMCOUNTER29 = 0xC1D # Performance-monitoring counter 55 HPMCOUNTER30 = 0xC1E # Performance-monitoring counter 56 HPMCOUNTER31 = 0xC1F # Performance-monitoring counter 57 CYCLEH = 0xC80 # Upper 32 bits of `cycle`, RV32 only 58 TIMEH = 0xC81 # Upper 32 bits of `time`, RV32 only 59 INSTRETH = 0xC82 # Upper 32 bits of `instret`, RV32 only 60 HPMCOUNTER3H = 0xC83 # Upper 32 bits of `hpmcounter3`, RV32 only 61 HPMCOUNTER4H = 0xC84 # Upper 32 bits of `hpmcounter4`, RV32 only 62 HPMCOUNTER5H = 0xC85 # Upper 32 bits of `hpmcounter5`, RV32 only 63 HPMCOUNTER6H = 0xC86 # Upper 32 bits of `hpmcounter6`, RV32 only 64 HPMCOUNTER7H = 0xC87 # Upper 32 bits of `hpmcounter7`, RV32 only 65 HPMCOUNTER8H = 0xC88 # Upper 32 bits of `hpmcounter8`, RV32 only 66 HPMCOUNTER9H = 0xC89 # Upper 32 bits of `hpmcounter9`, RV32 only 67 HPMCOUNTER10H = 0xC8A # Upper 32 bits of `hpmcounter10`, RV32 only 68 HPMCOUNTER11H = 0xC8B # Upper 32 bits of `hpmcounter11`, RV32 only 69 HPMCOUNTER12H = 0xC8C # Upper 32 bits of `hpmcounter12`, RV32 only 70 HPMCOUNTER13H = 0xC8D # Upper 32 bits of `hpmcounter13`, RV32 only 71 HPMCOUNTER14H = 0xC8E # Upper 32 bits of `hpmcounter14`, RV32 only 72 HPMCOUNTER15H = 0xC8F # Upper 32 bits of `hpmcounter15`, RV32 only 73 HPMCOUNTER16H = 0xC90 # Upper 32 bits of `hpmcounter16`, RV32 only 74 HPMCOUNTER17H = 0xC91 # Upper 32 bits of `hpmcounter17`, RV32 only 75 HPMCOUNTER18H = 0xC92 # Upper 32 bits of `hpmcounter18`, RV32 only 76 HPMCOUNTER19H = 0xC93 # Upper 32 bits of `hpmcounter19`, RV32 only 77 HPMCOUNTER20H = 0xC94 # Upper 32 bits of `hpmcounter20`, RV32 only 78 HPMCOUNTER21H = 0xC95 # Upper 32 bits of `hpmcounter21`, RV32 only 79 HPMCOUNTER22H = 0xC96 # Upper 32 bits of `hpmcounter22`, RV32 only 80 HPMCOUNTER23H = 0xC97 # Upper 32 bits of `hpmcounter23`, RV32 only 81 HPMCOUNTER24H = 0xC98 # Upper 32 bits of `hpmcounter24`, RV32 only 82 HPMCOUNTER25H = 0xC99 # Upper 32 bits of `hpmcounter25`, RV32 only 83 HPMCOUNTER26H = 0xC9A # Upper 32 bits of `hpmcounter26`, RV32 only 84 HPMCOUNTER27H = 0xC9B # Upper 32 bits of `hpmcounter27`, RV32 only 85 HPMCOUNTER28H = 0xC9C # Upper 32 bits of `hpmcounter28`, RV32 only 86 HPMCOUNTER29H = 0xC9D # Upper 32 bits of `hpmcounter29`, RV32 only 87 HPMCOUNTER30H = 0xC9E # Upper 32 bits of `hpmcounter30`, RV32 only 88 HPMCOUNTER31H = 0xC9F # Upper 32 bits of `hpmcounter31`, RV32 only 89 90 # Supervisor Trap Setup 91 SSTATUS = 0x100 # Supervisor status register 92 SIE = 0x104 # Supervisor interrupt-enable register 93 STVEC = 0x105 # Supervisor trap handler base address 94 SCOUNTEREN = 0x106 # Supervisor counter enable 95 96 # Supervisor Configuration 97 SENVCFG = 0x10A # Supervisor environment configuration register 98 99 # Supervisor Counter Setup 100 SCOUNTINHIBIT = 0x120 # Supervisor counter-inhibit register 101 102 # Supervisor Trap Handling 103 SSCRATCH = 0x140 # Scratch register for supervisor trap handlers 104 SEPC = 0x141 # Supervisor exception program counter 105 SCAUSE = 0x142 # Supervisor trap cause 106 STVAL = 0x143 # Supervisor bad address or instruction 107 SIP = 0x144 # Supervisor interrupt pending 108 SCOUNTOVF = 0xDA0 # Supervisor count overflow 109 110 # Supervisor Protection and Translation 111 SATP = 0x180 # Supervisor address translation and protection 112 113 # Debug/Trace Registers 114 SCONTEXT = 0x5A8 # Supervisor-mode context register 115 116 # Supervisor State Enable Registers 117 SSTATEEN0 = 0x10C # Supervisor State Enable 0 Register 118 SSTATEEN1 = 0x10D # Supervisor State Enable 1 Register 119 SSTATEEN2 = 0x10E # Supervisor State Enable 2 Register 120 SSTATEEN3 = 0x10F # Supervisor State Enable 3 Register 121 122 # Hypervisor Trap Setup 123 HSTATUS = 0x600 # Hypervisor status register 124 HEDELEG = 0x602 # Hypervisor exception delegation register 125 HIDELEG = 0x603 # Hypervisor interrupt delegation register 126 HIE = 0x604 # Hypervisor interrupt-enable register 127 HCOUNTEREN = 0x606 # Hypervisor counter enable 128 HGEIE = 0x607 # Hypervisor guest external interrupt-enable register 129 HEDELEGH = 0x612 # Upper 32 bits of `hedeleg`, RV32 only 130 131 # Hypervisor Trap Handling 132 HTVAL = 0x643 # Hypervisor bad guest physical address 133 HIP = 0x644 # Hypervisor interrupt pending 134 HVIP = 0x645 # Hypervisor virtual interrupt pending 135 HTINST = 0x64A # Hypervisor trap instruction (transformed) 136 HGEIP = 0xE12 # Hypervisor guest external interrupt pending 137 138 # Hypervisor Configuration 139 HENVCFG = 0x60A # Hypervisor environment configuration register 140 HENVCFGH = 0x61A # Upper 32 bits of `henvcfg`, RV32 only 141 142 # Hypervisor Protection and Translation 143 HGATP = 0x680 # Hypervisor guest address translation and protection 144 145 # Debug/Trace Registers 146 HCONTEXT = 0x6A8 # Hypervisor-mode context register 147 148 # Hypervisor Counter/Timer Virtualization Registers 149 HTIMEDELTA = 0x605 # Delta for VS/VU-mode timer 150 HTIMEDELTAH = 0x615 # Upper 32 bits of `htimedelta`, RV32 only 151 152 # Hypervisor State Enable Registers 153 HSTATEEN0 = 0x60C # Hypervisor State Enable 0 Register 154 HSTATEEN1 = 0x60D # Hypervisor State Enable 1 Register 155 HSTATEEN2 = 0x60E # Hypervisor State Enable 2 Register 156 HSTATEEN3 = 0x60F # Hypervisor State Enable 3 Register 157 HSTATEEN0H = 0x61C # Upper 32 bits of Hypervisor State Enable 0 Register, RV32 only 158 HSTATEEN1H = 0x61D # Upper 32 bits of Hypervisor State Enable 1 Register, RV32 only 159 HSTATEEN2H = 0x61E # Upper 32 bits of Hypervisor State Enable 2 Register, RV32 only 160 HSTATEEN3H = 0x61F # Upper 32 bits of Hypervisor State Enable 3 Register, RV32 only 161 162 # Virtual Supervisor Registers 163 VSSTATUS = 0x200 # Virtual supervisor status register 164 VSIE = 0x204 # Virtual supervisor interrupt-enable register 165 VSTVEC = 0x205 # Virtual supervisor trap handler base address 166 VSSCRATCH = 0x240 # Virtual supervisor scratch register 167 VSEPC = 0x241 # Virtual supervisor exception program counter 168 VSCAUSE = 0x242 # Virtual supervisor trap cause 169 VSTVAL = 0x243 # Virtual supervisor bad address or instruction 170 VSIP = 0x244 # Virtual supervisor interrupt pending 171 VSATP = 0x280 # Virtual supervisor address translation and protection 172 173 # Machine Information Registers 174 MVENDORID = 0xF11 # Vendor ID 175 MARCHID = 0xF12 # Architecture ID 176 MIMPID = 0xF13 # Implementation ID 177 MHARTID = 0xF14 # Hardware thread ID 178 MCONFIGPTR = 0xF15 # Pointer to configuration data structure 179 180 # Machine Trap Setup 181 MSTATUS = 0x300 # Machine status register 182 MISA = 0x301 # ISA and extension 183 MEDELEG = 0x302 # Machine exception delegation register 184 MIDELEG = 0x303 # Machine interrupt delegation register 185 MIE = 0x304 # Machine interrupt-enable register 186 MTVEC = 0x305 # Machine trap-handler base address 187 MCOUNTEREN = 0x306 # Machine counter enable 188 MSTATUSH = 0x310 # Additional machine status register, RV32 only 189 MEDELEGH = 0x312 # Upper 32 bits of `medeleg`, RV32 only 190 191 # Machine Trap Handling 192 MSCRATCH = 0x340 # Scratch register for machine trap handlers 193 MEPC = 0x341 # Machine exception program counter 194 MCAUSE = 0x342 # Machine trap cause 195 MTVAL = 0x343 # Machine bad address or instruction 196 MIP = 0x344 # Machine interrupt pending 197 MTINST = 0x34A # Machine trap instruction (transformed) 198 MTVAL2 = 0x34B # Machine bad guest physical address 199 200 # Machine Configuration 201 MENVCFG = 0x30A # Machine environment configuration register 202 MENVCFGH = 0x31A # Upper 32 bits of `menvcfg`, RV32 only 203 MSECCFG = 0x747 # Machine security configuration register 204 MSECCFGH = 0x757 # Upper 32 bits of `mseccfg`, RV32 only 205 206 # Machine Memory Protection 207 PMPCFG0 = 0x3A0 # Physical memory protection configuration 208 PMPCFG1 = 0x3A1 # Physical memory protection configuration, RV32 only 209 PMPCFG2 = 0x3A2 # Physical memory protection configuration 210 PMPCFG3 = 0x3A3 # Physical memory protection configuration, RV32 only 211 PMPCFG4 = 0x3A4 # Physical memory protection configuration 212 PMPCFG5 = 0x3A5 # Physical memory protection configuration, RV32 only 213 PMPCFG6 = 0x3A6 # Physical memory protection configuration 214 PMPCFG7 = 0x3A7 # Physical memory protection configuration, RV32 only 215 PMPCFG8 = 0x3A8 # Physical memory protection configuration 216 PMPCFG9 = 0x3A9 # Physical memory protection configuration, RV32 only 217 PMPCFG10 = 0x3AA # Physical memory protection configuration 218 PMPCFG11 = 0x3AB # Physical memory protection configuration, RV32 only 219 PMPCFG12 = 0x3AC # Physical memory protection configuration 220 PMPCFG13 = 0x3AD # Physical memory protection configuration, RV32 only 221 PMPCFG14 = 0x3AE # Physical memory protection configuration 222 PMPCFG15 = 0x3AF # Physical memory protection configuration, RV32 only 223 PMPADDR0 = 0x3B0 # Physical memory protection address register 224 PMPADDR1 = 0x3B1 # Physical memory protection address register 225 PMPADDR2 = 0x3B2 # Physical memory protection address register 226 PMPADDR3 = 0x3B3 # Physical memory protection address register 227 PMPADDR4 = 0x3B4 # Physical memory protection address register 228 PMPADDR5 = 0x3B5 # Physical memory protection address register 229 PMPADDR6 = 0x3B6 # Physical memory protection address register 230 PMPADDR7 = 0x3B7 # Physical memory protection address register 231 PMPADDR8 = 0x3B8 # Physical memory protection address register 232 PMPADDR9 = 0x3B9 # Physical memory protection address register 233 PMPADDR10 = 0x3BA # Physical memory protection address register 234 PMPADDR11 = 0x3BB # Physical memory protection address register 235 PMPADDR12 = 0x3BC # Physical memory protection address register 236 PMPADDR13 = 0x3BD # Physical memory protection address register 237 PMPADDR14 = 0x3BE # Physical memory protection address register 238 PMPADDR15 = 0x3BF # Physical memory protection address register 239 PMPADDR16 = 0x3C0 # Physical memory protection address register 240 PMPADDR17 = 0x3C1 # Physical memory protection address register 241 PMPADDR18 = 0x3C2 # Physical memory protection address register 242 PMPADDR19 = 0x3C3 # Physical memory protection address register 243 PMPADDR20 = 0x3C4 # Physical memory protection address register 244 PMPADDR21 = 0x3C5 # Physical memory protection address register 245 PMPADDR22 = 0x3C6 # Physical memory protection address register 246 PMPADDR23 = 0x3C7 # Physical memory protection address register 247 PMPADDR24 = 0x3C8 # Physical memory protection address register 248 PMPADDR25 = 0x3C9 # Physical memory protection address register 249 PMPADDR26 = 0x3CA # Physical memory protection address register 250 PMPADDR27 = 0x3CB # Physical memory protection address register 251 PMPADDR28 = 0x3CC # Physical memory protection address register 252 PMPADDR29 = 0x3CD # Physical memory protection address register 253 PMPADDR30 = 0x3CE # Physical memory protection address register 254 PMPADDR31 = 0x3CF # Physical memory protection address register 255 PMPADDR32 = 0x3D0 # Physical memory protection address register 256 PMPADDR33 = 0x3D1 # Physical memory protection address register 257 PMPADDR34 = 0x3D2 # Physical memory protection address register 258 PMPADDR35 = 0x3D3 # Physical memory protection address register 259 PMPADDR36 = 0x3D4 # Physical memory protection address register 260 PMPADDR37 = 0x3D5 # Physical memory protection address register 261 PMPADDR38 = 0x3D6 # Physical memory protection address register 262 PMPADDR39 = 0x3D7 # Physical memory protection address register 263 PMPADDR40 = 0x3D8 # Physical memory protection address register 264 PMPADDR41 = 0x3D9 # Physical memory protection address register 265 PMPADDR42 = 0x3DA # Physical memory protection address register 266 PMPADDR43 = 0x3DB # Physical memory protection address register 267 PMPADDR44 = 0x3DC # Physical memory protection address register 268 PMPADDR45 = 0x3DD # Physical memory protection address register 269 PMPADDR46 = 0x3DE # Physical memory protection address register 270 PMPADDR47 = 0x3DF # Physical memory protection address register 271 PMPADDR48 = 0x3E0 # Physical memory protection address register 272 PMPADDR49 = 0x3E1 # Physical memory protection address register 273 PMPADDR50 = 0x3E2 # Physical memory protection address register 274 PMPADDR51 = 0x3E3 # Physical memory protection address register 275 PMPADDR52 = 0x3E4 # Physical memory protection address register 276 PMPADDR53 = 0x3E5 # Physical memory protection address register 277 PMPADDR54 = 0x3E6 # Physical memory protection address register 278 PMPADDR55 = 0x3E7 # Physical memory protection address register 279 PMPADDR56 = 0x3E8 # Physical memory protection address register 280 PMPADDR57 = 0x3E9 # Physical memory protection address register 281 PMPADDR58 = 0x3EA # Physical memory protection address register 282 PMPADDR59 = 0x3EB # Physical memory protection address register 283 PMPADDR60 = 0x3EC # Physical memory protection address register 284 PMPADDR61 = 0x3ED # Physical memory protection address register 285 PMPADDR62 = 0x3EE # Physical memory protection address register 286 PMPADDR63 = 0x3EF # Physical memory protection address register 287 288 # Machine State Enable Registers 289 MSTATEEN0 = 0x30C # Machine State Enable 0 Register 290 MSTATEEN1 = 0x30D # Machine State Enable 1 Register 291 MSTATEEN2 = 0x30E # Machine State Enable 2 Register 292 MSTATEEN3 = 0x30F # Machine State Enable 3 Register 293 MSTATEEN0H = 0x31C # Upper 32 bits of Machine State Enable 0 Register, RV32 only 294 MSTATEEN1H = 0x31D # Upper 32 bits of Machine State Enable 1 Register, RV32 only 295 MSTATEEN2H = 0x31E # Upper 32 bits of Machine State Enable 2 Register, RV32 only 296 MSTATEEN3H = 0x31F # Upper 32 bits of Machine State Enable 3 Register, RV32 only 297 298 # Machine Non-Maskable Interrupt Handling 299 MNSCRATCH = 0x740 # Resumable NMI scratch register 300 MNEPC = 0x741 # Resumable NMI program counter 301 MNCAUSE = 0x742 # Resumable NMI cause 302 MNSTATUS = 0x744 # Resumable NMI status 303 304 # Machine Counter/Timers 305 MCYCLE = 0xB00 # Machine cycle counter 306 MINSTRET = 0xB02 # Machine instructions-retired counter 307 MHPMCOUNTER3 = 0xB03 # Machine performance-monitoring counter 308 MHPMCOUNTER4 = 0xB04 # Machine performance-monitoring counter 309 MHPMCOUNTER5 = 0xB05 # Machine performance-monitoring counter 310 MHPMCOUNTER6 = 0xB06 # Machine performance-monitoring counter 311 MHPMCOUNTER7 = 0xB07 # Machine performance-monitoring counter 312 MHPMCOUNTER8 = 0xB08 # Machine performance-monitoring counter 313 MHPMCOUNTER9 = 0xB09 # Machine performance-monitoring counter 314 MHPMCOUNTER10 = 0xB0A # Machine performance-monitoring counter 315 MHPMCOUNTER11 = 0xB0B # Machine performance-monitoring counter 316 MHPMCOUNTER12 = 0xB0C # Machine performance-monitoring counter 317 MHPMCOUNTER13 = 0xB0D # Machine performance-monitoring counter 318 MHPMCOUNTER14 = 0xB0E # Machine performance-monitoring counter 319 MHPMCOUNTER15 = 0xB0F # Machine performance-monitoring counter 320 MHPMCOUNTER16 = 0xB10 # Machine performance-monitoring counter 321 MHPMCOUNTER17 = 0xB11 # Machine performance-monitoring counter 322 MHPMCOUNTER18 = 0xB12 # Machine performance-monitoring counter 323 MHPMCOUNTER19 = 0xB13 # Machine performance-monitoring counter 324 MHPMCOUNTER20 = 0xB14 # Machine performance-monitoring counter 325 MHPMCOUNTER21 = 0xB15 # Machine performance-monitoring counter 326 MHPMCOUNTER22 = 0xB16 # Machine performance-monitoring counter 327 MHPMCOUNTER23 = 0xB17 # Machine performance-monitoring counter 328 MHPMCOUNTER24 = 0xB18 # Machine performance-monitoring counter 329 MHPMCOUNTER25 = 0xB19 # Machine performance-monitoring counter 330 MHPMCOUNTER26 = 0xB1A # Machine performance-monitoring counter 331 MHPMCOUNTER27 = 0xB1B # Machine performance-monitoring counter 332 MHPMCOUNTER28 = 0xB1C # Machine performance-monitoring counter 333 MHPMCOUNTER29 = 0xB1D # Machine performance-monitoring counter 334 MHPMCOUNTER30 = 0xB1E # Machine performance-monitoring counter 335 MHPMCOUNTER31 = 0xB1F # Machine performance-monitoring counter 336 MCYCLEH = 0xB80 # Upper 32 bits of `mcycle`, RV32 only 337 MINSTRETH = 0xB82 # Upper 32 bits of `minstret`, RV32 only 338 MHPMCOUNTER3H = 0xB83 # Upper 32 bits of `mhpmcounter3`, RV32 only 339 MHPMCOUNTER4H = 0xB84 # Upper 32 bits of `mhpmcounter4`, RV32 only 340 MHPMCOUNTER5H = 0xB85 # Upper 32 bits of `mhpmcounter5`, RV32 only 341 MHPMCOUNTER6H = 0xB86 # Upper 32 bits of `mhpmcounter6`, RV32 only 342 MHPMCOUNTER7H = 0xB87 # Upper 32 bits of `mhpmcounter7`, RV32 only 343 MHPMCOUNTER8H = 0xB88 # Upper 32 bits of `mhpmcounter8`, RV32 only 344 MHPMCOUNTER9H = 0xB89 # Upper 32 bits of `mhpmcounter9`, RV32 only 345 MHPMCOUNTER10H = 0xB8A # Upper 32 bits of `mhpmcounter10`, RV32 only 346 MHPMCOUNTER11H = 0xB8B # Upper 32 bits of `mhpmcounter11`, RV32 only 347 MHPMCOUNTER12H = 0xB8C # Upper 32 bits of `mhpmcounter12`, RV32 only 348 MHPMCOUNTER13H = 0xB8D # Upper 32 bits of `mhpmcounter13`, RV32 only 349 MHPMCOUNTER14H = 0xB8E # Upper 32 bits of `mhpmcounter14`, RV32 only 350 MHPMCOUNTER15H = 0xB8F # Upper 32 bits of `mhpmcounter15`, RV32 only 351 MHPMCOUNTER16H = 0xB90 # Upper 32 bits of `mhpmcounter16`, RV32 only 352 MHPMCOUNTER17H = 0xB91 # Upper 32 bits of `mhpmcounter17`, RV32 only 353 MHPMCOUNTER18H = 0xB92 # Upper 32 bits of `mhpmcounter18`, RV32 only 354 MHPMCOUNTER19H = 0xB93 # Upper 32 bits of `mhpmcounter19`, RV32 only 355 MHPMCOUNTER20H = 0xB94 # Upper 32 bits of `mhpmcounter20`, RV32 only 356 MHPMCOUNTER21H = 0xB95 # Upper 32 bits of `mhpmcounter21`, RV32 only 357 MHPMCOUNTER22H = 0xB96 # Upper 32 bits of `mhpmcounter22`, RV32 only 358 MHPMCOUNTER23H = 0xB97 # Upper 32 bits of `mhpmcounter23`, RV32 only 359 MHPMCOUNTER24H = 0xB98 # Upper 32 bits of `mhpmcounter24`, RV32 only 360 MHPMCOUNTER25H = 0xB99 # Upper 32 bits of `mhpmcounter25`, RV32 only 361 MHPMCOUNTER26H = 0xB9A # Upper 32 bits of `mhpmcounter26`, RV32 only 362 MHPMCOUNTER27H = 0xB9B # Upper 32 bits of `mhpmcounter27`, RV32 only 363 MHPMCOUNTER28H = 0xB9C # Upper 32 bits of `mhpmcounter28`, RV32 only 364 MHPMCOUNTER29H = 0xB9D # Upper 32 bits of `mhpmcounter29`, RV32 only 365 MHPMCOUNTER30H = 0xB9E # Upper 32 bits of `mhpmcounter30`, RV32 only 366 MHPMCOUNTER31H = 0xB9F # Upper 32 bits of `mhpmcounter31`, RV32 only 367 368 # Machine Counter Setup 369 MCOUNTINHIBIT = 0x320 # Machine counter-inhibit register 370 MHPMEVENT3 = 0x323 # Machine performance-monitoring event selector 371 MHPMEVENT4 = 0x324 # Machine performance-monitoring event selector 372 MHPMEVENT5 = 0x325 # Machine performance-monitoring event selector 373 MHPMEVENT6 = 0x326 # Machine performance-monitoring event selector 374 MHPMEVENT7 = 0x327 # Machine performance-monitoring event selector 375 MHPMEVENT8 = 0x328 # Machine performance-monitoring event selector 376 MHPMEVENT9 = 0x329 # Machine performance-monitoring event selector 377 MHPMEVENT10 = 0x32A # Machine performance-monitoring event selector 378 MHPMEVENT11 = 0x32B # Machine performance-monitoring event selector 379 MHPMEVENT12 = 0x32C # Machine performance-monitoring event selector 380 MHPMEVENT13 = 0x32D # Machine performance-monitoring event selector 381 MHPMEVENT14 = 0x32E # Machine performance-monitoring event selector 382 MHPMEVENT15 = 0x32F # Machine performance-monitoring event selector 383 MHPMEVENT16 = 0x330 # Machine performance-monitoring event selector 384 MHPMEVENT17 = 0x331 # Machine performance-monitoring event selector 385 MHPMEVENT18 = 0x332 # Machine performance-monitoring event selector 386 MHPMEVENT19 = 0x333 # Machine performance-monitoring event selector 387 MHPMEVENT20 = 0x334 # Machine performance-monitoring event selector 388 MHPMEVENT21 = 0x335 # Machine performance-monitoring event selector 389 MHPMEVENT22 = 0x336 # Machine performance-monitoring event selector 390 MHPMEVENT23 = 0x337 # Machine performance-monitoring event selector 391 MHPMEVENT24 = 0x338 # Machine performance-monitoring event selector 392 MHPMEVENT25 = 0x339 # Machine performance-monitoring event selector 393 MHPMEVENT26 = 0x33A # Machine performance-monitoring event selector 394 MHPMEVENT27 = 0x33B # Machine performance-monitoring event selector 395 MHPMEVENT28 = 0x33C # Machine performance-monitoring event selector 396 MHPMEVENT29 = 0x33D # Machine performance-monitoring event selector 397 MHPMEVENT30 = 0x33E # Machine performance-monitoring event selector 398 MHPMEVENT31 = 0x33F # Machine performance-monitoring event selector 399 MHPMEVENT3H = 0x723 # Upper 32 bits of `mhpmevent3`, RV32 only 400 MHPMEVENT4H = 0x724 # Upper 32 bits of `mhpmevent4`, RV32 only 401 MHPMEVENT5H = 0x725 # Upper 32 bits of `mhpmevent5`, RV32 only 402 MHPMEVENT6H = 0x726 # Upper 32 bits of `mhpmevent6`, RV32 only 403 MHPMEVENT7H = 0x727 # Upper 32 bits of `mhpmevent7`, RV32 only 404 MHPMEVENT8H = 0x728 # Upper 32 bits of `mhpmevent8`, RV32 only 405 MHPMEVENT9H = 0x729 # Upper 32 bits of `mhpmevent9`, RV32 only 406 MHPMEVENT10H = 0x72A # Upper 32 bits of `mhpmevent10`, RV32 only 407 MHPMEVENT11H = 0x72B # Upper 32 bits of `mhpmevent11`, RV32 only 408 MHPMEVENT12H = 0x72C # Upper 32 bits of `mhpmevent12`, RV32 only 409 MHPMEVENT13H = 0x72D # Upper 32 bits of `mhpmevent13`, RV32 only 410 MHPMEVENT14H = 0x72E # Upper 32 bits of `mhpmevent14`, RV32 only 411 MHPMEVENT15H = 0x72F # Upper 32 bits of `mhpmevent15`, RV32 only 412 MHPMEVENT16H = 0x730 # Upper 32 bits of `mhpmevent16`, RV32 only 413 MHPMEVENT17H = 0x731 # Upper 32 bits of `mhpmevent17`, RV32 only 414 MHPMEVENT18H = 0x732 # Upper 32 bits of `mhpmevent18`, RV32 only 415 MHPMEVENT19H = 0x733 # Upper 32 bits of `mhpmevent19`, RV32 only 416 MHPMEVENT20H = 0x734 # Upper 32 bits of `mhpmevent20`, RV32 only 417 MHPMEVENT21H = 0x735 # Upper 32 bits of `mhpmevent21`, RV32 only 418 MHPMEVENT22H = 0x736 # Upper 32 bits of `mhpmevent22`, RV32 only 419 MHPMEVENT23H = 0x737 # Upper 32 bits of `mhpmevent23`, RV32 only 420 MHPMEVENT24H = 0x738 # Upper 32 bits of `mhpmevent24`, RV32 only 421 MHPMEVENT25H = 0x739 # Upper 32 bits of `mhpmevent25`, RV32 only 422 MHPMEVENT26H = 0x73A # Upper 32 bits of `mhpmevent26`, RV32 only 423 MHPMEVENT27H = 0x73B # Upper 32 bits of `mhpmevent27`, RV32 only 424 MHPMEVENT28H = 0x73C # Upper 32 bits of `mhpmevent28`, RV32 only 425 MHPMEVENT29H = 0x73D # Upper 32 bits of `mhpmevent29`, RV32 only 426 MHPMEVENT30H = 0x73E # Upper 32 bits of `mhpmevent30`, RV32 only 427 MHPMEVENT31H = 0x73F # Upper 32 bits of `mhpmevent31`, RV32 only 428 429 # Debug/Trace Registers (shared with Debug Mode) 430 TSELECT = 0x7A0 # Debug/Trace trigger register select 431 TDATA1 = 0x7A1 # First Debug/Trace trigger data register 432 TDATA2 = 0x7A2 # Second Debug/Trace trigger data register 433 TDATA3 = 0x7A3 # Third Debug/Trace trigger data register 434 MCONTEXT = 0x7A8 # Machine-mode context register 435 436 # Debug Mode Registers 437 DCSR = 0x7B0 # Debug control and status register 438 DPC = 0x7B1 # Debug program counter 439 DSCRATCH0 = 0x7B2 # Debug scratch register 0 440 DSCRATCH1 = 0x7B3 # Debug scratch register 1. 441 442 # Internal Coreblocks CSRs 443 # used only for testbench verification 444 445 # CSR for custom communication with testbenches 446 COREBLOCKS_TEST_CSR = 0x7FF 447 # CSR providing writable current privilege mode (U-mode accesible) 448 COREBLOCKS_TEST_PRIV_MODE = 0x8FF 449 450 451 # Width of pmpXcfg subfields in pmpcfgX registers 452 PMPXCFG_WIDTH = 8 453 454 455 @unique 456 class MstatusFieldOffsets(IntEnum): 457 SIE = 1 # Supervisor Interrupt Enable 458 MIE = 3 # Machine Interrupt Enable 459 SPIE = 5 # Supervisor Previous Interrupt Enable 460 UBE = 6 # User Endianness Control 461 MPIE = 7 # Machine Previous Interrupt Enable 462 SPP = 8 # Supervisor Previous Privilege 463 VS = 9 # Vector Context Status 464 MPP = 11 # Machine Previous Privilege 465 FS = 13 # Float Context Status 466 XS = 15 # Additional Extension State Context Status 467 MPRV = 17 # Modify Privilege 468 SUM = 18 # Supervisor User Memory Access 469 MXR = 19 # Make Executable Readable 470 TVM = 20 # Trap Virtual Memory 471 TW = 21 # Timeout Wait 472 TSR = 22 # Trap SRET 473 SPELP = 23 # Supervisor Previous Expected Landing Pad 474 SDT = 24 # Supervisor Double Trap 475 UXL = 32 # User XLEN 476 SXL = 34 # Supervisor XLEN 477 SBE = 36 # Supervisor Endianness Control 478 MBE = 37 # Machine Endianness Control 479 GVA = 38 # Guest Virtual Address 480 MPV = 39 # Mass Page Valid 481 MPELP = 40 # Machine Previous Expected Landing Pad 482 MDT = 41 # Machine Disable Trap 483 SD = -1 # Context Status Dirty bit. Placed on last bit of mstatus 484 485 def field_length(self) -> int: 486 if self in [ 487 MstatusFieldOffsets.VS, 488 MstatusFieldOffsets.MPP, 489 MstatusFieldOffsets.FS, 490 MstatusFieldOffsets.XS, 491 MstatusFieldOffsets.UXL, 492 MstatusFieldOffsets.SXL, 493 ]: 494 return 2 495 496 return 1 497 498 499 @unique 500 class MenvcfgFieldOffsets(IntEnum): 501 FIOM = 0 # Fence of I/O implies Memory 502 LPE = 2 # Landing Pad Enable 503 SSE = 3 # Supervisor Shadow Stack Enable 504 CBIE = 4 # Cache Block Invalidate instruction Enable 505 CBCFE = 6 # Cache Block Clean and Flush instruction Enable 506 CBZE = 7 # Cache Block Zero instruction Enable 507 PMM = 32 # Pointer Masking for Machine mode 508 DTE = 59 # Double Trap Enable 509 CDE = 60 # Counter Delegation Enable 510 ADUE = 61 # Accessed Dirty Update Enable 511 PBMTE = 62 # Page-Based Memory Types Enable 512 STCE = 63 # STimeCmp Enable 513 514 def field_length(self) -> int: 515 if self in [ 516 MenvcfgFieldOffsets.PMM, 517 MenvcfgFieldOffsets.CBIE, 518 ]: 519 return 2 520 521 return 1 522 523 524 @unique 525 class CounterEnableFieldOffsets(IntEnum): 526 CY = 0 # Cycle counter enable 527 TM = 1 # Timer counter enable 528 IR = 2 # Instret counter enable 529 HPM3 = 3 # HPMCOUNTER3 enable 530 HPM4 = 4 # HPMCOUNTER4 enable 531 HPM5 = 5 # HPMCOUNTER5 enable 532 HPM6 = 6 # HPMCOUNTER6 enable 533 HPM7 = 7 # HPMCOUNTER7 enable 534 HPM8 = 8 # HPMCOUNTER8 enable 535 HPM9 = 9 # HPMCOUNTER9 enable 536 HPM10 = 10 # HPMCOUNTER10 enable 537 HPM11 = 11 # HPMCOUNTER11 enable 538 HPM12 = 12 # HPMCOUNTER12 enable 539 HPM13 = 13 # HPMCOUNTER13 enable 540 HPM14 = 14 # HPMCOUNTER14 enable 541 HPM15 = 15 # HPMCOUNTER15 enable 542 HPM16 = 16 # HPMCOUNTER16 enable 543 HPM17 = 17 # HPMCOUNTER17 enable 544 HPM18 = 18 # HPMCOUNTER18 enable 545 HPM19 = 19 # HPMCOUNTER19 enable 546 HPM20 = 20 # HPMCOUNTER20 enable 547 HPM21 = 21 # HPMCOUNTER21 enable 548 HPM22 = 22 # HPMCOUNTER22 enable 549 HPM23 = 23 # HPMCOUNTER23 enable 550 HPM24 = 24 # HPMCOUNTER24 enable 551 HPM25 = 25 # HPMCOUNTER25 enable 552 HPM26 = 26 # HPMCOUNTER26 enable 553 HPM27 = 27 # HPMCOUNTER27 enable 554 HPM28 = 28 # HPMCOUNTER28 enable 555 HPM29 = 29 # HPMCOUNTER29 enable 556 HPM30 = 30 # HPMCOUNTER30 enable 557 HPM31 = 31 # HPMCOUNTER31 enable 558 559 560 sstatus_field_subset: Set[MstatusFieldOffsets] = frozenset( 561 { 562 MstatusFieldOffsets.SIE, 563 MstatusFieldOffsets.SPIE, 564 MstatusFieldOffsets.UBE, 565 MstatusFieldOffsets.SPP, 566 MstatusFieldOffsets.VS, 567 MstatusFieldOffsets.FS, 568 MstatusFieldOffsets.XS, 569 MstatusFieldOffsets.SUM, 570 MstatusFieldOffsets.MXR, 571 MstatusFieldOffsets.SPELP, 572 MstatusFieldOffsets.SDT, 573 MstatusFieldOffsets.SD, 574 } 575 ) 576 577 senvcfg_field_subset: Set[MenvcfgFieldOffsets] = frozenset( 578 { 579 MenvcfgFieldOffsets.FIOM, 580 MenvcfgFieldOffsets.LPE, 581 MenvcfgFieldOffsets.SSE, 582 MenvcfgFieldOffsets.CBIE, 583 MenvcfgFieldOffsets.CBCFE, 584 MenvcfgFieldOffsets.CBZE, 585 } 586 )