common.py
1 from abc import abstractmethod 2 from amaranth import * 3 4 from coreblocks.params import GenParams 5 from coreblocks.interface.layouts import UnsignedMulUnitLayouts 6 from transactron import * 7 from transactron.core import def_method 8 9 __all__ = ["MulBaseUnsigned", "DSPMulUnit"] 10 11 12 class MulBaseUnsigned(Elaboratable): 13 """ 14 Abstract module creating common interface of unsigned multiplication module. 15 16 Attributes 17 ---------- 18 issue: Method(i=gen.get(UnsignedMulUnitLayouts).issue), in 19 Method used for requesting computation. 20 accept: Method(i=gen.get(UnsignedMulUnitLayouts).accept), out 21 Method used for getting result of requested computation. 22 """ 23 24 def __init__(self, gen_params: GenParams, dsp_width: int = 32): 25 """ 26 Parameters 27 ---------- 28 gen_params: GenParams 29 Core generation parameters. 30 """ 31 self.gen_params = gen_params 32 self.dsp_width = dsp_width 33 34 layout = gen_params.get(UnsignedMulUnitLayouts) 35 36 self.issue = Method(i=layout.issue) 37 self.accept = Method(o=layout.accept) 38 39 @abstractmethod 40 def elaborate(self, platform) -> TModule: 41 raise NotImplementedError() 42 43 44 class DSPMulUnit(Elaboratable): 45 """ 46 Module for 1 clock cycle multiplication, designed to be replaced with a DSP block by the synthesis tool. 47 48 Attributes 49 ---------- 50 compute: Method(i=[("i1", n), ("i2", n)], o=[("o", 2 * n)]), in out 51 Method for requesting computations and getting results in this same cycle. 52 """ 53 54 def __init__(self, dsp_width: int): 55 """ 56 Parameters 57 ---------- 58 dsp_width: int 59 Bit width of multiplied numbers. 60 """ 61 self.n = n = dsp_width 62 63 self.compute = Method(i=[("i1", n), ("i2", n)], o=[("o", 2 * n)]) 64 65 def elaborate(self, platform): 66 m = TModule() 67 68 @def_method(m, self.compute) 69 def _(arg): 70 # Here will be connection to DSP but right now I have no idea how to do it 71 return {"o": arg.i1 * arg.i2} 72 73 return m