1  from collections.abc import Collection
  2  
  3  import dataclasses
  4  from dataclasses import dataclass, field
  5  
  6  from typing import Self
  7  from transactron.utils.typing import type_self_kwargs_as
  8  from amaranth_types.memory import AbstractMemoryConstructor
  9  from amaranth.lib.memory import Memory
 10  
 11  from coreblocks.arch.isa import Extension
 12  from coreblocks.params.fu_params import BlockComponentParams
 13  
 14  from coreblocks.func_blocks.fu.common.rs_func_block import RSBlockComponent
 15  from coreblocks.func_blocks.fu.common.fifo_rs import FifoRS
 16  from coreblocks.func_blocks.fu.alu import ALUComponent
 17  from coreblocks.func_blocks.fu.shift_unit import ShiftUnitComponent
 18  from coreblocks.func_blocks.fu.jumpbranch import JumpComponent
 19  from coreblocks.func_blocks.fu.mul_unit import MulComponent, MulType
 20  from coreblocks.func_blocks.fu.div_unit import DivComponent
 21  from coreblocks.func_blocks.fu.zbc import ZbcComponent
 22  from coreblocks.func_blocks.fu.zbkx import ZbkxComponent
 23  from coreblocks.func_blocks.fu.zbs import ZbsComponent
 24  from coreblocks.func_blocks.fu.exception import ExceptionUnitComponent
 25  from coreblocks.func_blocks.fu.priv import PrivilegedUnitComponent
 26  from coreblocks.func_blocks.fu.lsu.dummyLsu import LSUComponent
 27  from coreblocks.func_blocks.fu.lsu.pma import PMARegion
 28  from coreblocks.func_blocks.fu.lsu.lsu_atomic_wrapper import LSUAtomicWrapperComponent
 29  from coreblocks.func_blocks.csr.csr_unit import CSRBlockComponent
 30  from coreblocks.arch.isa_consts import SatpMode
 31  
 32  __all__ = [
 33      "CoreConfiguration",
 34      "basic_core_config",
 35      "tiny_core_config",
 36      "small_linux_config",
 37      "full_core_config",
 38      "test_core_config",
 39  ]
 40  
 41  basic_configuration: tuple[BlockComponentParams, ...] = (
 42      RSBlockComponent(
 43          [
 44              ALUComponent(),
 45              ShiftUnitComponent(),
 46              JumpComponent(),
 47              ExceptionUnitComponent(),
 48              PrivilegedUnitComponent(supervisor_enable=True),
 49          ],
 50          rs_entries=4,
 51      ),
 52      RSBlockComponent(
 53          [
 54              MulComponent(mul_unit_type=MulType.PIPELINED_MUL),
 55              DivComponent(),
 56          ],
 57          rs_entries=2,
 58      ),
 59      RSBlockComponent([LSUComponent()], rs_entries=2, rs_type=FifoRS),
 60      CSRBlockComponent(),
 61  )
 62  
 63  
 64  @dataclass(kw_only=True)
 65  class _CoreConfigurationDataClass:
 66      """
 67      Core configuration parameters.
 68  
 69      Parameters
 70      ----------
 71      xlen: int
 72          Bit width of Core.
 73      func_units_config: Collection[BlockComponentParams]
 74          Configuration of Functional Units and Reservation Stations.
 75          Example: [RSBlockComponent([ALUComponent()], rs_entries=4), LSUBlockComponent()]
 76      compressed: bool
 77          Enables 16-bit Compressed instructions. Enables Zca, Zcf, and Zcd extensions as permitted by the ISA.
 78      zcb: bool
 79          Enables the Zcb compressed code-size reduction extension.
 80      embedded: bool
 81          Enables Reduced Integer (E) extension.
 82      marchid: int
 83          The value of the MARCHID CSR.
 84      mimpid: int
 85          The value of the MIMPID CSR.
 86      debug_signals: bool
 87          Enable debug signals (for example hardware metrics etc). If disabled, none of them will be synthesized.
 88      phys_regs_bits: int
 89          Size of the Physical Register File is 2**phys_regs_bits.
 90      rob_entries_bits: int
 91          Size of the Reorder Buffer is 2**rob_entries_bits.
 92      start_pc: int
 93          Initial Program Counter value.
 94      checkpoint_count: int
 95          Size of active checkpoints storage. This is a maximum speculation depth. It doesn't include current state.
 96      tag_bits: int
 97          Numer of tags is 2**tag_bits. Tag space fits unique monotonic checkpoint ids of all instructions
 98          currently in core, including instructions from already rolled-back checkpoints, that didn't leave the
 99          pipeline yet. Tag space size must be greater that checkpoint count.
100      icache_enable: bool
101          Enable instruction cache. If disabled, requests are bypassed directly to the bus.
102      icache_ways: int
103          Associativity of the instruction cache.
104      icache_sets_bits: int
105          Log of the number of sets of the instruction cache.
106      icache_line_bytes_log: int
107          Log of the cache line size (in bytes).
108      fetch_block_bytes_log: int
109          Log of the size of the fetch block (in bytes).
110      instr_buffer_size: int
111          Size of the instruction buffer.
112      interrupt_custom_count: int
113          Number of custom/local async interrupts to support. First interrupt will be registered at id 16.
114      interrupt_custom_edge_trig_mask: int
115          Bit mask specifying if interrupt should be edge or level triggered. If nth bit is set to 1, interrupt
116          with id 16+n will be considered as edge triggered and clearable via `mip`. In other case bit `mip` is
117          read-only and directly connected to input signal (implementation must provide clearing method)
118      user_mode: bool
119          Enable User Mode.
120      supervisor_mode: bool
121          Enable Supervisor Mode.
122      asidlen: int
123          Number of writable ASID bits in SATP.
124      supported_vm_schemes: Collection[SatpMode]
125          SATP MODE values accepted by this core.
126      phys_addr_bits: int | None
127          Width of physical addresses in bits. If not set, defaults to 34 for RV32 if supported_vm_schemes has
128          SV32 enabled, 32 for RV32 with only BARE mode and 56 for RV64.
129      hpm_counters_count: int
130          Number of implemented HPM counters (mhpmcounter3..mhpmcounter31).
131      pmp_register_count: int
132          Number of Physical Memory Protection CSR entries. Valid values are: 0, 16, and 64.
133      pmp_grain_log: int
134          Log of the PMP grain size (in bytes).
135          Must be >= 2 if PMP registers are enabled.
136          When PMP and icache are both enabled, must be >= icache_line_bytes_log.
137      allow_partial_extensions: bool
138          Allow partial support of extensions.
139      extra_verification: bool
140          Enables generation of additional hardware checks (asserts via logging system). Defaults to True.
141      multiport_memory_type: AbstractMemoryConstructor
142          The type of multiport synchronous memory to be used in the core, e.g. in superscalar structures.
143      _implied_extensions: Extension
144          Bit flag specifying enabled extensions that are not specified by func_units_config. Used in internal tests.
145      _generate_test_hardware: bool
146          Enables generation of additional hardware used for use in internal unit tests.
147      pma : list[PMARegion]
148          Definitions of PMAs per contiguous segments of memory.
149      """
150  
151      def __post_init__(self):
152          self.func_units_config = [
153              dataclasses.replace(conf, rs_number=k) if hasattr(conf, "rs_number") else conf
154              for k, conf in enumerate(self.func_units_config)
155          ]
156  
157      xlen: int = 32
158      func_units_config: Collection[BlockComponentParams] = basic_configuration
159  
160      compressed: bool = False
161      zcb: bool = False
162      embedded: bool = False
163  
164      marchid: int = 44
165      mimpid: int = 0
166  
167      debug_signals: bool = True
168  
169      phys_regs_bits: int = 6
170      rob_entries_bits: int = 7
171      start_pc: int = 0
172  
173      frontend_superscalarity: int = 1
174      announcement_superscalarity: int = 1
175      retirement_superscalarity: int = 1
176  
177      checkpoint_count: int = 16
178      tag_bits: int = 5
179  
180      icache_enable: bool = True
181      icache_ways: int = 2
182      icache_sets_bits: int = 7
183      icache_line_bytes_log: int = 5
184  
185      fetch_block_bytes_log: int = 2
186  
187      instr_buffer_size: int = 4
188  
189      interrupt_custom_count: int = 16
190      interrupt_custom_edge_trig_mask: int = 0
191  
192      user_mode: bool = True
193      supervisor_mode: bool = True
194  
195      asidlen: int = 0
196      supported_vm_schemes: Collection[SatpMode] = (SatpMode.BARE,)
197      phys_addr_bits: int | None = None
198      hpm_counters_count: int = 0
199  
200      pmp_register_count: int = 0
201      pmp_grain_log: int = 5
202  
203      allow_partial_extensions: bool = False
204  
205      extra_verification: bool = True
206  
207      multiport_memory_type: AbstractMemoryConstructor = Memory
208  
209      _implied_extensions: Extension = Extension(0)
210      _generate_test_hardware: bool = False
211  
212      pma: list[PMARegion] = field(
213          default_factory=lambda: [PMARegion(0xE0000000, 0xFFFFFFFF, mmio=True)]
214      )  # default I/O region used in LiteX coreblocks
215  
216  
217  class CoreConfiguration(_CoreConfigurationDataClass):
218      @type_self_kwargs_as(_CoreConfigurationDataClass.__init__)
219      def replace(self, **kwargs) -> Self:
220          return dataclasses.replace(self, **kwargs)
221  
222  
223  # Default core configuration
224  basic_core_config = CoreConfiguration()
225  
226  # Minimal core configuration
227  tiny_core_config = CoreConfiguration(
228      embedded=True,
229      func_units_config=(
230          RSBlockComponent(
231              [ALUComponent(), ShiftUnitComponent(), JumpComponent(), ExceptionUnitComponent()], rs_entries=2
232          ),
233          RSBlockComponent([LSUComponent()], rs_entries=2, rs_type=FifoRS),
234      ),
235      phys_regs_bits=basic_core_config.phys_regs_bits - 1,
236      rob_entries_bits=basic_core_config.rob_entries_bits - 1,
237      icache_enable=False,
238      user_mode=False,
239      supervisor_mode=False,
240      pmp_grain_log=2,
241  )
242  
243  # Basic core config with minimal additions required for Linux
244  small_linux_config = CoreConfiguration(
245      func_units_config=(
246          RSBlockComponent(
247              [
248                  ALUComponent(),
249                  ShiftUnitComponent(),
250                  JumpComponent(),
251                  ExceptionUnitComponent(),
252                  PrivilegedUnitComponent(supervisor_enable=True),
253              ],
254              rs_entries=4,
255          ),
256          RSBlockComponent(
257              [
258                  MulComponent(mul_unit_type=MulType.PIPELINED_MUL),
259                  DivComponent(),
260              ],
261              rs_entries=2,
262          ),
263          RSBlockComponent([LSUAtomicWrapperComponent(LSUComponent())], rs_entries=2, rs_type=FifoRS),
264          CSRBlockComponent(),
265      )
266  )
267  
268  # Core configuration with all supported components
269  full_core_config = CoreConfiguration(
270      func_units_config=(
271          RSBlockComponent(
272              [
273                  ALUComponent(zba_enable=True, zbb_enable=True, zicond_enable=True),
274                  ShiftUnitComponent(zbb_enable=True),
275                  ZbcComponent(),
276                  ZbkxComponent(),
277                  ZbsComponent(),
278              ],
279              rs_entries=2,  # reduced RS size to reduce impact of bad predictions
280          ),
281          RSBlockComponent(
282              [
283                  ALUComponent(zba_enable=True, zbb_enable=True, zicond_enable=True),
284                  ShiftUnitComponent(zbb_enable=True),
285                  ZbcComponent(),
286                  ZbkxComponent(),
287                  ZbsComponent(),
288                  JumpComponent(),
289                  ExceptionUnitComponent(),
290                  PrivilegedUnitComponent(supervisor_enable=True),
291              ],
292              rs_entries=2,  # reduced RS size to reduce impact of bad predictions
293          ),
294          RSBlockComponent(
295              [
296                  MulComponent(mul_unit_type=MulType.PIPELINED_MUL),
297                  DivComponent(),
298              ],
299              rs_entries=2,
300          ),
301          RSBlockComponent([LSUAtomicWrapperComponent(LSUComponent())], rs_entries=4, rs_type=FifoRS),
302          CSRBlockComponent(),
303      ),
304      compressed=True,
305      zcb=True,
306      fetch_block_bytes_log=4,
307      instr_buffer_size=16,
308      pmp_register_count=16,
309      frontend_superscalarity=2,
310      announcement_superscalarity=2,
311  )
312  
313  # Core configuration used in internal testbenches
314  test_core_config = CoreConfiguration(
315      func_units_config=tuple(RSBlockComponent([], rs_entries=4) for _ in range(2)),
316      rob_entries_bits=7,
317      phys_regs_bits=7,
318      interrupt_custom_count=2,
319      interrupt_custom_edge_trig_mask=0b01,
320      _implied_extensions=Extension.I,
321      _generate_test_hardware=True,
322  )