/ dm_compat.h
dm_compat.h
1 #ifndef _DM_COMPAT_H_ 2 #define _DM_COMPAT_H_ 3 4 #include "miner.h" 5 6 #include <linux/i2c-dev.h> 7 #include <linux/i2c.h> 8 #include <asm/ioctls.h> 9 #include <sys/stat.h> 10 #include <fcntl.h> 11 #include <unistd.h> 12 #include <sys/ioctl.h> 13 #include <sys/mman.h> 14 #include <ctype.h> 15 #include <limits.h> 16 #include <linux/watchdog.h> 17 #include <stdio.h> 18 #include <stdint.h> 19 #include <stdbool.h> 20 #include <pthread.h> 21 #include <linux/spi/spidev.h> 22 #include <linux/types.h> 23 24 25 #define NUMARGS(...) ((int)(sizeof((int[]){(int)__VA_ARGS__})/sizeof(int))) 26 27 #define FSCANF(STREAM, FORMAT, ...) \ 28 do { \ 29 if (unlikely(fscanf((STREAM), (FORMAT), __VA_ARGS__) != NUMARGS(__VA_ARGS__))) { \ 30 applog(LOG_ERR, "Failed to fscanf %d args from %s %s line %d", \ 31 NUMARGS(__VA_ARGS__), __FILE__, __func__, __LINE__); \ 32 } \ 33 } while (0) 34 35 #define FREAD(PTR, SIZE, NMEMB, STREAM) \ 36 do { \ 37 if (unlikely(fread((PTR), (SIZE), (NMEMB), (STREAM)) != NMEMB)) \ 38 applog(LOG_ERR, "Failed to fread size %d nmemb %d from %s %s line %d", \ 39 (SIZE), (NMEMB), __FILE__, __func__, __LINE__); \ 40 } while (0) 41 42 #define FWRITE(PTR, SIZE, NMEMB, STREAM) \ 43 do { \ 44 if (unlikely(fwrite((PTR), (SIZE), (NMEMB), (STREAM)) != NMEMB)) \ 45 applog(LOG_ERR, "Failed to fwrite size %d nmemb %d from %s %s line %d", \ 46 (SIZE), (NMEMB), __FILE__, __func__, __LINE__); \ 47 } while (0) 48 49 50 #define WRITE(FILDES, BUF, NBYTE) \ 51 do { \ 52 int ret = write((FILDES), (BUF), (NBYTE)); \ 53 if (unlikely(ret != (int)(NBYTE))) { \ 54 if (ret == -1) { \ 55 applog(LOG_ERR, "Failed to write size %d from %s %s line %d with errno %d:%s", \ 56 (NBYTE), __FILE__, __func__, __LINE__, errno, strerror(errno)); \ 57 } else { \ 58 applog(LOG_WARNING, "Failed to write size %d from %s %s line %d", \ 59 (NBYTE), __FILE__, __func__, __LINE__); \ 60 } \ 61 } \ 62 } while (0) 63 64 65 #define READ(FILDES, BUF, NBYTE) \ 66 do { \ 67 int ret = read((FILDES), (BUF), (NBYTE)); \ 68 if (unlikely(ret != (int)(NBYTE))) { \ 69 if (ret == -1) { \ 70 applog(LOG_ERR, "Failed to read size %d from %s %s line %d with errno %d:%s", \ 71 (NBYTE), __FILE__, __func__, __LINE__, errno, strerror(errno)); \ 72 } else { \ 73 applog(LOG_WARNING, "Failed to read size %d from %s %s line %d", \ 74 (NBYTE), __FILE__, __func__, __LINE__); \ 75 } \ 76 } \ 77 } while (0) 78 79 80 /* MCOMPAT_CHAIN */ 81 82 typedef struct MCOMPAT_CHAIN_TAG{ 83 // 84 bool (*power_on)(unsigned char); 85 // 86 bool (*power_down)(unsigned char); 87 // 88 bool (*hw_reset)(unsigned char); 89 // 90 bool (*power_on_all)(void); 91 // 92 bool (*power_down_all)(void); 93 }MCOMPAT_CHAIN_T; 94 95 96 97 void init_mcompat_chain(void); 98 void exit_mcompat_chain(void); 99 100 void register_mcompat_chain(MCOMPAT_CHAIN_T * ops); 101 102 103 bool mcompat_chain_power_on(unsigned char chain_id); 104 105 bool mcompat_chain_power_down(unsigned char chain_id); 106 107 bool mcompat_chain_hw_reset(unsigned char chain_id); 108 109 110 /* MCOMPAT_FAN */ 111 112 extern int g_temp_hi_thr; 113 extern int g_temp_lo_thr; 114 extern int g_temp_start_thr; 115 extern int g_dangerous_temp; 116 extern int g_work_temp; 117 118 typedef struct { 119 int final_temp_avg; 120 int final_temp_hi; 121 int final_temp_lo; 122 int temp_highest[3]; 123 int temp_lowest[3]; 124 }mcompat_temp_s; 125 126 127 typedef struct { 128 int temp_hi_thr; 129 int temp_lo_thr; 130 int temp_start_thr; 131 int dangerous_stat_temp; 132 int work_temp; 133 int default_fan_speed; 134 }mcompat_temp_config_s; 135 136 137 typedef struct { 138 int fd; 139 int last_valid_temp; 140 141 int speed; 142 int last_fan_speed; 143 int last_fan_temp; 144 mcompat_temp_s * mcompat_temp; 145 int temp_average; 146 int temp_highest; 147 int temp_lowest; 148 }mcompat_fan_temp_s; 149 150 151 extern void mcompat_fan_temp_init(unsigned char fan_id,mcompat_temp_config_s temp_config); 152 extern void mcompat_fan_speed_set(unsigned char fan_id, int speed); 153 extern void mcompat_fan_speed_update_hub(mcompat_fan_temp_s *fan_temp); 154 155 156 /* MCOMPAT_CMD */ 157 158 typedef struct MCOMPAT_CMD_TAG{ 159 // 160 void (*set_speed)(unsigned char, int); 161 // 162 bool (*cmd_reset)(unsigned char, unsigned char, unsigned char *, unsigned char *); 163 // 164 int (*cmd_bist_start)(unsigned char, unsigned char); 165 // 166 bool (*cmd_bist_collect)(unsigned char, unsigned char); 167 // 168 bool (*cmd_bist_fix)(unsigned char, unsigned char); 169 // 170 bool (*cmd_write_register)(unsigned char, unsigned char, unsigned char *, int); 171 // 172 bool (*cmd_read_register)(unsigned char, unsigned char, unsigned char *, int); 173 // 174 bool (*cmd_read_write_reg0d)(unsigned char, unsigned char, unsigned char *, int, unsigned char *); 175 // 176 bool (*cmd_write_job)(unsigned char, unsigned char, unsigned char *, int); 177 // 178 bool (*cmd_read_result)(unsigned char, unsigned char, unsigned char *, int); 179 // 180 bool (*cmd_auto_nonce)(unsigned char, int, int); 181 // 182 bool (*cmd_read_nonce)(unsigned char, unsigned char *, int); 183 184 bool (*cmd_get_temp)(mcompat_fan_temp_s *temp_ctrl); 185 }MCOMPAT_CMD_T; 186 187 188 189 void init_mcompat_cmd(void); 190 void exit_mcompat_cmd(void); 191 192 void register_mcompat_cmd(MCOMPAT_CMD_T * cmd_ops_p); 193 194 195 /* MCOMPAT_GPIO */ 196 197 typedef struct MCOMPAT_GPIO_TAG{ 198 // 199 void (*set_power_en)(unsigned char, int); 200 // 201 void (*set_start_en)(unsigned char, int); 202 // 203 bool (*set_reset)(unsigned char, int); 204 // 205 void (*set_led)(unsigned char, int); 206 // 207 int (*get_plug)(unsigned char); 208 // 209 bool (*set_vid)(unsigned char, int); 210 // 211 void (*set_green_led)(int mode); 212 // 213 void (*set_red_led)(int mode); 214 // 215 int (*get_button)(void); 216 }MCOMPAT_GPIO_T; 217 218 219 220 void init_mcompat_gpio(void); 221 void exit_mcompat_gpio(void); 222 223 void register_mcompat_gpio(MCOMPAT_GPIO_T * ops); 224 225 /* MCOMPAT_GPIO_I2C */ 226 227 #define _SCL_PIN (0) 228 #define _SDA_PIN (1) 229 230 void mcompat_gpio_i2c_init(void); 231 void mcompat_gpio_i2c_deinit(void); 232 233 void mcompat_gpio_i2c_send_byte(uint8_t data); 234 uint8_t mcompat_gpio_i2c_recv_byte(void); 235 236 bool mcompat_gpio_i2c_send_buf(uint8_t *buf, uint8_t buf_len, uint8_t dev_addr, uint16_t reg_addr); 237 bool mcompat_gpio_i2c_recv_buf(uint8_t *buf, uint8_t buf_len, uint8_t dev_addr, uint16_t reg_addr); 238 239 240 /* MCOMPAT_PWM */ 241 242 typedef struct MCOMPAT_PWM_TAG{ 243 // 244 void (*set_pwm)(unsigned char, int, int); 245 }MCOMPAT_PWM_T; 246 247 248 249 void init_mcompat_pwm(void); 250 void exit_mcompat_pwm(void); 251 252 void register_mcompat_pwm(MCOMPAT_PWM_T * ops); 253 254 /* MCOMPAT_TEMP */ 255 256 typedef struct _c_temp 257 { 258 short tmp_lo; // lowest temperature 259 short tmp_hi; // highest temperature 260 short tmp_avg; // average temperature 261 bool optimal; // temp considered in optimal range 262 } c_temp; 263 264 extern int mcompat_temp_to_centigrade(int temp); 265 extern bool mcompat_get_chain_temp(unsigned char chain_id, c_temp *chain_tmp); 266 extern void mcompat_get_chip_temp(int chain_id, int *chip_temp); 267 268 /* MCOMPAT_WATCHDOG */ 269 270 #define MCOMPAT_WATCHDOG_DEV ("/dev/watchdog0") 271 272 void mcompat_watchdog_keep_alive(void); 273 274 void mcompat_watchdog_open(void); 275 276 void mcompat_watchdog_set_timeout(int timeout); 277 278 void mcompat_watchdog_close(void); 279 280 281 /* MCOMPAT_LIB */ 282 283 #define MCOMPAT_LIB_MINER_TYPE_FILE ("/tmp/type") 284 #define MCOMPAT_LIB_HARDWARE_VERSION_FILE ("/tmp/hwver") 285 286 #define MCOMPAT_LIB_HARDWARE_VERSION_G9 (9) 287 #define MCOMPAT_LIB_HARDWARE_VERSION_G19 (19) 288 #define MCOMPAT_LIB_HARDWARE_VERSION_ERR (-1) 289 290 #define MCOMPAT_LIB_MINER_TYPE_T1 (1) 291 #define MCOMPAT_LIB_MINER_TYPE_T2 (2) 292 #define MCOMPAT_LIB_MINER_TYPE_T3 (3) 293 #define MCOMPAT_LIB_MINER_TYPE_T4 (4) 294 #define MCOMPAT_LIB_MINER_TYPE_D11 (5) 295 #define MCOMPAT_LIB_MINER_TYPE_D12 (6) 296 #define MCOMPAT_LIB_MINER_TYPE_ERR (-1) 297 298 #define MCOMPAT_LIB_VID_VID_TYPE (0) 299 #define MCOMPAT_LIB_VID_GPIO_I2C_TYPE (1) 300 #define MCOMPAT_LIB_VID_UART_TYPE (2) 301 #define MCOMPAT_LIB_VID_I2C_TYPE (3) 302 #define MCOMPAT_LIB_VID_ERR_TYPE (-1) 303 304 #define REG_LENGTH (12) 305 #define VID_MAX (31) 306 #define VID_MIN (0) 307 308 309 int mcompat_get_shell_cmd_rst(char *cmd, char *result, int size); 310 311 int misc_call_api(char *command, char *host, short int port); 312 313 bool misc_tcp_is_ok(char *host, short int port); 314 315 char *misc_trim(char *str); 316 317 int misc_get_board_version(void); 318 319 int misc_get_miner_type(void); 320 321 int misc_get_vid_type(void); 322 323 void misc_system(const char *cmd, char *rst_buf, int buf_size); 324 325 void mcompat_configure_tvsensor(int chain_id, int chip_id, bool is_tsensor); 326 327 void mcompat_cfg_tsadc_divider(int chain_id,unsigned int pll_clk); 328 329 void mcompat_get_chip_volt(int chain_id, int *chip_volt); 330 331 int mcompat_find_chain_vid(int chain_id, int chip_num, int vid_start, double volt_target); 332 333 double mcompat_get_average_volt(int *volt, int size); 334 335 336 /* MCOMPAT_DRV */ 337 338 #define PLATFORM_ZYNQ_SPI_G9 (0x01) 339 #define PLATFORM_ZYNQ_SPI_G19 (0x02) 340 #define PLATFORM_ZYNQ_HUB_G9 (0x03) 341 #define PLATFORM_ZYNQ_HUB_G19 (0x04) 342 #define PLATFORM_SOC (0x10) 343 #define PLATFORM_ORANGE_PI (0x20) 344 345 #define SPI_SPEED_390K (0) 346 #define SPI_SPEED_781K (1) 347 #define SPI_SPEED_1562K (2) 348 #define SPI_SPEED_3125K (3) 349 #define SPI_SPEED_6250K (4) 350 #define SPI_SPEED_9960K (5) 351 352 #define MCOMPAT_LOG_DEBUG (1) 353 #define MCOMPAT_LOG_INFO (2) 354 #define MCOMPAT_LOG_NOTICE (3) 355 #define MCOMPAT_LOG_WARNING (4) 356 #define MCOMPAT_LOG_ERR (5) 357 #define MCOMPAT_LOG_CRIT (6) 358 #define MCOMPAT_LOG_ALERT (7) 359 #define MCOMPAT_LOG_EMERG (8) 360 361 362 extern void sys_platform_debug_init(int debug_level); 363 364 extern bool sys_platform_init(int platform, int miner_type, int chain_num, int chip_num); 365 366 extern bool sys_platform_exit(); 367 368 369 extern bool mcompat_set_spi_speed(unsigned char chain_id, int index); 370 371 extern bool mcompat_cmd_reset(unsigned char chain_id, unsigned char chip_id, unsigned char *in, unsigned char *out); 372 373 extern int mcompat_cmd_bist_start(unsigned char chain_id, unsigned char chip_id); 374 375 extern bool mcompat_cmd_bist_collect(unsigned char chain_id, unsigned char chip_id); 376 377 extern bool mcompat_cmd_bist_fix(unsigned char chain_id, unsigned char chip_id); 378 379 extern bool mcompat_cmd_write_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len); 380 381 extern bool mcompat_cmd_read_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len); 382 383 extern bool mcompat_cmd_read_write_reg0d(unsigned char chain_id, unsigned char chip_id, unsigned char *in, int len, unsigned char *out); 384 385 extern bool mcompat_cmd_read_result(unsigned char chain_id, unsigned char chip_id, unsigned char *res, int len); 386 387 extern bool mcompat_cmd_write_job(unsigned char chain_id, unsigned char chip_id, unsigned char *job, int len); 388 389 extern bool mcompat_cmd_auto_nonce(unsigned char chain_id, int mode, int len); 390 391 extern bool mcompat_cmd_read_nonce(unsigned char chain_id, unsigned char *res, int len); 392 393 extern bool mcompat_cmd_get_temp(mcompat_fan_temp_s * fan_temp); 394 395 extern bool mcompat_get_chain_temp(unsigned char chain_id, c_temp *chain_tmp); 396 397 extern void mcompat_set_power_en(unsigned char chain_id, int val); 398 399 extern void mcompat_set_start_en(unsigned char chain_id, int val); 400 401 extern bool mcompat_set_reset(unsigned char chain_id, int val); 402 403 extern void mcompat_set_led(unsigned char chain_id, int val); 404 405 extern bool mcompat_set_vid(unsigned char chain_id, int val); 406 407 extern bool mcompat_set_vid_by_step(unsigned char chain_id, int start_vid, int target_vid); 408 409 extern void mcompat_set_pwm(unsigned char fan_id, int frequency, int duty); 410 411 extern int mcompat_get_plug(unsigned char chain_id); 412 413 extern int mcompat_get_button(void); 414 415 extern void mcompat_set_green_led(int mode); 416 417 extern void mcompat_set_red_led(int mode); 418 419 extern bool mcompat_chain_power_on(unsigned char chain_id); 420 421 extern bool mcompat_chain_power_down(unsigned char chain_id); 422 423 extern bool mcompat_chain_hw_reset(unsigned char chain_id); 424 425 extern bool mcompat_chain_power_on_all(void); 426 427 extern bool mcompat_chain_power_down_all(void); 428 429 430 #define MCOMPAT_CONFIG_MAX_CHAIN_NUM (8) 431 #define MCOMPAT_CONFIG_MAX_CHIP_NUM (80) 432 #define MCOMPAT_CONFIG_MAX_JOB_LEN (92) 433 #define MCOMPAT_CONFIG_MAX_CMD_LENGTH (256) 434 435 #define MAGIC_NUM (100) 436 437 #define CMD_BIST_START (0x01) 438 #define CMD_BIST_COLLECT (0x0b) 439 #define CMD_BIST_FIX (0x03) 440 #define CMD_RESET (0x04) 441 #define CMD_RESETBC (0x05) 442 #define CMD_WRITE_JOB (0x07) 443 #define CMD_WRITE_JOB_T1 (0x0c) 444 #define CMD_READ_RESULT (0x08) 445 #define CMD_WRITE_REG (0x09) 446 #define CMD_READ_REG (0x0a) 447 #define CMD_WRITE_REG0d (0x0d) 448 #define CMD_POWER_ON (0x02) 449 #define CMD_POWER_OFF (0x06) 450 #define CMD_POWER_RESET (0x0c) 451 452 #define RESP_READ_REG (0x1a) 453 454 #define CMD_ADDR_BROADCAST (0x00) 455 #define CMD_HL (2) 456 #define CMD_RESET_DL (4) 457 #define CMD_RESET_TL (CMD_HL + CMD_RESET_DL) 458 459 460 #define ASIC_MCOMPAT_FAN_PWM_STEP (5) 461 #define ASIC_MCOMPAT_FAN_PWM_DUTY_MAX (100) 462 #define ASIC_MCOMPAT_FAN_PWM_FREQ_TARGET (20000) 463 #define ASIC_MCOMPAT_FAN_PWM_FREQ (20000) 464 #define FAN_CNT ( 2 ) 465 #define ASIC_MCOMPAT_FAN_TEMP_MAX_THRESHOLD (100) 466 #define ASIC_MCOMPAT_FAN_TEMP_UP_THRESHOLD (55) 467 #define ASIC_MCOMPAT_FAN_TEMP_DOWN_THRESHOLD (35) 468 469 #define MCOMPAT_VID_UART_PATH ("/dev/ttyPS1") 470 471 472 #define MCOMPAT_CONFIG_CMD_MAX_LEN (MCOMPAT_CONFIG_MAX_JOB_LEN + MCOMPAT_CONFIG_MAX_CHAIN_NUM * 2 * 2) 473 #define MCOMPAT_CONFIG_CMD_RST_MAX_LEN (MCOMPAT_CONFIG_CMD_MAX_LEN) 474 475 /* SPI */ 476 #define MCOMPAT_CONFIG_SPI_DEFAULT_CS_LINE (0) 477 #define MCOMPAT_CONFIG_SPI_DEFAULT_MODE (SPI_MODE_1) 478 #define MCOMPAT_CONFIG_SPI_DEFAULT_SPEED (1500000) 479 #define MCOMPAT_CONFIG_SPI_DEFAULT_BITS_PER_WORD (8) 480 /* GPIO */ 481 #define MCOMPAT_CONFIG_CHAIN0_POWER_EN_GPIO (872) 482 #define MCOMPAT_CONFIG_CHAIN1_POWER_EN_GPIO (873) 483 #define MCOMPAT_CONFIG_CHAIN2_POWER_EN_GPIO (874) 484 #define MCOMPAT_CONFIG_CHAIN3_POWER_EN_GPIO (875) 485 #define MCOMPAT_CONFIG_CHAIN4_POWER_EN_GPIO (876) 486 #define MCOMPAT_CONFIG_CHAIN5_POWER_EN_GPIO (877) 487 #define MCOMPAT_CONFIG_CHAIN6_POWER_EN_GPIO (878) 488 #define MCOMPAT_CONFIG_CHAIN7_POWER_EN_GPIO (879) 489 #define MCOMPAT_CONFIG_CHAIN0_START_EN_GPIO (854) 490 #define MCOMPAT_CONFIG_CHAIN1_START_EN_GPIO (856) 491 #define MCOMPAT_CONFIG_CHAIN2_START_EN_GPIO (858) 492 #define MCOMPAT_CONFIG_CHAIN3_START_EN_GPIO (860) 493 #define MCOMPAT_CONFIG_CHAIN4_START_EN_GPIO (862) 494 #define MCOMPAT_CONFIG_CHAIN5_START_EN_GPIO (864) 495 #define MCOMPAT_CONFIG_CHAIN6_START_EN_GPIO (866) 496 #define MCOMPAT_CONFIG_CHAIN7_START_EN_GPIO (868) 497 #define MCOMPAT_CONFIG_CHAIN0_RESET_GPIO (855) 498 #define MCOMPAT_CONFIG_CHAIN1_RESET_GPIO (857) 499 #define MCOMPAT_CONFIG_CHAIN2_RESET_GPIO (859) 500 #define MCOMPAT_CONFIG_CHAIN3_RESET_GPIO (861) 501 #define MCOMPAT_CONFIG_CHAIN4_RESET_GPIO (863) 502 #define MCOMPAT_CONFIG_CHAIN5_RESET_GPIO (865) 503 #define MCOMPAT_CONFIG_CHAIN6_RESET_GPIO (867) 504 #define MCOMPAT_CONFIG_CHAIN7_RESET_GPIO (869) 505 #define MCOMPAT_CONFIG_CHAIN0_LED_GPIO (881) 506 #define MCOMPAT_CONFIG_CHAIN1_LED_GPIO (882) 507 #define MCOMPAT_CONFIG_CHAIN2_LED_GPIO (883) 508 #define MCOMPAT_CONFIG_CHAIN3_LED_GPIO (884) 509 #define MCOMPAT_CONFIG_CHAIN4_LED_GPIO (885) 510 #define MCOMPAT_CONFIG_CHAIN5_LED_GPIO (886) 511 #define MCOMPAT_CONFIG_CHAIN6_LED_GPIO (887) 512 #define MCOMPAT_CONFIG_CHAIN7_LED_GPIO (888) 513 #define MCOMPAT_CONFIG_CHAIN0_PLUG_GPIO (896) 514 #define MCOMPAT_CONFIG_CHAIN1_PLUG_GPIO (897) 515 #define MCOMPAT_CONFIG_CHAIN2_PLUG_GPIO (898) 516 #define MCOMPAT_CONFIG_CHAIN3_PLUG_GPIO (899) 517 #define MCOMPAT_CONFIG_CHAIN4_PLUG_GPIO (900) 518 #define MCOMPAT_CONFIG_CHAIN5_PLUG_GPIO (901) 519 #define MCOMPAT_CONFIG_CHAIN6_PLUG_GPIO (902) 520 #define MCOMPAT_CONFIG_CHAIN7_PLUG_GPIO (903) 521 522 #define MCOMPAT_CONFIG_B9_GPIO (906 + 51) 523 #define MCOMPAT_CONFIG_A10_GPIO (906 + 37) 524 525 extern int g_platform; 526 extern int g_miner_type; 527 extern int g_chain_num; 528 extern int g_chip_num; 529 530 531 /* ZYNQ_GPIO */ 532 533 extern void zynq_gpio_init(int pin, int dir); 534 535 extern void zynq_gpio_exit(int pin); 536 537 extern int zynq_gpio_read(int pin); 538 539 540 /* ZYNQ_PWM */ 541 542 #define SYSFS_PWM_DEV ("/dev/pwmgen0.0") 543 544 #define IOCTL_SET_PWM_FREQ(x) _IOR(MAGIC_NUM, (2*x), char *) 545 #define IOCTL_SET_PWM_DUTY(x) _IOR(MAGIC_NUM, (2*x+1), char *) 546 547 548 extern void zynq_set_pwm(unsigned char fan_id, int frequency, int duty); 549 550 extern int zynq_gpio_g19_vid_set(int chain_id, int level); 551 552 553 /* ZYNQ_SPI */ 554 555 typedef struct ZYNQ_SPI_TAG{ 556 int fd; 557 pthread_mutex_t lock; 558 }ZYNQ_SPI_T; 559 560 void zynq_spi_init(ZYNQ_SPI_T *spi, int bus); 561 562 void zynq_spi_exit(ZYNQ_SPI_T *spi); 563 564 void zynq_spi_read(ZYNQ_SPI_T *spi, uint8_t *rxbuf, int len); 565 566 void zynq_spi_write(ZYNQ_SPI_T *spi, uint8_t *txbuf, int len); 567 568 569 void zynq_set_spi_speed(int speed); 570 571 572 573 /* ZYNQ_VID */ 574 575 #define SYSFS_VID_DEV ("/dev/vidgen0.0") 576 577 #define IOCTL_SET_VAL_0 _IOR(MAGIC_NUM, 0, char *) 578 #define IOCTL_SET_VALUE_0 _IOR(MAGIC_NUM, 0, char *) 579 #define IOCTL_SET_CHAIN_0 _IOR(MAGIC_NUM, 1, char *) 580 581 typedef struct ZYNQ_VID_TAG{ 582 int fd; 583 pthread_mutex_t lock; 584 }ZYNQ_VID_T; 585 586 extern int zynq_gpio_g9_vid_set(int level); 587 588 extern int zynq_gpio_g19_vid_set(int chain_id, int level); 589 590 591 /* HUB_HARDWARE */ 592 593 #define _MAX_MEM_RANGE (0x10000) 594 595 void hub_hardware_init(void); 596 void hub_hardware_deinit(void); 597 598 599 /* HUB_VID */ 600 601 #define I2C_DEVICE_NAME "/dev/i2c-0" 602 #define I2C_SLAVE_ADDR 0x01 603 604 bool hub_set_vid(uint8_t chan_id, int vol); 605 606 bool set_timeout_on_i2c(int time); 607 608 609 610 /* DRV_HUB */ 611 612 #define PAGE_SIZE ((size_t)getpagesize())*2 613 #define PAGE_MASK ((uint32_t) (long)~(PAGE_SIZE - 1)) 614 615 616 /* Definition for CPU ID */ 617 #define XPAR_CPU_ID 0 618 619 /* Definitions for peripheral PS7_CORTEXA9_0 */ 620 #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 621 622 623 /******************************************************************/ 624 625 /* Canonical definitions for peripheral PS7_CORTEXA9_0 */ 626 #define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 627 628 629 /******************************************************************/ 630 631 #define STDIN_BASEADDRESS 0xE0001000 632 #define STDOUT_BASEADDRESS 0xE0001000 633 634 /******************************************************************/ 635 636 637 /* Definitions for peripheral PS7_DDR_0 */ 638 #define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000 639 #define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF 640 641 642 /******************************************************************/ 643 644 /* Definitions for driver DEVCFG */ 645 #define XPAR_XDCFG_NUM_INSTANCES 1 646 647 /* Definitions for peripheral PS7_DEV_CFG_0 */ 648 #define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0 649 #define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000 650 #define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF 651 652 653 /******************************************************************/ 654 655 /* Canonical definitions for peripheral PS7_DEV_CFG_0 */ 656 #define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID 657 #define XPAR_XDCFG_0_BASEADDR 0xF8007000 658 #define XPAR_XDCFG_0_HIGHADDR 0xF80070FF 659 660 661 /******************************************************************/ 662 663 /* Definitions for driver DMAPS */ 664 #define XPAR_XDMAPS_NUM_INSTANCES 2 665 666 /* Definitions for peripheral PS7_DMA_NS */ 667 #define XPAR_PS7_DMA_NS_DEVICE_ID 0 668 #define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000 669 #define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF 670 671 672 /* Definitions for peripheral PS7_DMA_S */ 673 #define XPAR_PS7_DMA_S_DEVICE_ID 1 674 #define XPAR_PS7_DMA_S_BASEADDR 0xF8003000 675 #define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF 676 677 678 /******************************************************************/ 679 680 /* Canonical definitions for peripheral PS7_DMA_NS */ 681 #define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID 682 #define XPAR_XDMAPS_0_BASEADDR 0xF8004000 683 #define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF 684 685 /* Canonical definitions for peripheral PS7_DMA_S */ 686 #define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID 687 #define XPAR_XDMAPS_1_BASEADDR 0xF8003000 688 #define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF 689 690 691 /******************************************************************/ 692 693 /* Definitions for driver EMACPS */ 694 #define XPAR_XEMACPS_NUM_INSTANCES 1 695 696 /* Definitions for peripheral PS7_ETHERNET_0 */ 697 #define XPAR_PS7_ETHERNET_0_DEVICE_ID 0 698 #define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 699 #define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF 700 #define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000 701 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 1 702 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 703 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 1 704 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 705 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 1 706 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 707 708 709 /******************************************************************/ 710 711 /* Canonical definitions for peripheral PS7_ETHERNET_0 */ 712 #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID 713 #define XPAR_XEMACPS_0_BASEADDR 0xE000B000 714 #define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF 715 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000 716 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 1 717 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 718 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 1 719 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 720 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 1 721 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 722 723 724 /******************************************************************/ 725 726 /* Definitions for driver FANS_CTRL */ 727 #define XPAR_FANS_CTRL_NUM_INSTANCES 1 728 729 /* Definitions for peripheral FANS_CTRL_0 */ 730 #define XPAR_FANS_CTRL_0_DEVICE_ID 0 731 #define XPAR_FANS_CTRL_0_S00_AXI_BASEADDR 0x43C00000 732 #define XPAR_FANS_CTRL_0_S00_AXI_HIGHADDR 0x43C0FFFF 733 734 735 /******************************************************************/ 736 737 738 /* Definitions for peripheral PS7_AFI_0 */ 739 #define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000 740 #define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF 741 742 743 /* Definitions for peripheral PS7_AFI_1 */ 744 #define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000 745 #define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF 746 747 748 /* Definitions for peripheral PS7_AFI_2 */ 749 #define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000 750 #define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF 751 752 753 /* Definitions for peripheral PS7_AFI_3 */ 754 #define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000 755 #define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF 756 757 758 /* Definitions for peripheral PS7_DDRC_0 */ 759 #define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000 760 #define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF 761 762 763 /* Definitions for peripheral PS7_GLOBALTIMER_0 */ 764 #define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200 765 #define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF 766 767 768 /* Definitions for peripheral PS7_GPV_0 */ 769 #define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000 770 #define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF 771 772 773 /* Definitions for peripheral PS7_INTC_DIST_0 */ 774 #define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000 775 #define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF 776 777 778 /* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */ 779 #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000 780 #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF 781 782 783 /* Definitions for peripheral PS7_L2CACHEC_0 */ 784 #define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000 785 #define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF 786 787 788 /* Definitions for peripheral PS7_OCMC_0 */ 789 #define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000 790 #define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF 791 792 793 /* Definitions for peripheral PS7_PL310_0 */ 794 #define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000 795 #define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF 796 797 798 /* Definitions for peripheral PS7_PMU_0 */ 799 #define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000 800 #define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF 801 #define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000 802 #define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF 803 804 805 /* Definitions for peripheral PS7_RAM_0 */ 806 #define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000 807 #define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF 808 809 810 /* Definitions for peripheral PS7_RAM_1 */ 811 #define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000 812 #define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF 813 814 815 /* Definitions for peripheral PS7_SCUC_0 */ 816 #define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000 817 #define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC 818 819 820 /* Definitions for peripheral PS7_SLCR_0 */ 821 #define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000 822 #define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF 823 824 825 /* Definitions for peripheral PS7_SMCC_0 */ 826 #define XPAR_PS7_SMCC_0_S_AXI_BASEADDR 0xE000E000 827 #define XPAR_PS7_SMCC_0_S_AXI_HIGHADDR 0xE100EFFF 828 829 830 /******************************************************************/ 831 832 /* Definitions for driver GPIOPS */ 833 #define XPAR_XGPIOPS_NUM_INSTANCES 1 834 835 /* Definitions for peripheral PS7_GPIO_0 */ 836 #define XPAR_PS7_GPIO_0_DEVICE_ID 0 837 #define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000 838 #define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF 839 840 841 /******************************************************************/ 842 843 /* Canonical definitions for peripheral PS7_GPIO_0 */ 844 #define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID 845 #define XPAR_XGPIOPS_0_BASEADDR 0xE000A000 846 #define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF 847 848 849 /******************************************************************/ 850 851 /* Definitions for driver MCOMPAT_SPI_WRAPPER */ 852 #define XPAR_MCOMPAT_SPI_WRAPPER_NUM_INSTANCES 1 853 854 /* Definitions for peripheral MCOMPAT_SPI_WRAPPER_0 */ 855 #define XPAR_MCOMPAT_SPI_WRAPPER_0_DEVICE_ID 0 856 #define XPAR_MCOMPAT_SPI_WRAPPER_0_S00_AXI_BASEADDR 0x43C30000 857 #define XPAR_MCOMPAT_SPI_WRAPPER_0_S00_AXI_HIGHADDR 0x43C3FFFF 858 859 860 /******************************************************************/ 861 862 /* Definitions for driver NANDPS */ 863 #define XPAR_XNANDPS_NUM_INSTANCES 1 864 865 /* Definitions for peripheral PS7_NAND_0 */ 866 #define XPAR_PS7_NAND_0_DEVICE_ID 0 867 #define XPAR_PS7_NAND_0_BASEADDR 0xE1000000 868 #define XPAR_PS7_NAND_0_HIGHADDR 0xE1000FFF 869 #define XPAR_PS7_NAND_0_NAND_CLK_FREQ_HZ 100000000 870 #define XPAR_PS7_NAND_0_SMC_BASEADDR 0xE000E000 871 #define XPAR_PS7_NAND_0_NAND_WIDTH 8 872 873 874 /******************************************************************/ 875 876 /* Canonical definitions for peripheral PS7_NAND_0 */ 877 #define XPAR_XNANDPS_0_DEVICE_ID XPAR_PS7_NAND_0_DEVICE_ID 878 #define XPAR_XNANDPS_0_CPU_BASEADDR 0xE1000000 879 #define XPAR_XNANDPS_0_CPU_HIGHADDR 0xE1000FFF 880 #define XPAR_XNANDPS_0_NAND_CLK_FREQ_HZ 100000000 881 #define XPAR_XNANDPS_0_SMC_BASEADDR 0xE000E000 882 #define XPAR_XNANDPS_0_NAND_WIDTH 8 883 884 885 /******************************************************************/ 886 887 /* Definitions for driver READ_DNA */ 888 #define XPAR_READ_DNA_NUM_INSTANCES 1 889 890 /* Definitions for peripheral READ_DNA_0 */ 891 #define XPAR_READ_DNA_0_DEVICE_ID 0 892 #define XPAR_READ_DNA_0_S00_AXI_BASEADDR 0x43C20000 893 #define XPAR_READ_DNA_0_S00_AXI_HIGHADDR 0x43C2FFFF 894 895 896 /******************************************************************/ 897 898 /* Definitions for driver SCUGIC */ 899 #define XPAR_XSCUGIC_NUM_INSTANCES 1U 900 901 /* Definitions for peripheral PS7_SCUGIC_0 */ 902 #define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U 903 #define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U 904 #define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU 905 #define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U 906 907 908 /******************************************************************/ 909 910 /* Canonical definitions for peripheral PS7_SCUGIC_0 */ 911 #define XPAR_SCUGIC_0_DEVICE_ID 0U 912 #define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U 913 #define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU 914 #define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U 915 916 917 /******************************************************************/ 918 919 /* Definitions for driver SCUTIMER */ 920 #define XPAR_XSCUTIMER_NUM_INSTANCES 1 921 922 /* Definitions for peripheral PS7_SCUTIMER_0 */ 923 #define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0 924 #define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600 925 #define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F 926 927 928 /******************************************************************/ 929 930 /* Canonical definitions for peripheral PS7_SCUTIMER_0 */ 931 #define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID 932 #define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 933 #define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F 934 935 936 /******************************************************************/ 937 938 /* Definitions for driver SCUWDT */ 939 #define XPAR_XSCUWDT_NUM_INSTANCES 1 940 941 /* Definitions for peripheral PS7_SCUWDT_0 */ 942 #define XPAR_PS7_SCUWDT_0_DEVICE_ID 0 943 #define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620 944 #define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF 945 946 947 /******************************************************************/ 948 949 /* Canonical definitions for peripheral PS7_SCUWDT_0 */ 950 #define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID 951 #define XPAR_SCUWDT_0_BASEADDR 0xF8F00620 952 #define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF 953 954 955 /******************************************************************/ 956 957 /* Definitions for driver SDPS */ 958 #define XPAR_XSDPS_NUM_INSTANCES 1 959 960 /* Definitions for peripheral PS7_SD_0 */ 961 #define XPAR_PS7_SD_0_DEVICE_ID 0 962 #define XPAR_PS7_SD_0_BASEADDR 0xE0100000 963 #define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF 964 #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 100000000 965 #define XPAR_PS7_SD_0_HAS_CD 0 966 #define XPAR_PS7_SD_0_HAS_WP 0 967 #define XPAR_PS7_SD_0_BUS_WIDTH 0 968 #define XPAR_PS7_SD_0_MIO_BANK 0 969 #define XPAR_PS7_SD_0_HAS_EMIO 0 970 971 972 /******************************************************************/ 973 974 /* Canonical definitions for peripheral PS7_SD_0 */ 975 #define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID 976 #define XPAR_XSDPS_0_BASEADDR 0xE0100000 977 #define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF 978 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 100000000 979 #define XPAR_XSDPS_0_HAS_CD 0 980 #define XPAR_XSDPS_0_HAS_WP 0 981 #define XPAR_XSDPS_0_BUS_WIDTH 0 982 #define XPAR_XSDPS_0_MIO_BANK 0 983 #define XPAR_XSDPS_0_HAS_EMIO 0 984 985 986 /******************************************************************/ 987 988 /* Definitions for driver UARTPS */ 989 #define XPAR_XUARTPS_NUM_INSTANCES 1 990 991 /* Definitions for peripheral PS7_UART_1 */ 992 #define XPAR_PS7_UART_1_DEVICE_ID 0 993 #define XPAR_PS7_UART_1_BASEADDR 0xE0001000 994 #define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF 995 #define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000 996 #define XPAR_PS7_UART_1_HAS_MODEM 0 997 998 999 /******************************************************************/ 1000 1001 /* Canonical definitions for peripheral PS7_UART_1 */ 1002 #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID 1003 #define XPAR_XUARTPS_0_BASEADDR 0xE0001000 1004 #define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF 1005 #define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000 1006 #define XPAR_XUARTPS_0_HAS_MODEM 0 1007 1008 1009 /******************************************************************/ 1010 1011 /* Definitions for driver USBPS */ 1012 #define XPAR_XUSBPS_NUM_INSTANCES 1 1013 1014 /* Definitions for peripheral PS7_USB_0 */ 1015 #define XPAR_PS7_USB_0_DEVICE_ID 0 1016 #define XPAR_PS7_USB_0_BASEADDR 0xE0002000 1017 #define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF 1018 1019 1020 /******************************************************************/ 1021 1022 /* Canonical definitions for peripheral PS7_USB_0 */ 1023 #define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID 1024 #define XPAR_XUSBPS_0_BASEADDR 0xE0002000 1025 #define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF 1026 1027 1028 /******************************************************************/ 1029 1030 /* Definitions for driver VID_LED_BUZZER_CTRL */ 1031 #define XPAR_VID_LED_BUZZER_CTRL_NUM_INSTANCES 1 1032 1033 /* Definitions for peripheral VID_LED_BUZZER_CTRL_0 */ 1034 #define XPAR_VID_LED_BUZZER_CTRL_0_DEVICE_ID 0 1035 #define XPAR_VID_LED_BUZZER_CTRL_0_S00_AXI_BASEADDR 0x43C10000 1036 #define XPAR_VID_LED_BUZZER_CTRL_0_S00_AXI_HIGHADDR 0x43C1FFFF 1037 1038 1039 /******************************************************************/ 1040 1041 /* Definitions for driver XADCPS */ 1042 #define XPAR_XADCPS_NUM_INSTANCES 1 1043 1044 /* Definitions for peripheral PS7_XADC_0 */ 1045 #define XPAR_PS7_XADC_0_DEVICE_ID 0 1046 #define XPAR_PS7_XADC_0_BASEADDR 0xF8007100 1047 #define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120 1048 1049 1050 /******************************************************************/ 1051 1052 /* Canonical definitions for peripheral PS7_XADC_0 */ 1053 #define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID 1054 #define XPAR_XADCPS_0_BASEADDR 0xF8007100 1055 #define XPAR_XADCPS_0_HIGHADDR 0xF8007120 1056 1057 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG0_OFFSET 0 1058 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG1_OFFSET 4 1059 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG2_OFFSET 8 1060 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG3_OFFSET 12 1061 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG4_OFFSET 16 1062 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG5_OFFSET 20 1063 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG6_OFFSET 24 1064 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG7_OFFSET 28 1065 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG8_OFFSET 32 1066 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG9_OFFSET 36 1067 #define VID_LED_BUZZER_CTRL_S00_AXI_SLV_REG10_OFFSET 40 1068 1069 #define FANS_CTRL_S00_AXI_SLV_REG0_OFFSET 0 1070 #define FANS_CTRL_S00_AXI_SLV_REG1_OFFSET 4 1071 #define FANS_CTRL_S00_AXI_SLV_REG2_OFFSET 8 1072 #define FANS_CTRL_S00_AXI_SLV_REG3_OFFSET 12 1073 #define FANS_CTRL_S00_AXI_SLV_REG4_OFFSET 16 1074 #define FANS_CTRL_S00_AXI_SLV_REG5_OFFSET 20 1075 #define FANS_CTRL_S00_AXI_SLV_REG6_OFFSET 24 1076 #define FANS_CTRL_S00_AXI_SLV_REG7_OFFSET 28 1077 #define FANS_CTRL_S00_AXI_SLV_REG8_OFFSET 32 1078 #define FANS_CTRL_S00_AXI_SLV_REG9_OFFSET 36 1079 #define FANS_CTRL_S00_AXI_SLV_REG10_OFFSET 40 1080 #define FANS_CTRL_S00_AXI_SLV_REG11_OFFSET 44 1081 1082 #define AUTO_CMD0A_REG0_ADDR 0x0160 1083 #define AUTO_CMD0A_REG1_ADDR 0x0164 1084 #define AUTO_CMD0A_REG2_ADDR 0x0168 1085 #define AUTO_CMD0A_REG3_ADDR 0x016c 1086 #define AUTO_CMD0A_REG4_ADDR 0x0170 1087 #define AUTO_CMD0A_REG5_ADDR 0x0174 1088 #define AUTO_CMD0A_REG6_ADDR 0x0178 1089 #define AUTO_CMD0A_REG7_ADDR 0x017c 1090 1091 1092 #define LED_ON 0 1093 #define LED_OFF 1 1094 #define LED_BLING_ON 2 1095 #define LED_BLING_OFF 3 1096 1097 1098 #define SPI_RESET_REG 0x1200 1099 #define SPI_BASEADDR_GAP 0x200 1100 #define SPI_AXIBASE 0x43C30000 1101 1102 #define XST_SUCCESS 0L 1103 #define XST_FAILURE 1L 1104 #define XST_DEVICE_NOT_FOUND 2L 1105 #define XST_DEVICE_BLOCK_NOT_FOUND 3L 1106 #define XST_INVALID_VERSION 4L 1107 #define XST_DEVICE_IS_STARTED 5L 1108 #define XST_DEVICE_IS_STOPPED 6L 1109 #define XST_FIFO_ERROR 7L 1110 #define XST_CRC_ERROR 8L 1111 1112 #define MAIN_CFG_REG0_ADDR 0x00 1113 #define MAIN_CFG_REG1_ADDR 0x04 1114 #define MAIN_CFG_REG2_ADDR 0x08 1115 #define MAIN_CFG_REG3_ADDR 0x0c 1116 #define CMD_CTRL_REG0_ADDR 0x10 1117 #define CMD_CTRL_REG1_ADDR 0x14 1118 #define CMD_CTRL_REG2_ADDR 0x18 1119 #define CMD_CTRL_REG3_ADDR 0x1c 1120 #define CMD_READ_REG0_ADDR 0x20 1121 #define CMD_READ_REG1_ADDR 0x24 1122 #define CMD_READ_REG2_ADDR 0x28 1123 #define CMD_READ_REG3_ADDR 0x2c 1124 #define CMD_READ_REG4_ADDR 0x30 1125 #define CMD_READ_REG5_ADDR 0x34 1126 #define CMD_READ_REG6_ADDR 0x38 1127 #define CMD_READ_REG7_ADDR 0x3c 1128 #define CMD_READ_REG8_ADDR 0x40 1129 #define CMD_READ_REG9_ADDR 0x44 1130 #define CMD_READ_REGA_ADDR 0x48 1131 #define CMD_READ_REGB_ADDR 0x4c 1132 #define CMD_READ_REGC_ADDR 0x50 1133 #define CMD_READ_REGD_ADDR 0x54 1134 #define CMD_READ_REGE_ADDR 0x58 1135 #define CMD_READ_REGF_ADDR 0x5c 1136 #define CMD_WRITE_HEAD_ADDR 0x60 1137 #define CMD_WRITE_REG01_ADDR 0x64 1138 #define CMD_WRITE_REG02_ADDR 0x68 1139 #define CMD_WRITE_REG03_ADDR 0x6c 1140 #define CMD_WRITE_REG04_ADDR 0x70 1141 #define CMD_WRITE_REG05_ADDR 0x74 1142 #define CMD_WRITE_REG06_ADDR 0x78 1143 #define CMD_WRITE_REG07_ADDR 0x7c 1144 #define CMD_WRITE_REG08_ADDR 0x80 1145 #define CMD_WRITE_REG09_ADDR 0x84 1146 #define CMD_WRITE_REG0A_ADDR 0x88 1147 #define CMD_WRITE_REG0B_ADDR 0x8c 1148 #define CMD_WRITE_REG0C_ADDR 0x90 1149 #define CMD_WRITE_REG0D_ADDR 0x94 1150 #define CMD_WRITE_REG0E_ADDR 0x98 1151 #define CMD_WRITE_REG0F_ADDR 0x9c 1152 #define CMD_WRITE_REG10_ADDR 0xa0 1153 #define CMD_WRITE_REG11_ADDR 0xa4 1154 #define CMD_WRITE_REG12_ADDR 0xa8 1155 #define CMD_WRITE_REG13_ADDR 0xac 1156 #define CMD_WRITE_REG14_ADDR 0xb0 1157 #define CMD_WRITE_REG15_ADDR 0xb4 1158 #define CMD_WRITE_REG16_ADDR 0xb8 1159 #define CMD_WRITE_REG17_ADDR 0xbc 1160 #define CMD_WRITE_REG18_ADDR 0xc0 1161 #define CMD_WRITE_REG19_ADDR 0xc4 1162 #define CMD_WRITE_REG1A_ADDR 0xc8 1163 #define CMD_WRITE_REG1B_ADDR 0xcc 1164 #define CMD_WRITE_REG1C_ADDR 0xd0 1165 #define CMD_WRITE_REG1D_ADDR 0xd4 1166 #define CMD_WRITE_REG1E_ADDR 0xd8 1167 #define CMD_WRITE_REG1F_ADDR 0xdc 1168 #define CMD_WRITE_REG20_ADDR 0xe0 1169 #define CMD_WRITE_REG21_ADDR 0xe4 1170 #define CMD_WRITE_REG22_ADDR 0xe8 1171 #define CMD_WRITE_REG23_ADDR 0xec 1172 #define CMD_WRITE_REG24_ADDR 0xf0 1173 #define CMD_WRITE_REG25_ADDR 0xf4 1174 #define CMD_WRITE_REG26_ADDR 0xf8 1175 #define CMD_WRITE_REG27_ADDR 0xfc 1176 1177 #define SPI_BUFFER_SIZE 170 1178 #define SPI_TX_BUF_SIZE (((CMD_WRITE_REG27_ADDR-CMD_WRITE_HEAD_ADDR) / 4) + 1) * 2 1179 #define SPI_RX_BUF_SIZE (((CMD_READ_REGF_ADDR-CMD_READ_REG0_ADDR) / 4) + 1) * 2 1180 1181 #define CHK_HY 0x00000080 1182 #define CHK_H1 0x00000040 1183 #define CHK_LN 0x00000020 1184 #define CHK_CMD 0x00000004 1185 #define CHK_ID 0x00000008 1186 1187 1188 #define SPI_BYPASS_EN 0x00001000 1189 #define SPI_BYPASS_END 0x00002000 1190 1191 1192 #define REORDER16(arg) ((uint16_t)(arg<<8 | arg>>8)) 1193 1194 1195 #define SYSTEM_LINUX 1196 1197 1198 void hub_init(void); 1199 1200 void hub_deinit(void); 1201 1202 int Xil_SPI_In32(uint32_t phyaddr); 1203 1204 void Xil_SPI_Out32(uint32_t phyaddr, uint32_t val); 1205 1206 1207 extern bool rece_queue_has_nonce(uint8_t spi_id, uint32_t timeout_us); 1208 1209 extern void read_nonce_buffer(uint8_t spi_id, uint8_t* buf8, uint32_t len_cfg); 1210 1211 extern int send_job_queue(uint8_t spi_id, uint8_t* tx_buf8, uint8_t* rx_buf8, uint32_t len_cfg, uint32_t last_job); 1212 1213 extern int do_spi_cmd(uint8_t spi_id, uint8_t* tx_buf8, uint8_t* rx_buf8, uint32_t len_cfg); 1214 1215 int hub_spi_init(uint8_t spi_id, uint8_t chip_num); 1216 1217 void hub_spi_reset(uint8_t spi_id); 1218 1219 void hub_spi_clean_chain(uint32_t spi_id); 1220 1221 void hub_set_spi_speed(uint8_t spi_id, int select); 1222 1223 void hub_set_power_en(uint8_t chain_id, int value); 1224 1225 void hub_set_start_en(uint8_t chain_id, int value); 1226 1227 bool hub_set_reset(uint8_t chain_id, int value); 1228 1229 void hub_set_led(uint8_t chain_id, int mode); 1230 1231 bool hub_set_vid(uint8_t chain_id, int vid); 1232 void hub_set_vid_vid(uint8_t chain_id, int vid); 1233 void hub_set_vid_uart_select(uint8_t spi_id); 1234 1235 void hub_set_pwm(uint8_t fan_id, int frequency, int duty); 1236 1237 int hub_get_plug(uint8_t chain_id); 1238 1239 void hub_set_green_led(int mode); 1240 1241 void hub_set_red_led(int mode); 1242 1243 int hub_get_button(void); 1244 1245 int enable_auto_nonce(uint8_t chain_id, uint16_t cmd08_cmd, uint32_t len_cfg); 1246 1247 int disable_auto_nonce(uint8_t chain_id); 1248 1249 void enable_auto_cmd0a(uint8_t spi_id, uint32_t threshold, uint32_t msb, uint32_t lsb, uint32_t large_en, uint32_t mode );//mode : 1 only cmd0a;0 cmd08 follows cmd0a 1250 1251 void disable_auto_cmd0a(uint8_t spi_id, uint32_t threshold, uint32_t msb, uint32_t lsb, uint32_t large_en, uint32_t mode );//mode : 1 only cmd0a;0 cmd08 follows cmd0a 1252 1253 void init_hub_gpio(void); 1254 1255 1256 1257 //#define XPAR_MCOMPAT_PERIPHERAL_0_S00_AXI_BASEADDR 0x43C00000 1258 1259 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG0_OFFSET 0 1260 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG1_OFFSET 4 1261 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG2_OFFSET 8 1262 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG3_OFFSET 12 1263 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG4_OFFSET 16 1264 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG5_OFFSET 20 1265 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG6_OFFSET 24 1266 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG7_OFFSET 28 1267 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG8_OFFSET 32 1268 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG9_OFFSET 36 1269 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG10_OFFSET 40 1270 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG11_OFFSET 44 1271 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG12_OFFSET 48 1272 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG13_OFFSET 52 1273 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG14_OFFSET 56 1274 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG15_OFFSET 60 1275 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG16_OFFSET 64 1276 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG17_OFFSET 68 1277 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG18_OFFSET 72 1278 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG19_OFFSET 76 1279 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG20_OFFSET 80 1280 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG21_OFFSET 84 1281 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG22_OFFSET 88 1282 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG23_OFFSET 92 1283 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG24_OFFSET 96 1284 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG25_OFFSET 100 1285 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG26_OFFSET 104 1286 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG27_OFFSET 108 1287 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG28_OFFSET 112 1288 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG29_OFFSET 116 1289 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG30_OFFSET 120 1290 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG31_OFFSET 124 1291 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG32_OFFSET 128 1292 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG33_OFFSET 132 1293 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG34_OFFSET 136 1294 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG35_OFFSET 140 1295 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG36_OFFSET 144 1296 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG37_OFFSET 148 1297 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG38_OFFSET 152 1298 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG39_OFFSET 156 1299 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG40_OFFSET 160 1300 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG41_OFFSET 164 1301 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG42_OFFSET 168 1302 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG43_OFFSET 172 1303 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG44_OFFSET 176 1304 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG45_OFFSET 180 1305 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG46_OFFSET 184 1306 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG47_OFFSET 188 1307 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG48_OFFSET 192 1308 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG49_OFFSET 196 1309 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG50_OFFSET 200 1310 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG51_OFFSET 204 1311 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG52_OFFSET 208 1312 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG53_OFFSET 212 1313 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG54_OFFSET 216 1314 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG55_OFFSET 220 1315 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG56_OFFSET 224 1316 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG57_OFFSET 228 1317 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG58_OFFSET 232 1318 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG59_OFFSET 236 1319 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG60_OFFSET 240 1320 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG61_OFFSET 244 1321 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG62_OFFSET 248 1322 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG63_OFFSET 252 1323 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG64_OFFSET 256 1324 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG65_OFFSET 260 1325 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG66_OFFSET 264 1326 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG67_OFFSET 268 1327 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG68_OFFSET 272 1328 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG69_OFFSET 276 1329 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG70_OFFSET 280 1330 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG71_OFFSET 284 1331 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG72_OFFSET 288 1332 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG73_OFFSET 292 1333 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG74_OFFSET 296 1334 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG75_OFFSET 300 1335 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG76_OFFSET 304 1336 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG77_OFFSET 308 1337 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG78_OFFSET 312 1338 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG79_OFFSET 316 1339 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG80_OFFSET 320 1340 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG81_OFFSET 324 1341 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG82_OFFSET 328 1342 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG83_OFFSET 332 1343 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG84_OFFSET 336 1344 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG85_OFFSET 340 1345 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG86_OFFSET 344 1346 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG87_OFFSET 348 1347 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG88_OFFSET 352 1348 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG89_OFFSET 356 1349 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG90_OFFSET 360 1350 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG91_OFFSET 364 1351 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG92_OFFSET 368 1352 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG93_OFFSET 372 1353 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG94_OFFSET 376 1354 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG95_OFFSET 380 1355 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG96_OFFSET 384 1356 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG97_OFFSET 388 1357 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG98_OFFSET 392 1358 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG99_OFFSET 396 1359 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG100_OFFSET 400 1360 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG101_OFFSET 404 1361 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG102_OFFSET 408 1362 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG103_OFFSET 412 1363 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG104_OFFSET 416 1364 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG105_OFFSET 420 1365 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG106_OFFSET 424 1366 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG107_OFFSET 428 1367 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG108_OFFSET 432 1368 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG109_OFFSET 436 1369 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG110_OFFSET 440 1370 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG111_OFFSET 444 1371 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG112_OFFSET 448 1372 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG113_OFFSET 452 1373 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG114_OFFSET 456 1374 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG115_OFFSET 460 1375 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG116_OFFSET 464 1376 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG117_OFFSET 468 1377 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG118_OFFSET 472 1378 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG119_OFFSET 476 1379 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG120_OFFSET 480 1380 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG121_OFFSET 484 1381 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG122_OFFSET 488 1382 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG123_OFFSET 492 1383 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG124_OFFSET 496 1384 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG125_OFFSET 500 1385 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG126_OFFSET 504 1386 #define MCOMPAT_PERIPHERAL_S00_AXI_SLV_REG127_OFFSET 508 1387 1388 /* DRV_OPI */ 1389 1390 #define AX_CMD_SYNC_HEAD 0xA55A 1391 #define CUSTOM_SYNC_HEAD 0x6996 1392 1393 #define OPI_SPI_TIMEOUT 100 1394 1395 #define OPI_STATUS_SUC 0 1396 #define OPI_STATUS_EOR 1 1397 1398 #define OPI_SET_POWER_EN (0x11) 1399 #define OPI_SET_STARR_EN (0x12) 1400 #define OPI_SET_RESET (0x13) 1401 #define OPI_SET_LED (0x14) 1402 #define OPI_GET_PLUG (0x15) 1403 #define OPI_SET_VID (0x16) 1404 #define OPI_SET_PWM (0x17) 1405 #define OPI_SET_SPI_SPEED (0x18) 1406 #define OPI_POWER_ON (0x21) 1407 #define OPI_POWER_DOWN (0x22) 1408 #define OPI_POWER_RESET (0x23) 1409 1410 1411 1412 #define OPI_HI_BYTE(a) ((uint8_t)(((a) >> 8) & 0xff)) 1413 #define OPI_LO_BYTE(a) ((uint8_t)(((a) >> 0) & 0xff)) 1414 1415 #define OPI_MAKE_WORD(a, b) (uint16_t)((((a) & 0xff) << 8) | (( (a) & 0xff) << 0)) 1416 1417 1418 bool opi_spi_read_write(uint8_t chain_id, uint8_t *txbuf, uint8_t *rxbuf, int len); 1419 1420 bool opi_send_command(uint8_t chain_id, uint8_t cmd, uint8_t chip_id, uint8_t *buff, int len); 1421 1422 bool opi_poll_result(uint8_t chain_id, uint8_t cmd, uint8_t chip_id, uint8_t *buff, int len); 1423 1424 1425 void opi_set_power_en(unsigned char chain_id, int val); 1426 1427 void opi_set_start_en(unsigned char chain_id, int val); 1428 1429 bool opi_set_reset(unsigned char chain_id, int val); 1430 1431 void opi_set_led(unsigned char chain_id, int val); 1432 1433 int opi_get_plug(unsigned char chain_id); 1434 1435 bool opi_set_vid(unsigned char chain_id, int vid); 1436 1437 void opi_set_pwm(unsigned char fan_id, int frequency, int duty); 1438 1439 1440 bool opi_chain_power_on(unsigned char chain_id); 1441 1442 bool opi_chain_power_down(unsigned char chain_id); 1443 1444 bool opi_chain_hw_reset(unsigned char chain_id); 1445 1446 bool opi_chain_power_on_all(void); 1447 1448 bool opi_chain_power_down_all(void); 1449 1450 1451 void opi_set_spi_speed(unsigned char chain_id, int index); 1452 1453 1454 /* DRV_SPI */ 1455 1456 void spi_send_data(ZYNQ_SPI_T *spi, unsigned char *buf, int len); 1457 void spi_recv_data(ZYNQ_SPI_T *spi, unsigned char *buf, int len); 1458 1459 void spi_send_data_in_word(ZYNQ_SPI_T *spi, unsigned char *buf, int len); 1460 void spi_recv_data_in_word(ZYNQ_SPI_T *spi, unsigned char *buf, int len); 1461 1462 bool spi_send_command(ZYNQ_SPI_T *spi, unsigned char cmd, unsigned char chip_id, unsigned char *buff, int len); 1463 bool spi_poll_result(ZYNQ_SPI_T *spi, unsigned char cmd, unsigned char chip_id, unsigned char *buff, int len); 1464 1465 1466 void init_spi_gpio(int chain_num); 1467 void exit_spi_gpio(int chain_num); 1468 1469 1470 void spi_set_power_en(unsigned char chain_id, int val); 1471 void spi_set_start_en(unsigned char chain_id, int val); 1472 bool spi_set_reset(unsigned char chain_id, int val); 1473 void spi_set_led(unsigned char chain_id, int val); 1474 bool spi_set_vid(unsigned char chain_id, int vid); 1475 int spi_get_plug(unsigned char chain_id); 1476 1477 void spi_set_spi_speed(unsigned char chain_id, int index); 1478 1479 1480 /* DRV_ZYNQ */ 1481 1482 bool zynq_chain_power_on(unsigned char chain_id); 1483 1484 bool zynq_chain_power_down(unsigned char chain_id); 1485 1486 bool zynq_chain_hw_reset(unsigned char chain_id); 1487 1488 bool zynq_chain_power_on_all(void); 1489 1490 bool zynq_chain_power_down_all(void); 1491 1492 1493 /* HUB_CMD */ 1494 1495 bool init_hub_cmd(int chain_num, int chip_num); 1496 1497 bool exit_hub_cmd(int chain_num); 1498 1499 bool hub_cmd_reset(unsigned char chain_id, unsigned char chip_id, unsigned char *in, unsigned char *out); 1500 1501 int hub_cmd_bist_start(unsigned char chain_id, unsigned char chip_id); 1502 1503 bool hub_cmd_bist_collect(unsigned char chain_id, unsigned char chip_id); 1504 1505 bool hub_cmd_bist_fix(unsigned char chain_id, unsigned char chip_id); 1506 1507 bool hub_cmd_write_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len); 1508 1509 bool hub_cmd_read_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len); 1510 1511 bool hub_cmd_read_write_reg0d(unsigned char chain_id, unsigned char chip_id, unsigned char *in, int len, unsigned char *out); 1512 1513 bool hub_cmd_read_result(unsigned char chain_id, unsigned char chip_id, unsigned char *res, int len); 1514 1515 bool hub_cmd_write_job(unsigned char chain_id, unsigned char chip_id, unsigned char *job, int len); 1516 1517 bool hub_cmd_auto_nonce(unsigned char chain_id, int mode, int len); 1518 1519 bool hub_cmd_read_nonce(unsigned char chain_id, unsigned char *res, int len); 1520 1521 //bool hub_cmd_get_temp(mcompat_fan_temp_s *fan_temp_ctrl); 1522 1523 bool hub_get_chain_temp(unsigned char chain_id, short tmp_hi, short tmp_lo, short tmp_avg); 1524 1525 1526 /* OPI_CMD */ 1527 1528 bool init_opi_cmd(void); 1529 1530 bool exit_opi_cmd(void); 1531 1532 bool opi_cmd_reset(unsigned char chain_id, unsigned char chip_id, unsigned char *in, unsigned char *out); 1533 1534 int opi_cmd_bist_start(unsigned char chain_id, unsigned char chip_id); 1535 1536 bool opi_cmd_bist_collect(unsigned char chain_id, unsigned char chip_id); 1537 1538 bool opi_cmd_bist_fix(unsigned char chain_id, unsigned char chip_id); 1539 1540 bool opi_cmd_write_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len); 1541 1542 bool opi_cmd_read_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len); 1543 1544 bool opi_cmd_read_write_reg0d(unsigned char chain_id, unsigned char chip_id, unsigned char *in, int len, unsigned char *out); 1545 1546 bool opi_cmd_read_result(unsigned char chain_id, unsigned char chip_id, unsigned char *res, int len); 1547 1548 bool opi_cmd_write_job(unsigned char chain_id, unsigned char chip_id, unsigned char *job, int len); 1549 1550 1551 /* SPI_CMD */ 1552 1553 bool init_spi_cmd(int chain_num); 1554 1555 bool exit_spi_cmd(int chain_num); 1556 1557 bool spi_cmd_reset(unsigned char chain_id, unsigned char chip_id, unsigned char *in, unsigned char *out); 1558 1559 int spi_cmd_bist_start(unsigned char chain_id, unsigned char chip_id); 1560 1561 bool spi_cmd_bist_collect(unsigned char chain_id, unsigned char chip_id); 1562 1563 bool spi_cmd_bist_fix(unsigned char chain_id, unsigned char chip_id); 1564 1565 bool spi_cmd_write_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len); 1566 1567 bool spi_cmd_read_register(unsigned char chain_id, unsigned char chip_id, unsigned char *reg, int len); 1568 1569 bool spi_cmd_read_write_reg0d(unsigned char chain_id, unsigned char chip_id, unsigned char *in, int len, unsigned char *out); 1570 1571 bool spi_cmd_read_result(unsigned char chain_id, unsigned char chip_id, unsigned char *res, int len); 1572 1573 bool spi_cmd_write_job(unsigned char chain_id, unsigned char chip_id, unsigned char *job, int len); 1574 1575 1576 /* UTIL */ 1577 1578 unsigned short CRC16_2(unsigned char* pchMsg, unsigned short wDataLen); 1579 1580 1581 /* OPI_H3 */ 1582 1583 #define SW_PORTC_IO_BASE 0x01c20800 1584 #define GPIO_BANK(pin) ((pin) >> 5) 1585 #define GPIO_CFG_INDEX(pin) (((pin) & 0x1F) >> 3) 1586 #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1F) & 0x7) << 2) 1587 #define GPIO_NUM(pin) ((pin) & 0x1F) 1588 #define GPIO_PUL_INDEX(pin) (((pin) & 0x1F )>> 4) 1589 #define GPIO_PUL_OFFSET(pin) (((pin) & 0x0F) << 1) 1590 1591 struct sunxi_gpio { 1592 unsigned int cfg[4]; 1593 unsigned int dat; 1594 unsigned int drv[2]; 1595 unsigned int pull[2]; 1596 }; 1597 1598 struct sunxi_gpio_int { 1599 unsigned int cfg[3]; 1600 unsigned int ctl; 1601 unsigned int sta; 1602 unsigned int deb; 1603 }; 1604 1605 struct sunxi_gpio_reg { 1606 struct sunxi_gpio gpio_bank[9]; 1607 unsigned char res[0xbc]; 1608 struct sunxi_gpio_int gpio_int; 1609 }; 1610 1611 typedef struct 1612 { 1613 uint8_t mode; 1614 uint8_t bits; 1615 uint32_t speed; 1616 uint16_t delay; 1617 } spi_config_t; 1618 1619 #define PA12 12 1620 #define PA11 11 1621 #define PA6 6 1622 #define PA0 0 1623 #define PA1 1 1624 #define PA3 3 1625 #define PC0 64 1626 #define PC1 65 1627 #define PC2 66 1628 #define PA19 19 1629 #define PA7 7 1630 #define PA8 8 1631 #define PA9 9 1632 #define PA10 10 1633 #define PA20 20 1634 1635 #define PA13 13 1636 #define PA14 14 1637 #define PD14 110 1638 #define PC4 68 1639 #define PC7 71 1640 #define PA2 2 1641 #define PC3 67 1642 #define PA21 21 1643 #define PA18 18 1644 #define PG8 200 1645 #define PG9 201 1646 #define PG6 198 1647 #define PG7 199 1648 1649 1650 #define PA15 15 1651 #define PL10 362 1652 #define PL3 355 1653 1654 #define _3 12 1655 #define _5 11 1656 #define _7 6 1657 #define _8 13 1658 #define _10 14 1659 #define _11 0 1660 #define _12 110 1661 #define _13 1 1662 #define _15 3 1663 #define _16 68 1664 #define _18 71 1665 #define _19 64 1666 #define _21 65 1667 #define _22 2 1668 #define _23 66 1669 #define _24 67 1670 #define _26 21 1671 #define _27 19 1672 #define _28 18 1673 #define _29 7 1674 #define _31 8 1675 #define _32 200 1676 #define _33 9 1677 #define _35 10 1678 #define _36 201 1679 #define _37 20 1680 #define _38 198 1681 #define _40 199 1682 1683 #define STATUS_LED 15 1684 #define POWER_LED 362 1685 #define POWER_KEY 355 1686 1687 #define HIGH 1 1688 #define LOW 0 1689 1690 #define INPUT 0 1691 #define OUTPUT 1 1692 1693 #define PUTDOWM 2 1694 #define PUTUP 1 1695 1696 1697 int gpio_init(void); 1698 int gpio_setcfg(unsigned int pin, unsigned int p1); 1699 int gpio_getcfg(unsigned int pin); 1700 int gpio_output(unsigned int pin, unsigned int p1); 1701 int gpio_pullup(unsigned int pin, unsigned int p1); 1702 int gpio_input(unsigned int pin); 1703 int i2c_open(char *dev, uint8_t address); 1704 int i2c_close(int fd); 1705 int i2c_send(int fd, uint8_t *buf, uint8_t num_bytes); 1706 int i2c_read(int fd, uint8_t *buf, uint8_t num_bytes); 1707 int spi_open(char *dev, spi_config_t config); 1708 int spi_close(int fd); 1709 int spi_xfer(int fd, uint8_t *tx_buf, uint8_t tx_len, uint8_t *rx_buf, uint8_t rx_len); 1710 int spi_read(int fd, uint8_t *rx_buf, uint8_t rx_len); 1711 int spi_write(int fd, uint8_t *tx_buffer, uint8_t tx_len); 1712 void delay(unsigned int howLong); 1713 1714 1715 /* OPI_SPI */ 1716 1717 #define PIN_SPI_A0 _11 1718 #define PIN_SPI_A1 _12 1719 #define PIN_SPI_A2 _13 1720 1721 #define PIN_SPI_E1 _22 1722 1723 1724 #define SPI_DEVICE_TEMPLATE "/dev/spidev%d.%d" 1725 #define DEFAULT_SPI_BUS 1 1726 #define DEFAULT_SPI_CS_LINE 0 1727 #define DEFAULT_SPI_MODE SPI_MODE_1 1728 #define DEFAULT_SPI_BITS_PER_WORD 16 1729 #define DEFAULT_SPI_SPEED 1500000 1730 #define DEFAULT_SPI_DELAY_USECS 0 1731 1732 1733 struct spi_config { 1734 int bus; 1735 int cs_line; 1736 uint8_t mode; 1737 uint32_t speed; 1738 uint8_t bits; 1739 uint16_t delay; 1740 }; 1741 1742 struct spi_ctx { 1743 int fd; 1744 int power_en; 1745 int start_en; 1746 int reset; 1747 int led; 1748 int plug; 1749 int id; 1750 struct spi_config config; 1751 }; 1752 1753 1754 void opi_spi_init(void); 1755 1756 void opi_spi_exit(void); 1757 1758 //void opi_set_spi_speed(uint32_t speed); 1759 1760 bool opi_spi_transfer(uint8_t id, uint16_t *txbuf, uint16_t *rxbuf, int len); 1761 1762 #endif /* _DM_COMPAT_H_ */