architecture.html
1 <!doctype html> 2 <html lang="en"> 3 <head> 4 <meta charset="utf-8"> 5 <meta name="viewport" content="width=device-width, initial-scale=1"> 6 <title>AERIS-10 Docs | Architecture</title> 7 <link rel="stylesheet" href="assets/style.css"> 8 </head> 9 <body> 10 <header class="topbar"> 11 <div class="container nav"> 12 <a class="brand" href="index.html">AERIS-10 Docs</a> 13 <nav> 14 <a href="architecture.html">Architecture</a> 15 <a href="implementation-log.html">Implementation Log</a> 16 <a href="bring-up.html">Bring-Up</a> 17 <a href="reports.html">Reports</a> 18 <a href="release-notes.html">Release Notes</a> 19 </nav> 20 </div> 21 </header> 22 23 <main class="container page"> 24 <section class="hero"> 25 <p class="eyebrow">System View</p> 26 <h1>Architecture and Data Path</h1> 27 <p>Hardware and firmware structure for the current XC7A200T implementation and bring-up targets.</p> 28 </section> 29 30 <section class="grid-2"> 31 <article class="card"> 32 <h2>Top-level processing flow</h2> 33 <div class="table-wrap"> 34 <table> 35 <thead> 36 <tr> 37 <th>Stage</th> 38 <th>Module Focus</th> 39 <th>Notes</th> 40 </tr> 41 </thead> 42 <tbody> 43 <tr> 44 <td>ADC capture</td> 45 <td>AD9484 interface + CDC edge</td> 46 <td>400 MHz sampling domain, synchronized into processing pipeline.</td> 47 </tr> 48 <tr> 49 <td>DDC</td> 50 <td>NCO + CIC + FIR</td> 51 <td>I/Q conversion and decimation for baseband-ready stream.</td> 52 </tr> 53 <tr> 54 <td>Matched filter</td> 55 <td>FFT-based chain</td> 56 <td>Synthesis branch is golden for hardware-equivalent co-sim.</td> 57 </tr> 58 <tr> 59 <td>Range/Doppler</td> 60 <td>Range bin decimator + Doppler FFT</td> 61 <td>32 chirps/frame, 64 range bins, deterministic frame outputs.</td> 62 </tr> 63 <tr> 64 <td>Host path</td> 65 <td>FT601 interface</td> 66 <td>USB streaming with framing and soak validation in bring-up.</td> 67 </tr> 68 </tbody> 69 </table> 70 </div> 71 </article> 72 73 <article class="card"> 74 <h2>Current target split strategy</h2> 75 <ul> 76 <li>Production target remains <code>xc7a200t-2fbg484i</code> with full board constraints.</li> 77 <li>TE0712/TE0701 and TE0713/TE0701 use dedicated top wrappers and dedicated XDC files.</li> 78 <li>Board-specific pinouts are isolated from core DSP modules to avoid accidental cross-target regression.</li> 79 <li>Bring-up sequence starts from minimal heartbeat top, then steps into full signal chain validation.</li> 80 </ul> 81 </article> 82 </section> 83 84 <section class="card" style="margin-top:0.8rem;"> 85 <h2>Reference block diagram</h2> 86 <img class="diagram" src="assets/img/RADAR_V6.jpg" alt="AERIS-10 system architecture diagram"> 87 <p class="muted">Diagram snapshot from AERIS-10 project architecture.</p> 88 </section> 89 </main> 90 91 <footer class="footer"> 92 <div class="container"><p>Architecture is updated as bring-up and integration milestones complete.</p></div> 93 </footer> 94 </body> 95 </html>