bring-up.html
1 <!doctype html> 2 <html lang="en"> 3 <head> 4 <meta charset="utf-8"> 5 <meta name="viewport" content="width=device-width, initial-scale=1"> 6 <title>AERIS-10 Docs | Bring-Up</title> 7 <link rel="stylesheet" href="assets/style.css"> 8 </head> 9 <body> 10 <header class="topbar"> 11 <div class="container nav"> 12 <a class="brand" href="index.html">AERIS-10 Docs</a> 13 <nav> 14 <a href="architecture.html">Architecture</a> 15 <a href="implementation-log.html">Implementation Log</a> 16 <a href="bring-up.html">Bring-Up</a> 17 <a href="reports.html">Reports</a> 18 <a href="release-notes.html">Release Notes</a> 19 </nav> 20 </div> 21 </header> 22 23 <main class="container page"> 24 <section class="hero"> 25 <p class="eyebrow">Execution Checklist</p> 26 <h1>Hardware Bring-Up Plan</h1> 27 <p>Pre-arrival completeness gates, board-day smoke tests, and fault-localization rules for the first FPGA module and carrier-board sessions.</p> 28 <div class="cta-row"> 29 <a class="button" href="board-day-worksheet.html">Open Board-Day Worksheet</a> 30 <a class="button ghost" href="reports.html">Open Artifact Inventory</a> 31 </div> 32 </section> 33 34 <section class="card" style="margin-top:0.8rem;"> 35 <h2>Pre-arrival completeness gates</h2> 36 <div class="table-wrap"> 37 <table> 38 <thead> 39 <tr> 40 <th>Gate</th> 41 <th>Objective</th> 42 <th>Pass Criteria</th> 43 <th>Evidence</th> 44 </tr> 45 </thead> 46 <tbody> 47 <tr><td>1</td><td>Freeze known-good firmware and bitstream baselines</td><td>Tracked commit, named artifact set, and repeatable programming flow are available</td><td>Git commit, bitstream path, reports, programming TCL; heartbeat image at <code>docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit</code>; FT601 integration dev image at <code>docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit</code> (WNS +0.059 ns, timing clean)</td></tr> 48 <tr><td>2</td><td>Preserve clean implementation constraints</td><td>Positive WNS/WHS/WPWS, XDCB-5 cleared, only documented methodology residue remains</td><td>Timing summary and methodology report</td></tr> 49 <tr><td>3</td><td>Keep regressions green before board arrival</td><td>MCU host tests and FPGA regression/integration suites pass on the tracked tree</td><td>15/15 MCU and 18/18 FPGA logs</td></tr> 50 <tr><td>4</td><td>Make first-power-on behavior observable</td><td>Clock, LO, beamformer, PA, and USB status can be identified from logs or status outputs</td><td>DIAG coverage, status fields, ILA/debug plan</td></tr> 51 <tr><td>5</td><td>Prepare board-arrival execution checklist</td><td>Power order, abort criteria, and host-side capture steps are written and reviewed</td><td>This page plus reports and scripts references</td></tr> 52 <tr><td>6</td><td>Document unresolved pre-hardware risks</td><td>Open issues are explicitly listed so Day-0 findings are interpreted correctly</td><td>Known-open-risks section below</td></tr> 53 </tbody> 54 </table> 55 </div> 56 </section> 57 58 <section class="grid-2" style="margin-top:0.8rem;"> 59 <article class="card"> 60 <h2>Board-arrival smoke test</h2> 61 <ol> 62 <li>Inspect carrier defaults, regulator enables, jumpers, and any board-level clock source selections before power is applied.</li> 63 <li>Power the carrier and module in the safest configuration with RF transmit paths disabled and document current draw immediately.</li> 64 <li>Run the FPGA programming flow, verify JTAG enumeration, and confirm DONE and INIT_COMPLETE from the hardware manager script.</li> 65 <li>Check deterministic reset release and heartbeat/status outputs before enabling any analog or RF-dependent function.</li> 66 <li>Bring up MCU firmware logging, confirm AD9523 status pins, LO initialization results, and beamformer communication readback.</li> 67 <li>Use the debug-capable FPGA image and probes to confirm raw ADC, DDC, matched-filter, and USB-path activity in that order.</li> 68 <li>Exercise the FT601 path with known framing expectations before any long-duration streaming test.</li> 69 <li>Only after all previous steps pass, begin PA bias, calibration, and higher-risk RF activation.</li> 70 </ol> 71 </article> 72 <article class="card"> 73 <h2>Abort criteria</h2> 74 <ul> 75 <li>Stop immediately on unexpected rail current, regulator instability, or thermal rise beyond the planned idle envelope.</li> 76 <li>Do not continue past LO bring-up if the lock GPIOs or lock-status reads disagree repeatedly.</li> 77 <li>Stop RF activation if beamformer scratchpad/readback checks fail on any device.</li> 78 <li>Do not continue USB stress testing if framing, backpressure, or bus-direction behavior is inconsistent.</li> 79 <li>Revert to the heartbeat or debug image if reset sequencing or clock presence is ambiguous.</li> 80 <li>Keep the production-target constraints and pinout source untouched while bring-up-specific targets are being adjusted.</li> 81 </ul> 82 </article> 83 </section> 84 85 <section class="card" style="margin-top:0.8rem;"> 86 <h2>First-power-on observability targets</h2> 87 <div class="table-wrap"> 88 <table> 89 <thead> 90 <tr> 91 <th>Subsystem</th> 92 <th>What must be visible</th> 93 <th>Expected evidence</th> 94 </tr> 95 </thead> 96 <tbody> 97 <tr><td>FPGA configuration</td><td>JTAG enumeration, DONE, INIT_COMPLETE, optional ILA probe presence</td><td>program_fpga.tcl summary and hardware-manager status</td></tr> 98 <tr><td>Clocking</td><td>AD9523 status pins and deterministic downstream reset release</td><td>DIAG clock messages and status GPIO snapshots</td></tr> 99 <tr><td>LO chain</td><td>ADF4382A init status, timed-sync path status, TX/RX lock state</td><td>USART3 DIAG log plus lock GPIO behavior</td></tr> 100 <tr><td>Beamformer control</td><td>Per-device communication sanity and basic temperature readback</td><td>ADAR1000 scratchpad/readback and temperature prints</td></tr> 101 <tr><td>PA biasing</td><td>DAC/ADC bring-up progression and IDQ calibration convergence bounds</td><td>Per-channel PA DIAG output with stop conditions</td></tr> 102 <tr><td>FPGA data path</td><td>ADC, DDC, matched-filter, and USB-path activity in sequence</td><td>ILA captures and system status outputs</td></tr> 103 <tr><td>USB/FT601 link</td><td>Stable framing, no obvious underrun/backpressure surprises, host decode sanity</td><td>Host capture script output and stable packet boundaries</td></tr> 104 </tbody> 105 </table> 106 </div> 107 </section> 108 109 <section class="grid-2" style="margin-top:0.8rem;"> 110 <article class="card"> 111 <h2>Required artifacts before hardware arrives</h2> 112 <ul> 113 <li>Named firmware baseline commit and build instructions for the MCU image.</li> 114 <li>Named FPGA baseline bitstream and matching `.ltx` probes file for debug sessions; current low-risk heartbeat artifact is <code>docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit</code>.</li> 115 <li>Current production-target XDC, timing summary, and methodology report.</li> 116 <li>Programming and debug TCL scripts for baseline and debug images.</li> 117 <li>Regression evidence for the tracked branch: MCU host suite and FPGA regression/integration suite.</li> 118 <li>Day-0 measurement sheet covering supply currents, temperatures, and observed status outputs.</li> 119 </ul> 120 <p><a class="button ghost" href="reports.html">View concrete artifact inventory</a></p> 121 </article> 122 <article class="card"> 123 <h2>Host-side tools and workflows</h2> 124 <ul> 125 <li>JTAG programming workflow using the checked-in Vivado TCL scripts and the TE0713 heartbeat baseline built on 2026-03-21.</li> 126 <li>Serial capture on USART3 with timestamps preserved for bring-up logs.</li> 127 <li>FT601 or host-side USB capture/decoder workflow to validate framing and payload stability.</li> 128 <li>ILA capture workflow for raw ADC, DDC, matched-filter, and USB-domain checkpoints.</li> 129 <li>Repeatable checklist for baseline image, debug image, and rollback image selection.</li> 130 </ul> 131 <p><a class="button ghost" href="board-day-worksheet.html">Open printable worksheet</a></p> 132 </article> 133 </section> 134 135 <section class="card" style="margin-top:0.8rem;"> 136 <h2>Known open risks before board arrival</h2> 137 <div class="table-wrap"> 138 <table> 139 <thead> 140 <tr> 141 <th>Risk</th> 142 <th>Current state</th> 143 <th>Day-0 handling</th> 144 </tr> 145 </thead> 146 <tbody> 147 <tr><td>Residual FT601 methodology warning</td><td>Production-target XDC cleanup is validated, but one `ft601_txe` methodology residue remains documented.</td><td>Treat as a known observation item and verify real FT601 status behavior before attempting deeper constraint churn.</td></tr> 148 <tr><td>RF control-path realism</td><td>Firmware sequencing and diagnostics improved, but LO sync, phase behavior, and beamformer control still require physical validation.</td><td>Use readback-first bring-up and do not assume analog behavior from simulation or logs alone.</td></tr> 149 <tr><td>Prototype-grade top-level functional assumptions</td><td>The active FPGA baseline is regression-clean, but some radar-function behavior still needs real-board confirmation under actual I/O conditions.</td><td>Validate each data-path stage incrementally with ILA and host captures before full streaming claims.</td></tr> 150 <tr><td>PA calibration boundaries</td><td>IDQ calibration logic is much safer than before, but real-device convergence and margin limits are not yet board-proven.</td><td>Use conservative limits, observe every channel, and stop on abnormal current or non-convergent channels.</td></tr> 151 <tr><td>Board-specific integration unknowns</td><td>Carrier/module interaction, rails, clocks, and connector assumptions remain partially unproven until first assembly.</td><td>Begin with the tracked TE0713/TE0701 heartbeat image and configuration checks before enabling higher-energy subsystems.</td></tr> 152 </tbody> 153 </table> 154 </div> 155 </section> 156 </main> 157 158 <footer class="footer"> 159 <div class="container"><p>This page is the operational source of truth for pre-arrival readiness and first-power-on execution.</p></div> 160 </footer> 161 </body> 162 </html>