index.html
1 <!doctype html> 2 <html lang="en"> 3 <head> 4 <meta charset="utf-8"> 5 <meta name="viewport" content="width=device-width, initial-scale=1"> 6 <title>AERIS-10 Engineering Docs</title> 7 <link rel="stylesheet" href="assets/style.css"> 8 </head> 9 <body> 10 <header class="topbar"> 11 <div class="container nav"> 12 <a class="brand" href="index.html">AERIS-10 Docs</a> 13 <nav> 14 <a href="architecture.html">Architecture</a> 15 <a href="implementation-log.html">Implementation Log</a> 16 <a href="bring-up.html">Bring-Up</a> 17 <a href="reports.html">Reports</a> 18 <a href="release-notes.html">Release Notes</a> 19 </nav> 20 </div> 21 </header> 22 23 <main class="container page"> 24 <section class="hero"> 25 <p class="eyebrow">Open-Source Phased Array Radar</p> 26 <h1>Engineering Documentation Site</h1> 27 <p>This site tracks architecture, validated implementation baselines, constraint cleanup progress, and pre-hardware bring-up readiness for AERIS-10.</p> 28 <div class="cta-row"> 29 <a class="button" href="implementation-log.html">View Change Timeline</a> 30 <a class="button ghost" href="bring-up.html">Open Readiness Package</a> 31 </div> 32 </section> 33 34 <section class="stats-grid"> 35 <article class="card stat"> 36 <h2>Tracked Timing Baseline</h2> 37 <p class="metric">WNS +0.058 ns</p> 38 <p class="muted">WHS +0.068, WPWS +0.684 after validated Build 16 XDC port</p> 39 </article> 40 <article class="card stat"> 41 <h2>Regression Status</h2> 42 <p class="metric">MCU 15 / 15, FPGA 18 / 18</p> 43 <p class="muted">Host firmware regression plus FPGA unit and integration suites passing</p> 44 </article> 45 <article class="card stat"> 46 <h2>Methodology State</h2> 47 <p class="metric">XDCB-5 = 0</p> 48 <p class="muted">Single documented TIMING-18 residue on `ft601_txe` async observation</p> 49 </article> 50 <article class="card stat"> 51 <h2>Current Phase</h2> 52 <p class="metric">Pre-Hardware Readiness</p> 53 <p class="muted">Board-arrival smoke test, artifact inventory, and open-risk tracking prepared</p> 54 </article> 55 </section> 56 57 <section class="grid-2"> 58 <article class="card"> 59 <h2>What changed recently</h2> 60 <ul> 61 <li>Ported the validated Build 16 production-target XDC cleanup into the tracked repository.</li> 62 <li>Preserved positive post-route timing while clearing XDCB-5 and reducing methodology residue to a single documented item.</li> 63 <li>Validated the tracked branch with MCU host regression and FPGA regression/integration suites.</li> 64 <li>Refreshed the bring-up documentation into a pre-arrival readiness package for the FPGA module and carrier board.</li> 65 <li>Kept upstream ADAR1000 bulk imports out of the baseline pending selective, justified reuse only.</li> 66 </ul> 67 </article> 68 <article class="card"> 69 <h2>Documentation Map</h2> 70 <ul> 71 <li><a href="architecture.html">System and FPGA Architecture</a></li> 72 <li><a href="implementation-log.html">Detailed Engineering Change Log</a></li> 73 <li><a href="bring-up.html">Pre-Arrival Bring-Up Plan, Artifact Checklist, and Open Risks</a></li> 74 <li><a href="reports.html">Published reports, simulations, and artifact context</a></li> 75 <li><a href="release-notes.html">Release Notes by Key Commit</a></li> 76 </ul> 77 </article> 78 </section> 79 </main> 80 81 <footer class="footer"> 82 <div class="container"> 83 <p>AERIS-10 documentation published via GitHub Pages from <code>/docs</code>.</p> 84 </div> 85 </footer> 86 </body> 87 </html>