release-notes.html
1 <!doctype html> 2 <html lang="en"> 3 <head> 4 <meta charset="utf-8"> 5 <meta name="viewport" content="width=device-width, initial-scale=1"> 6 <title>AERIS-10 Docs | Release Notes</title> 7 <link rel="stylesheet" href="assets/style.css"> 8 </head> 9 <body> 10 <header class="topbar"> 11 <div class="container nav"> 12 <a class="brand" href="index.html">AERIS-10 Docs</a> 13 <nav> 14 <a href="architecture.html">Architecture</a> 15 <a href="implementation-log.html">Implementation Log</a> 16 <a href="bring-up.html">Bring-Up</a> 17 <a href="reports.html">Reports</a> 18 <a href="release-notes.html">Release Notes</a> 19 </nav> 20 </div> 21 </header> 22 23 <main class="container page"> 24 <section class="hero"> 25 <p class="eyebrow">Traceability</p> 26 <h1>Release Notes by Key Commit</h1> 27 <p>Milestone notes keyed to major bring-up, debug, and documentation commits.</p> 28 </section> 29 30 <section class="card" style="margin-top:0.8rem;"> 31 <h2>Commit timeline</h2> 32 <div class="table-wrap"> 33 <table> 34 <thead> 35 <tr> 36 <th>Commit</th> 37 <th>Title</th> 38 <th>Impact</th> 39 </tr> 40 </thead> 41 <tbody> 42 <tr> 43 <td><code>TBD</code> <strong>v0.1.8-te0713-ft601-dev</strong></td> 44 <td>TE0713/TE0701 + UMFT601X-B FT601 integration dev bitstream</td> 45 <td>First timing-clean FT601 USB integration build for the Trenz + UMFT601X-B FMC LPC stack. Wrapper module (<code>radar_system_top_te0713_umft601x_dev</code>) instantiates the full <code>usb_data_interface</code> with synthetic test data (range/Doppler/CFAR packets). Timing closure achieved after fixing source-synchronous clock skew: replaced <code>set_output_delay</code> with <code>set_max_delay -datapath_only</code> for outputs, removed erroneous <code>set_input_delay</code> on output-only <code>ft601_be[*]</code>. WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors. Strategy: <code>Performance_ExplorePostRoutePhysOpt</code>. Vivado 2025.2. Bitstream: <code>docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit</code>.</td> 46 </tr> 47 <tr> 48 <td><code>TBD</code> <strong>v0.1.7-te0713-heartbeat</strong></td> 49 <td>TE0713/TE0701 minimal heartbeat bring-up bitstream</td> 50 <td>Created a low-risk bring-up artifact for the Trenz TE0713 + TE0701 stack using <code>radar_system_top_te0713_dev</code> and <code>te0713_te0701_minimal.xdc</code>. Remote Vivado 2025.2 build completed with DRC 0 errors, WNS +17.863 ns, WHS +0.265 ns. Intended as the first board-day image before FT601 arrival and before any radar-path integration.</td> 51 </tr> 52 <tr> 53 <td><code>ed629e7</code> <strong>v0.1.6-mti</strong></td> 54 <td>Build 25: MTI canceller + DC notch filter integration</td> 55 <td>New production baseline. WNS +0.132 ns, WHS +0.058 ns. 9,252 LUTs (6.87%), 12,488 FFs (4.64%), 17 BRAM (4.66%), 142 DSP48E1 (19.19%), 0.753 W. New modules: mti_canceller.v (2-pulse canceller, H(z)=1-z^-1), DC notch filter (inline in system_top). Two new host registers: host_mti_enable (0x26), host_dc_notch_width (0x27). 23/23 FPGA, 20/20 MCU, 3/3 real-data co-sim exact match.</td> 56 </tr> 57 <tr> 58 <td><code>075ae1e</code> <strong>v0.1.5-cfar</strong></td> 59 <td>Build 24: CA-CFAR detector integration with pipelined noise computation</td> 60 <td>Prior production baseline. WNS +0.179 ns, WHS +0.056 ns. 8,558 LUTs, 10,384 FFs, 17 BRAM, 142 DSP48E1, 0.754 W. CA/GO/SO CFAR modes with BRAM magnitude buffer, sliding-window algorithm. Host-configurable guard/train/alpha/mode registers (0x21-0x25). Build 23 timing failure fixed by pipelining noise computation. 22/22 FPGA, 20/20 MCU.</td> 61 </tr> 62 <tr> 63 <td><code>e93bc33</code> <strong>v0.1.4-prod-fixes</strong></td> 64 <td>7 production-quality fixes: detection bugs, digital gain, watchdog, dead code removal</td> 65 <td>Detection sticky flag + magnitude lag fix, rename cfar→threshold_detect, host-configurable digital gain control (power-of-2 shift), Doppler/chirps mismatch protection (clamp + error flag), decimator watchdog timeout, bypass_mode dead code removal, range-mode register (0x20). Real-data co-sim framework added. 22/22 FPGA.</td> 66 </tr> 67 <tr> 68 <td><code>2efab23</code> <strong>v0.1.4-build21</strong></td> 69 <td>Build 21: FFT opts + E2E RTL fixes + Vivado DRC fix + MMCM LOCKED false_path fix</td> 70 <td>New production baseline. WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns. 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W. Includes 4-cycle FFT butterfly (20% throughput), barrel-shift twiddle (-1 DSP), Vivado DRC multiple-driver fix for data_pending flags, MMCM LOCKED XDC false_path fix (-from → -through). 19/19 FPGA, 20/20 MCU.</td> 71 </tr> 72 <tr> 73 <td><code>0773001</code></td> 74 <td>E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring</td> 75 <td>New 46-check E2E testbench (tb_system_e2e.v) across 12 groups. RTL fixes: TX/RX mixer enables mutually exclusive by FSM state, USB write FSM data_pending sticky flags with stream-control reset default 3'b001, STM32 toggle signal wiring for mode-00, dynamic frame detection. USB tests 21/22/56 and regression script PASS/FAIL parsing fixed. 19/19 FPGA, 20/20 MCU.</td> 76 </tr> 77 <tr> 78 <td><code>a3e1996</code></td> 79 <td>FFT engine: merge SHIFT into WRITE (4-cycle butterfly) + barrel-shift twiddle index</td> 80 <td>SHIFT state merged into WRITE for 5→4 cycle butterfly (20% throughput gain). Multiplier-based twiddle index replaced with barrel-shift (frees 1 DSP48). Verified via FFT testbench; no timing regression expected.</td> 81 </tr> 82 <tr> 83 <td><code>7cdfa48</code></td> 84 <td>Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback</td> 85 <td>Runtime-configurable chirp timing (6 new opcodes 0x10-0x15), stream control gating (opcode 0x04 now gates USB write FSM), CFAR threshold wiring (opcode 0x03 replaces hardcoded value), status readback (opcode 0xFF returns 7-word packet). 4 new TB test groups. 18/18 FPGA, 20/20 MCU regression.</td> 86 </tr> 87 <tr> 88 <td><code>e5d1b3c</code></td> 89 <td>Gap 4 USB Read Path: host-to-FPGA command path with toggle CDC</td> 90 <td>Wired FT601 read FSM cmd_* outputs through toggle CDC to clk_100m command decode registers. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming. 3 new TB test groups (55 checks). 18/18 FPGA regression.</td> 91 </tr> 92 <tr> 93 <td><code>c6103b3</code> <strong>v0.1.3-build20</strong></td> 94 <td>Gap 7 MMCM jitter cleaner + CIC CREG pipeline + XDC clock-name fix</td> 95 <td>Added 400 MHz MMCM for ADC clock jitter cleaning, CIC comb DSP48E1 CREG pipeline, and fixed XDC conflicting generated clock. Build 20: WNS +0.426 ns (7x improvement over Build 18). All timing met.</td> 96 </tr> 97 <tr> 98 <td><code>f3bbf77</code></td> 99 <td>Gap 3 Safety Architecture</td> 100 <td>IWDG watchdog, Emergency_Stop PA rail cutoff, temperature max guard, periodic IDQ re-read, emergency state ordering. 5 new MCU tests, 20/20 pass.</td> 101 </tr> 102 <tr> 103 <td><code>c87dce0</code></td> 104 <td>Gap 5 BRAM async reset fix</td> 105 <td>Fixed chirp memory loader BRAM async reset to use synchronous reset pattern per Xilinx UG901 guidelines.</td> 106 </tr> 107 <tr> 108 <td><code>3b7afba</code> <strong>v0.1.2-build18</strong></td> 109 <td>Build 18 production build</td> 110 <td>Production baseline: WNS +0.062 ns, WHS +0.059 ns. 6,088 LUTs, 8,946 FFs, 16 BRAM, 140 DSP48E1, 0.631 W.</td> 111 </tr> 112 <tr> 113 <td><code>ed6f79c</code> <strong>v0.1.1-build17</strong></td> 114 <td>FIR DSP48 pipelining + matched filter BRAM migration</td> 115 <td>Build 17 production build with DSP48 pipelining improvements.</td> 116 </tr> 117 <tr> 118 <td><code>c466021</code></td> 119 <td>Firmware bug sweep closure (B12-B17)</td> 120 <td>Closed the PA calibration, ADC buffer, DIAG macro, TIM3 PWM, and stale-diagnostic issues with additional MCU regression coverage.</td> 121 </tr> 122 <tr> 123 <td><code>49c9aa2</code></td> 124 <td>SPI platform fix plus FPGA B2/B3 timing work</td> 125 <td>Fixed the legacy platform SPI transmit-only path and landed chirp BRAM migration plus Doppler DSP48 pipelining work.</td> 126 </tr> 127 <tr> 128 <td><code>3b32f67</code></td> 129 <td>ADF4382A SPI and chip-select correctness</td> 130 <td>Fixed platform SPI ops wiring, added software-managed CS behavior, and widened SPI chip-select storage to handle STM32 pin values correctly.</td> 131 </tr> 132 <tr> 133 <td><code>3979693</code></td> 134 <td>Initial 8-firmware-bug closure with tests</td> 135 <td>Closed the LO init ordering, AD9523 sequencing, sync trigger, temperature timer, GPIO mapping, and related MCU issues with regression coverage.</td> 136 </tr> 137 </tbody> 138 </table> 139 </div> 140 </section> 141 142 <section class="card" style="margin-top:0.8rem;"> 143 <h2>Tagged releases</h2> 144 <ul> 145 <li><strong>v0.1.7-te0713-heartbeat</strong> — TE0713/TE0701 first-power baseline. Minimal heartbeat top, DRC clean, WNS +17.863 ns, WHS +0.265 ns. Artifact tracked at <code>docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit</code>.</li> 146 <li><strong>v0.1.6-mti</strong> (ed629e7) — Current production baseline. WNS +0.132 ns, WHS +0.058 ns. MTI canceller + DC notch filter. 9,252 LUTs, 12,488 FFs, 142 DSP48E1, 17 BRAM. 0.753 W.</li> 147 <li><strong>v0.1.5-cfar</strong> (075ae1e) — Prior production baseline. WNS +0.179 ns. CA-CFAR detector (CA/GO/SO modes) with pipelined noise computation.</li> 148 <li><strong>v0.1.4-prod-fixes</strong> (e93bc33) — 7 production fixes + real-data co-sim framework. WNS same as Build 21 (simulation-only changes).</li> 149 <li><strong>v0.1.4-build21</strong> (2efab23) — Pre-CFAR production baseline. WNS +0.156 ns, WHS +0.064 ns. Includes FFT opts, E2E RTL fixes, Vivado DRC fix, MMCM LOCKED XDC fix. 139 DSP48E1 (-1 vs Build 20).</li> 150 <li><strong>v0.1.3-build20</strong> (c6103b3) — Prior production baseline. WNS +0.426 ns, all timing met. Includes Gaps 3, 5, 7.</li> 151 <li><strong>v0.1.2-build18</strong> (3b7afba) — Prior production baseline. WNS +0.062 ns.</li> 152 <li><strong>v0.1.1-build17</strong> (ed6f79c) — FIR DSP48 + BRAM migration build.</li> 153 <li><strong>v0.1.0-bringup</strong> — Initial bring-up tag.</li> 154 </ul> 155 </section> 156 157 <section class="card" style="margin-top:0.8rem;"> 158 <h2>Architectural gap status</h2> 159 <div class="table-wrap"> 160 <table> 161 <thead><tr><th>#</th><th>Gap</th><th>Status</th></tr></thead> 162 <tbody> 163 <tr><td>3</td><td>Safety Architecture</td><td>Done (f3bbf77)</td></tr> 164 <tr><td>5</td><td>BRAM Async Reset</td><td>Done (c87dce0)</td></tr> 165 <tr><td>7</td><td>400 MHz MMCM</td><td>Done (c6103b3, Build 20)</td></tr> 166 <tr><td>4</td><td>USB Read Path</td><td>Done (e5d1b3c)</td></tr> 167 <tr><td>2</td><td>GUI Settings</td><td>Done (7cdfa48)</td></tr> 168 <tr><td>6</td><td>CDC-15 USB Buses</td><td>Post-bring-up</td></tr> 169 <tr><td>1</td><td>CFAR Real Implementation</td><td>Done (075ae1e, Build 24 + MTI in ed629e7)</td></tr> 170 </tbody> 171 </table> 172 </div> 173 </section> 174 175 <section class="card" style="margin-top:0.8rem;"> 176 <h2>Open in GitHub</h2> 177 <ul> 178 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/ed629e7" target="_blank" rel="noopener">ed629e7</a> MTI canceller + DC notch filter (v0.1.6-mti)</li> 179 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/075ae1e" target="_blank" rel="noopener">075ae1e</a> Build 24 report (v0.1.5-cfar)</li> 180 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/0745cc4" target="_blank" rel="noopener">0745cc4</a> Pipeline CFAR noise computation (timing fix)</li> 181 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f71923b" target="_blank" rel="noopener">f71923b</a> Integrate CA-CFAR detector</li> 182 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/e93bc33" target="_blank" rel="noopener">e93bc33</a> Production fixes 1-7 (v0.1.4-prod-fixes)</li> 183 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/0b06436" target="_blank" rel="noopener">0b06436</a> Real-data co-simulation (v0.1.4-pre-fixes)</li> 184 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/2efab23" target="_blank" rel="noopener">2efab23</a> Build 21: FFT opts + DRC fix + XDC fix (v0.1.4-build21)</li> 185 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/0773001" target="_blank" rel="noopener">0773001</a> E2E test + RTL fixes</li> 186 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/a3e1996" target="_blank" rel="noopener">a3e1996</a> FFT engine optimizations</li> 187 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/7cdfa48" target="_blank" rel="noopener">7cdfa48</a> Gap 2 GUI Settings</li> 188 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/e5d1b3c" target="_blank" rel="noopener">e5d1b3c</a> Gap 4 USB Read Path</li> 189 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c6103b3" target="_blank" rel="noopener">c6103b3</a> Gap 7 MMCM + CREG (v0.1.3-build20)</li> 190 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f3bbf77" target="_blank" rel="noopener">f3bbf77</a> Gap 3 Safety Architecture</li> 191 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c87dce0" target="_blank" rel="noopener">c87dce0</a> Gap 5 BRAM Reset</li> 192 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c466021" target="_blank" rel="noopener">c466021</a> Firmware bugs B12-B17</li> 193 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/49c9aa2" target="_blank" rel="noopener">49c9aa2</a> SPI + FPGA timing</li> 194 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3b32f67" target="_blank" rel="noopener">3b32f67</a> ADF4382A SPI</li> 195 <li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3979693" target="_blank" rel="noopener">3979693</a> Initial 8-bug closure</li> 196 </ul> 197 </section> 198 </main> 199 200 <footer class="footer"> 201 <div class="container"><p>Keep this page updated whenever major hardware validation milestones are merged.</p></div> 202 </footer> 203 </body> 204 </html>