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1 <!doctype html> 2 <html lang="en"> 3 <head> 4 <meta charset="utf-8"> 5 <meta name="viewport" content="width=device-width, initial-scale=1"> 6 <title>AERIS-10 Docs | Reports</title> 7 <link rel="stylesheet" href="assets/style.css"> 8 </head> 9 <body> 10 <header class="topbar"> 11 <div class="container nav"> 12 <a class="brand" href="index.html">AERIS-10 Docs</a> 13 <nav> 14 <a href="architecture.html">Architecture</a> 15 <a href="implementation-log.html">Implementation Log</a> 16 <a href="bring-up.html">Bring-Up</a> 17 <a href="reports.html">Reports</a> 18 <a href="release-notes.html">Release Notes</a> 19 </nav> 20 </div> 21 </header> 22 23 <main class="container page"> 24 <section class="hero"> 25 <p class="eyebrow">Artifacts</p> 26 <h1>Published Reports and Visuals</h1> 27 <p>Central access point for antenna simulations, implementation summaries, timing baselines, and board-day artifact references.</p> 28 <div class="cta-row"> 29 <a class="button" href="board-day-worksheet.html">Open Board-Day Worksheet</a> 30 <a class="button ghost" href="bring-up.html">Open Bring-Up Plan</a> 31 </div> 32 </section> 33 34 <section class="card" style="margin-top:0.8rem;"> 35 <h2>Current FPGA implementation status</h2> 36 <ul> 37 <li><strong>Build 25</strong> is the current production baseline for the XC7A200T target. All timing constraints met. Includes MTI canceller + DC notch filter integration on top of CA-CFAR.</li> 38 <li>Build 25 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build25/</code>.</li> 39 <li>Build 24 (v0.1.5-cfar) retained as pre-MTI reference at <code>reports_build24/</code>.</li> 40 <li>Build 21 (v0.1.4-build21) retained as pre-CFAR reference at <code>reports_build21/</code>.</li> 41 </ul> 42 </section> 43 44 <!-- ===== Build 25 — 15-Point Report ===== --> 45 <section class="card" style="margin-top:0.8rem;"> 46 <h2>Build 25 — 15-Point Engineering Report</h2> 47 <p><span class="chip">Status: PASS — Production-safe bitstream generated</span></p> 48 <p class="muted">Date: 2026-03-20 | Commit: <code>ed629e7</code> | Device: XC7A200T-2FBG484I | Vivado 2025.2</p> 49 50 <!-- 1. Timing --> 51 <h3>1. Timing Summary</h3> 52 <div class="table-wrap"> 53 <table> 54 <thead><tr><th>Clock Domain</th><th>Period (ns)</th><th>WNS (ns)</th><th>WHS (ns)</th><th>WPWS (ns)</th><th>Status</th></tr></thead> 55 <tbody> 56 <tr><td>clk_100m</td><td>10.000</td><td>+0.634</td><td>+0.058</td><td>+3.870</td><td>PASS</td></tr> 57 <tr><td>clk_mmcm_out0 (400 MHz)</td><td>2.500</td><td>+0.304</td><td>+0.115</td><td>+0.684</td><td>PASS</td></tr> 58 <tr><td>adc_dco_p</td><td>—</td><td>+0.904</td><td>—</td><td>+0.361</td><td>PASS</td></tr> 59 <tr><td>ft601_clk_in</td><td>10.000</td><td>+0.132</td><td>+0.121</td><td>+4.500</td><td>PASS</td></tr> 60 <tr><td>clk_120m_dac</td><td>—</td><td>+0.773</td><td>+0.151</td><td>+3.666</td><td>PASS</td></tr> 61 </tbody> 62 </table> 63 </div> 64 <p class="muted">TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints. Overall WNS +0.132 ns (ft601_clk_in domain, USB FSM path). Overall WHS +0.058 ns.</p> 65 66 <!-- 2. Utilization --> 67 <h3>2. Utilization (Post-Route)</h3> 68 <div class="table-wrap"> 69 <table> 70 <thead><tr><th>Resource</th><th>Build 24 (CFAR)</th><th>Build 25 (MTI)</th><th>Available</th><th>Util%</th><th>Delta</th></tr></thead> 71 <tbody> 72 <tr><td>Slice LUTs</td><td>8,558</td><td>9,252</td><td>134,600</td><td>6.87%</td><td>+694 (+8.1%)</td></tr> 73 <tr><td>Slice Registers (FFs)</td><td>10,384</td><td>12,488</td><td>269,200</td><td>4.64%</td><td>+2,104 (+20%)</td></tr> 74 <tr><td>Block RAM Tiles</td><td>17</td><td>17</td><td>365</td><td>4.66%</td><td>0</td></tr> 75 <tr><td> RAMB36E1</td><td>12</td><td>12</td><td>365</td><td>3.29%</td><td>0</td></tr> 76 <tr><td> RAMB18E1</td><td>10</td><td>10</td><td>730</td><td>1.37%</td><td>0</td></tr> 77 <tr><td>LUT as Distributed RAM</td><td>—</td><td>48</td><td>46,200</td><td>0.10%</td><td>—</td></tr> 78 <tr><td>DSP48E1</td><td>142</td><td>142</td><td>740</td><td>19.19%</td><td>0</td></tr> 79 <tr><td>Bonded IOBs</td><td>178</td><td>178</td><td>285</td><td>62.46%</td><td>0</td></tr> 80 <tr><td>BUFGCTRL</td><td>5</td><td>5</td><td>32</td><td>15.63%</td><td>0</td></tr> 81 <tr><td>MMCME2_ADV</td><td>1</td><td>1</td><td>10</td><td>10.00%</td><td>0</td></tr> 82 </tbody> 83 </table> 84 </div> 85 <p class="muted">MTI canceller added +694 LUTs (distributed RAM for chirp delay line + subtraction logic + DC notch comparators) and +2,104 FFs (I/Q pipeline registers, saturation logic, notch width comparators). Zero BRAM and DSP impact — MTI uses distributed RAM and fabric arithmetic only.</p> 86 87 <!-- 3. DSP48E1 Breakdown --> 88 <h3>3. DSP48E1 Breakdown by Module</h3> 89 <div class="table-wrap"> 90 <table> 91 <thead><tr><th>Module</th><th>DSP48E1</th><th>Notes</th></tr></thead> 92 <tbody> 93 <tr><td>DDC (FIR I + FIR Q + CIC + NCO)</td><td>117</td><td>Dominant consumer: 47+47 FIR taps + 10+10 CIC + 2 DDC + 1 NCO</td></tr> 94 <tr><td>Matched Filter Processing Chain</td><td>12</td><td>8 FFT butterflies + 4 freq-domain multiply</td></tr> 95 <tr><td>Doppler Processor + FFT</td><td>10</td><td>8 FFT butterflies + 2 magnitude</td></tr> 96 <tr><td>CFAR Detector</td><td>3</td><td>alpha*noise multiply + GO/SO cross-multiply (pipelined)</td></tr> 97 <tr><td>MTI Canceller</td><td>0</td><td>Pure fabric arithmetic (subtraction + saturation)</td></tr> 98 <tr><td><strong>Total</strong></td><td><strong>142</strong></td><td>19.19% of 740 available</td></tr> 99 </tbody> 100 </table> 101 </div> 102 103 <!-- 4. BRAM Breakdown --> 104 <h3>4. BRAM Breakdown by Module</h3> 105 <div class="table-wrap"> 106 <table> 107 <thead><tr><th>Module</th><th>RAMB36</th><th>RAMB18</th><th>Tiles</th><th>Notes</th></tr></thead> 108 <tbody> 109 <tr><td>Doppler Processor</td><td>4</td><td>0</td><td>4</td><td>Range-Doppler accumulation buffers</td></tr> 110 <tr><td>Matched Filter (mf_dual)</td><td>2</td><td>10</td><td>7</td><td>Coefficient + I/Q data BRAMs</td></tr> 111 <tr><td>CFAR Detector</td><td>1</td><td>0</td><td>1</td><td>Magnitude buffer (2048×17 bits)</td></tr> 112 <tr><td>Transmitter (chirp mem)</td><td>1</td><td>0</td><td>1</td><td>Chirp waveform storage</td></tr> 113 <tr><td>FFT Engines (2×)</td><td>4</td><td>0</td><td>4</td><td>Twiddle factor + butterfly BRAMs</td></tr> 114 <tr><td>MTI Canceller</td><td>0</td><td>0</td><td>0</td><td>Uses distributed RAM (LUTs), not BRAM</td></tr> 115 <tr><td><strong>Total</strong></td><td><strong>12</strong></td><td><strong>10</strong></td><td><strong>17</strong></td><td>4.66% of 365 tiles</td></tr> 116 </tbody> 117 </table> 118 </div> 119 120 <!-- 5. Power --> 121 <h3>5. Power Estimate</h3> 122 <div class="table-wrap"> 123 <table> 124 <thead><tr><th>Category</th><th>Build 24</th><th>Build 25</th></tr></thead> 125 <tbody> 126 <tr><td>Dynamic Power</td><td>0.591 W</td><td>0.590 W</td></tr> 127 <tr><td>Device Static</td><td>0.163 W</td><td>0.163 W</td></tr> 128 <tr><td><strong>Total On-Chip</strong></td><td><strong>0.754 W</strong></td><td><strong>0.753 W</strong></td></tr> 129 </tbody> 130 </table> 131 </div> 132 <p class="muted">Power is essentially unchanged (-1 mW). MTI logic is lightweight fabric arithmetic; DC notch is combinational zeroing with negligible dynamic power.</p> 133 134 <!-- 6. Critical Path --> 135 <h3>6. Critical Path Analysis</h3> 136 <p>The tightest path (WNS = +0.132 ns) is in the <code>ft601_clk_in</code> (100 MHz) domain: <code>ft601_rxf</code> input pad → 8 logic levels (IBUF + LUT1 + LUT3 + 4×LUT6 + LUT5) → <code>usb_inst/FSM_sequential_current_state_reg[2]/D</code>. This is the USB read FSM path and is unrelated to MTI or CFAR.</p> 137 <p>The <code>clk_100m</code> domain (where MTI, CFAR, and Doppler operate) has +0.634 ns slack — improved from Build 24's +0.287 ns. The MTI canceller adds no new critical paths.</p> 138 139 <!-- 7. Post-synth vs Post-route --> 140 <h3>7. Post-Synthesis vs Post-Route Comparison</h3> 141 <div class="table-wrap"> 142 <table> 143 <thead><tr><th>Metric</th><th>Post-Synth</th><th>Post-Route (final)</th></tr></thead> 144 <tbody> 145 <tr><td>WNS (setup)</td><td>+0.123 ns</td><td>+0.132 ns</td></tr> 146 <tr><td>WHS (hold)</td><td>-0.076 ns (29 violations)</td><td>+0.058 ns (0 violations)</td></tr> 147 <tr><td>LUTs</td><td>9,363</td><td>9,252</td></tr> 148 <tr><td>FFs</td><td>12,537</td><td>12,488</td></tr> 149 </tbody> 150 </table> 151 </div> 152 <p class="muted">Post-route phys_opt resolved all 29 hold violations and improved setup slack by 9 ps. LUT/FF count reduced slightly by optimization passes.</p> 153 154 <!-- 8. DRC --> 155 <h3>8. DRC (Design Rule Checks)</h3> 156 <p>184 checks performed. <strong>0 errors, 0 critical warnings.</strong> Same advisory/warning profile as Build 24 (DPIP-1, DPOP-1/2, REQP-1839/1840, RPBF-3 etc.). No new DRC issues from MTI integration.</p> 157 158 <!-- 9. Methodology --> 159 <h3>9. Methodology Report</h3> 160 <p>Same methodology advisory profile as Build 24. No new methodology warnings from MTI or DC notch logic.</p> 161 162 <!-- 10. Congestion --> 163 <h3>10. Congestion</h3> 164 <p><strong>No congestion windows found above level 5.</strong> The design remains well-placed at 6.87% LUT utilization.</p> 165 166 <!-- 11. Route Status --> 167 <h3>11. Route Status</h3> 168 <ul> 169 <li>Total logical nets: 34,325</li> 170 <li>Routable nets: 24,510 — <strong>24,510 fully routed (100%)</strong></li> 171 <li>Nets with routing errors: <strong>0</strong></li> 172 </ul> 173 174 <!-- 12. Hierarchical Utilization (MTI focus) --> 175 <h3>12. Hierarchical Utilization — MTI Module</h3> 176 <div class="table-wrap"> 177 <table> 178 <thead><tr><th>Instance</th><th>LUTs</th><th>FFs</th><th>BRAM</th><th>DSP</th><th>Notes</th></tr></thead> 179 <tbody> 180 <tr><td>radar_system_top (total)</td><td>9,252</td><td>12,488</td><td>17</td><td>142</td><td>Full design</td></tr> 181 <tr><td> cfar_inst</td><td>2,210</td><td>1,282</td><td>1</td><td>3</td><td>CA-CFAR detector</td></tr> 182 <tr><td> rx_inst (receiver)</td><td>6,731</td><td>10,703</td><td>10</td><td>139</td><td>Full receiver chain</td></tr> 183 <tr><td> mti_inst</td><td>544</td><td>2,082</td><td>0</td><td>0</td><td>MTI canceller (new)</td></tr> 184 <tr><td> doppler_proc</td><td>681</td><td>540</td><td>4</td><td>10</td><td>Doppler processor</td></tr> 185 <tr><td> ddc</td><td>676</td><td>2,959</td><td>0</td><td>117</td><td>DDC subsystem</td></tr> 186 <tr><td> mf_dual</td><td>2,439</td><td>4,796</td><td>7</td><td>12</td><td>Matched filter</td></tr> 187 <tr><td> range_decim</td><td>219</td><td>129</td><td>0</td><td>0</td><td>Range bin decimator</td></tr> 188 <tr><td> usb_inst</td><td>159</td><td>217</td><td>0</td><td>0</td><td>USB data interface</td></tr> 189 <tr><td> tx_inst</td><td>111</td><td>91</td><td>1</td><td>0</td><td>Transmitter</td></tr> 190 </tbody> 191 </table> 192 </div> 193 <p class="muted">MTI canceller: 544 LUTs (0.40% device), 2,082 FFs (0.77% device), 0 BRAM, 0 DSP. The high FF count is from the chirp delay line (64 range bins × 16-bit I + 16-bit Q = 2,048 FFs for storage) implemented as distributed register file rather than BRAM.</p> 194 195 <!-- 13. Build Comparison --> 196 <h3>13. Build-Over-Build Comparison</h3> 197 <div class="table-wrap"> 198 <table> 199 <thead><tr><th>Metric</th><th>Build 21 (baseline)</th><th>Build 23 (failed)</th><th>Build 24 (CFAR)</th><th>Build 25 (MTI)</th></tr></thead> 200 <tbody> 201 <tr><td>WNS (ns)</td><td>+0.156</td><td style="color:#c33;">-0.309</td><td>+0.179</td><td style="color:#080;"><strong>+0.132</strong></td></tr> 202 <tr><td>WHS (ns)</td><td>+0.064</td><td>—</td><td>+0.056</td><td>+0.058</td></tr> 203 <tr><td>LUTs</td><td>6,192</td><td>8,668 (synth)</td><td>8,558</td><td>9,252</td></tr> 204 <tr><td>FFs</td><td>9,064</td><td>10,411 (synth)</td><td>10,384</td><td>12,488</td></tr> 205 <tr><td>BRAM Tiles</td><td>16</td><td>17 (synth)</td><td>17</td><td>17</td></tr> 206 <tr><td>DSP48E1</td><td>139</td><td>—</td><td>142</td><td>142</td></tr> 207 <tr><td>Power (W)</td><td>0.732</td><td>—</td><td>0.754</td><td>0.753</td></tr> 208 <tr><td>Bitstream</td><td>Safe</td><td style="color:#c33;">Unsafe</td><td>Safe</td><td style="color:#080;"><strong>Safe</strong></td></tr> 209 </tbody> 210 </table> 211 </div> 212 213 <!-- 14. MTI + DC Notch Resource Cost --> 214 <h3>14. MTI + DC Notch Integration Resource Cost</h3> 215 <div class="table-wrap"> 216 <table> 217 <thead><tr><th>Resource</th><th>MTI + DC Notch</th><th>% of Device</th><th>Notes</th></tr></thead> 218 <tbody> 219 <tr><td>LUTs</td><td>~694</td><td>0.52%</td><td>MTI: 544 LUTs (subtraction, saturation, mux). DC notch: ~150 LUTs (bin compare, data zeroing) in system_top.</td></tr> 220 <tr><td>FFs</td><td>~2,104</td><td>0.78%</td><td>MTI: 2,082 FFs (chirp delay line 64×32-bit + control). DC notch: ~22 FFs (registered width, active flags).</td></tr> 221 <tr><td>BRAM</td><td>0</td><td>0%</td><td>Chirp delay line fits in distributed registers (64 bins × 32 bits = 2,048 bits)</td></tr> 222 <tr><td>DSP48E1</td><td>0</td><td>0%</td><td>Subtraction uses fabric adders, no multiply needed</td></tr> 223 </tbody> 224 </table> 225 </div> 226 <p class="muted">Total MTI + DC notch cost: 0.52% of device LUTs, 0.78% of FFs. Very lightweight addition. Backward-compatible: <code>host_mti_enable</code> defaults to 0 (pass-through), <code>host_dc_notch_width</code> defaults to 0 (off).</p> 227 228 <!-- 15. Verification Summary --> 229 <h3>15. Verification Summary</h3> 230 <div class="table-wrap"> 231 <table> 232 <thead><tr><th>Test Suite</th><th>Tests</th><th>Checks</th><th>Status</th></tr></thead> 233 <tbody> 234 <tr><td>FPGA regression (run_regression.sh)</td><td>23</td><td>—</td><td>23/23 PASS</td></tr> 235 <tr><td>MTI standalone (tb_mti_canceller.v)</td><td>11</td><td>29</td><td>29/29 PASS</td></tr> 236 <tr><td>CFAR standalone (tb_cfar_ca.v)</td><td>14</td><td>23</td><td>23/23 PASS</td></tr> 237 <tr><td>Digital gain (tb_rx_gain_control.v)</td><td>—</td><td>32</td><td>32/32 PASS</td></tr> 238 <tr><td>Threshold fallback (tb_threshold_detector.v)</td><td>—</td><td>22</td><td>22/22 PASS</td></tr> 239 <tr><td>System E2E (tb_system_e2e.v, Group 14)</td><td>13</td><td>67</td><td>67/67 PASS</td></tr> 240 <tr><td>Real-data co-sim: Range FFT</td><td>1</td><td>1,024</td><td>1024/1024 exact</td></tr> 241 <tr><td>Real-data co-sim: Doppler</td><td>1</td><td>2,056</td><td>2056/2056 exact</td></tr> 242 <tr><td>Real-data co-sim: Full-chain</td><td>1</td><td>2,057</td><td>2057/2057 exact</td></tr> 243 <tr><td>MCU regression</td><td>20</td><td>—</td><td>20/20 PASS</td></tr> 244 </tbody> 245 </table> 246 </div> 247 <p class="muted">5,310 individual data checks across all RTL test suites. Zero failures. MTI standalone test covers: pass-through, first-chirp mute, subtraction correctness, stationary target cancellation, moving target preservation, saturation (positive/negative), enable toggle, reset behavior, bin tracking, back-to-back chirps, and negative value handling.</p> 248 249 <h3>Build 25 Artifacts</h3> 250 <ul> 251 <li>Bitstream: <code>~/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top_build25.bit</code> (9.7 MB)</li> 252 <li>Reports: <code>~/PLFM_RADAR_work/vivado_project/reports_build25/</code> (21 report files)</li> 253 <li>Build log: <code>~/PLFM_RADAR_work/build25.log</code></li> 254 <li>TCL script: <code>~/PLFM_RADAR_work/vivado_project/build25_mti.tcl</code></li> 255 </ul> 256 <p class="muted">Note: TCL crashed at step 13/15 (<code>extract_files</code> missing parameter) after all reports were generated. Same non-critical scripting bug as Build 24.</p> 257 </section> 258 259 <!-- ===== Build 24 — 15-Point Report ===== --> 260 <section class="card" style="margin-top:0.8rem;"> 261 <h2>Build 24 — 15-Point Engineering Report</h2> 262 <p><span class="chip">Status: PASS — Production-safe bitstream generated</span></p> 263 <p class="muted">Date: 2026-03-20 | Commit: <code>0745cc4</code> | Device: XC7A200T-2FBG484I | Vivado 2025.2</p> 264 265 <!-- 1. Timing --> 266 <h3>1. Timing Summary</h3> 267 <div class="table-wrap"> 268 <table> 269 <thead><tr><th>Clock Domain</th><th>Period (ns)</th><th>WNS (ns)</th><th>WHS (ns)</th><th>WPWS (ns)</th><th>Status</th></tr></thead> 270 <tbody> 271 <tr><td>clk_100m</td><td>10.000</td><td>+0.287</td><td>+0.056</td><td>+3.870</td><td>PASS</td></tr> 272 <tr><td>clk_mmcm_out0 (400 MHz)</td><td>2.500</td><td>+0.179</td><td>+0.092</td><td>+0.684</td><td>PASS</td></tr> 273 <tr><td>adc_dco_p</td><td>—</td><td>+0.904</td><td>—</td><td>+0.361</td><td>PASS</td></tr> 274 <tr><td>ft601_clk_in</td><td>10.000</td><td>+0.347</td><td>+0.094</td><td>+4.500</td><td>PASS</td></tr> 275 <tr><td>clk_120m_dac</td><td>—</td><td>+1.755</td><td>+0.056</td><td>+3.666</td><td>PASS</td></tr> 276 </tbody> 277 </table> 278 </div> 279 <p class="muted">TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints.</p> 280 281 <!-- 2. Utilization --> 282 <h3>2. Utilization (Post-Route)</h3> 283 <div class="table-wrap"> 284 <table> 285 <thead><tr><th>Resource</th><th>Build 21 (baseline)</th><th>Build 24</th><th>Available</th><th>Util%</th><th>Delta</th></tr></thead> 286 <tbody> 287 <tr><td>Slice LUTs</td><td>6,192</td><td>8,558</td><td>134,600</td><td>6.36%</td><td>+2,366 (+38%)</td></tr> 288 <tr><td>Slice Registers (FFs)</td><td>9,064</td><td>10,384</td><td>269,200</td><td>3.86%</td><td>+1,320 (+15%)</td></tr> 289 <tr><td>Block RAM Tiles</td><td>16</td><td>17</td><td>365</td><td>4.66%</td><td>+1</td></tr> 290 <tr><td> RAMB36E1</td><td>—</td><td>12</td><td>365</td><td>3.29%</td><td>—</td></tr> 291 <tr><td> RAMB18E1</td><td>—</td><td>10</td><td>730</td><td>1.37%</td><td>—</td></tr> 292 <tr><td>DSP48E1</td><td>139</td><td>142</td><td>740</td><td>19.19%</td><td>+3</td></tr> 293 <tr><td>Bonded IOBs</td><td>—</td><td>178</td><td>285</td><td>62.46%</td><td>—</td></tr> 294 <tr><td>BUFGCTRL</td><td>—</td><td>5</td><td>32</td><td>15.63%</td><td>—</td></tr> 295 <tr><td>MMCME2_ADV</td><td>—</td><td>1</td><td>10</td><td>10.00%</td><td>—</td></tr> 296 </tbody> 297 </table> 298 </div> 299 <p class="muted">CFAR added +1 BRAM18 (magnitude buffer, 2048×17), +3 DSP48E1 (alpha multiply + cross-multiply for GO/SO), +2,366 LUTs (sliding window logic, state machine, mode mux), +1,320 FFs (pipeline registers, counters, window sums).</p> 300 301 <!-- 3. DSP48E1 Breakdown --> 302 <h3>3. DSP48E1 Breakdown by Module</h3> 303 <div class="table-wrap"> 304 <table> 305 <thead><tr><th>Module</th><th>DSP48E1</th><th>Notes</th></tr></thead> 306 <tbody> 307 <tr><td>DDC (FIR I + FIR Q + CIC + NCO)</td><td>117</td><td>Dominant consumer: 47+47 FIR taps + 10+10 CIC + 2 DDC + 1 NCO</td></tr> 308 <tr><td>Matched Filter Processing Chain</td><td>12</td><td>8 FFT butterflies + 4 freq-domain multiply</td></tr> 309 <tr><td>Doppler Processor + FFT</td><td>10</td><td>8 FFT butterflies + 2 magnitude</td></tr> 310 <tr><td>CFAR Detector</td><td>3</td><td>alpha*noise multiply + GO/SO cross-multiply (pipelined)</td></tr> 311 <tr><td>System Top + Other</td><td>0</td><td>—</td></tr> 312 <tr><td><strong>Total</strong></td><td><strong>142</strong></td><td>19.19% of 740 available</td></tr> 313 </tbody> 314 </table> 315 </div> 316 317 <!-- 4. BRAM Breakdown --> 318 <h3>4. BRAM Breakdown by Module</h3> 319 <div class="table-wrap"> 320 <table> 321 <thead><tr><th>Module</th><th>RAMB36</th><th>RAMB18</th><th>Tiles</th><th>Notes</th></tr></thead> 322 <tbody> 323 <tr><td>Doppler Processor</td><td>4</td><td>0</td><td>4</td><td>Range-Doppler accumulation buffers</td></tr> 324 <tr><td>Matched Filter (mf_dual)</td><td>2</td><td>10</td><td>7</td><td>Coefficient + I/Q data BRAMs</td></tr> 325 <tr><td>CFAR Detector</td><td>1</td><td>0</td><td>1</td><td>Magnitude buffer (2048×17 bits)</td></tr> 326 <tr><td>Transmitter (chirp mem)</td><td>1</td><td>0</td><td>1</td><td>Chirp waveform storage</td></tr> 327 <tr><td>FFT Engines (2×)</td><td>4</td><td>0</td><td>4</td><td>Twiddle factor + butterfly BRAMs</td></tr> 328 <tr><td><strong>Total</strong></td><td><strong>12</strong></td><td><strong>10</strong></td><td><strong>17</strong></td><td>4.66% of 365 tiles</td></tr> 329 </tbody> 330 </table> 331 </div> 332 333 <!-- 5. Power --> 334 <h3>5. Power Estimate</h3> 335 <div class="table-wrap"> 336 <table> 337 <thead><tr><th>Category</th><th>Build 21</th><th>Build 24</th></tr></thead> 338 <tbody> 339 <tr><td>Dynamic Power</td><td>—</td><td>0.591 W</td></tr> 340 <tr><td>Device Static</td><td>—</td><td>0.163 W</td></tr> 341 <tr><td><strong>Total On-Chip</strong></td><td><strong>0.732 W</strong></td><td><strong>0.754 W</strong></td></tr> 342 <tr><td>Junction Temperature</td><td>—</td><td>26.9°C</td></tr> 343 <tr><td>Max Ambient (TJA)</td><td>—</td><td>83.1°C</td></tr> 344 </tbody> 345 </table> 346 </div> 347 <p class="muted">+22 mW (+3%) from CFAR logic. Well within thermal budget.</p> 348 349 <!-- 6. Critical Path --> 350 <h3>6. Critical Path Analysis</h3> 351 <p>The tightest path (WNS = +0.179 ns) is in the <code>clk_mmcm_out0</code> (400 MHz) domain: NCO sine LUT index register → LUT6 → <code>sin_abs_reg</code>. This is the same path that was critical in Build 21 and is unrelated to CFAR.</p> 352 <p>The <code>clk_100m</code> domain (where CFAR operates) has +0.287 ns slack. The Build 23 critical path (<code>cfar_inst/leading_sum → cross-multiply → alpha*noise DSP</code>, WNS = -0.309 ns) has been completely eliminated by the pipeline fix.</p> 353 354 <!-- 7. Post-synth vs Post-route --> 355 <h3>7. Post-Synthesis vs Post-Route Comparison</h3> 356 <div class="table-wrap"> 357 <table> 358 <thead><tr><th>Metric</th><th>Post-Synth</th><th>Post-Route (final)</th></tr></thead> 359 <tbody> 360 <tr><td>WNS (setup)</td><td>+0.123 ns</td><td>+0.179 ns</td></tr> 361 <tr><td>WHS (hold)</td><td>-0.076 ns (29 violations)</td><td>+0.056 ns (0 violations)</td></tr> 362 <tr><td>LUTs</td><td>8,671</td><td>8,558</td></tr> 363 <tr><td>FFs</td><td>10,433</td><td>10,384</td></tr> 364 </tbody> 365 </table> 366 </div> 367 <p class="muted">Post-route phys_opt resolved all 29 hold violations and improved setup slack by 56 ps. LUT/FF count reduced slightly by optimization passes.</p> 368 369 <!-- 8. DRC --> 370 <h3>8. DRC (Design Rule Checks)</h3> 371 <p>184 checks performed. <strong>0 errors, 0 critical warnings.</strong> Advisory/warning breakdown:</p> 372 <ul> 373 <li>DPIP-1 (input pipelining advisory): 68 — DSP input pipeline suggestions, acceptable for our architecture</li> 374 <li>DPOP-1/2 (output pipelining): 18 + 19 — DSP PREG/MREG advisory, non-critical</li> 375 <li>REQP-1839/1840 (BRAM async control): 20 + 20 — expected with async-reset BRAMs</li> 376 <li>RPBF-3 (IO buffering): 8 — intentional for differential pairs</li> 377 <li>CHECK-3 (report rule limit): 2 — tool display limit, not design issue</li> 378 <li>IOSR-1 (IOB set/reset sharing): 1 — non-critical</li> 379 </ul> 380 381 <!-- 9. Methodology --> 382 <h3>9. Methodology Report</h3> 383 <ul> 384 <li>DPIR-1 (async driver): 91 — known from async-reset architecture, mitigated by CDC modules</li> 385 <li>HPDR-1 (port direction inconsistency): 8 — bidir USB data bus, expected</li> 386 <li>LUTAR-1 (LUT drives async reset): 1 — watchdog reset path, intentional</li> 387 <li>PDRC-190 (suboptimal sync register placement): 3 — minor, does not affect timing</li> 388 <li>SYNTH-6 (RAM timing sub-optimal): 18 — inferred RAMs, all meeting timing</li> 389 <li>TIMING-9 (unknown CDC logic): 1 — covered by explicit CDC synchronizers</li> 390 <li>TIMING-28 (auto-derived clock in constraint): 8 — expected with MMCM-derived clocks</li> 391 <li>TIMING-47 (false path between sync clocks): 4 — intentional XDC false_path constraints</li> 392 </ul> 393 394 <!-- 10. Congestion --> 395 <h3>10. Congestion</h3> 396 <p><strong>No congestion windows found above level 5.</strong> The design is well-placed with no routing pressure. XC7A200T provides ample routing resources at 6.36% LUT utilization.</p> 397 398 <!-- 11. Route Status --> 399 <h3>11. Route Status</h3> 400 <ul> 401 <li>Total logical nets: 31,136</li> 402 <li>Routable nets: 22,026 — <strong>22,026 fully routed (100%)</strong></li> 403 <li>Nets with routing errors: <strong>0</strong></li> 404 </ul> 405 406 <!-- 12. Logic Level Distribution --> 407 <h3>12. Logic Level Distribution (Top 1000 Worst Paths)</h3> 408 <div class="table-wrap"> 409 <table> 410 <thead><tr><th>Clock</th><th>Period</th><th>Lvl 0</th><th>Lvl 1</th><th>Lvl 2</th><th>Lvl 3</th><th>Lvl 4</th><th>Lvl 5</th></tr></thead> 411 <tbody> 412 <tr><td>clk_100m</td><td>10.000 ns</td><td>25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr> 413 <tr><td>clk_mmcm_out0</td><td>2.500 ns</td><td>808</td><td>108</td><td>3</td><td>19</td><td>8</td><td>3</td></tr> 414 <tr><td>ft601_clk_in</td><td>10.000 ns</td><td>0</td><td>0</td><td>0</td><td>2</td><td>1</td><td>23</td></tr> 415 </tbody> 416 </table> 417 </div> 418 <p class="muted">The <code>clk_100m</code> domain has only level-0 paths in the top-1000 worst — CFAR pipeline fix reduced logic depth to register-to-register transfers. The 400 MHz DDC domain remains the most timing-critical area.</p> 419 420 <!-- 13. Build Comparison --> 421 <h3>13. Build-Over-Build Comparison</h3> 422 <div class="table-wrap"> 423 <table> 424 <thead><tr><th>Metric</th><th>Build 21 (baseline)</th><th>Build 23 (CFAR, failed)</th><th>Build 24 (CFAR + pipeline)</th></tr></thead> 425 <tbody> 426 <tr><td>WNS (ns)</td><td>+0.156</td><td style="color:#c33;">-0.309</td><td style="color:#080;"><strong>+0.179</strong></td></tr> 427 <tr><td>WHS (ns)</td><td>+0.064</td><td>—</td><td>+0.056</td></tr> 428 <tr><td>LUTs</td><td>6,192</td><td>8,668 (post-synth)</td><td>8,558</td></tr> 429 <tr><td>FFs</td><td>9,064</td><td>10,411 (post-synth)</td><td>10,384</td></tr> 430 <tr><td>BRAM Tiles</td><td>16</td><td>17 (post-synth)</td><td>17</td></tr> 431 <tr><td>DSP48E1</td><td>139</td><td>—</td><td>142</td></tr> 432 <tr><td>Power (W)</td><td>0.732</td><td>—</td><td>0.754</td></tr> 433 <tr><td>Bitstream</td><td>Safe</td><td style="color:#c33;">Unsafe (timing fail)</td><td style="color:#080;"><strong>Safe</strong></td></tr> 434 </tbody> 435 </table> 436 </div> 437 438 <!-- 14. CFAR Resource Cost --> 439 <h3>14. CFAR Integration Resource Cost</h3> 440 <div class="table-wrap"> 441 <table> 442 <thead><tr><th>Resource</th><th>CFAR Module Only</th><th>% of Device</th><th>Notes</th></tr></thead> 443 <tbody> 444 <tr><td>LUTs</td><td>2,229</td><td>1.66%</td><td>Sliding window sums, GO/SO cross-multiply, state machine, mode mux</td></tr> 445 <tr><td>FFs</td><td>1,281</td><td>0.48%</td><td>Pipeline registers, window counters, sum accumulators, noise_sum_reg</td></tr> 446 <tr><td>RAMB36E1</td><td>1</td><td>0.27%</td><td>Magnitude buffer: 2048 entries × 17 bits</td></tr> 447 <tr><td>DSP48E1</td><td>3</td><td>0.41%</td><td>alpha×noise, leading cross-multiply, lagging cross-multiply</td></tr> 448 </tbody> 449 </table> 450 </div> 451 <p class="muted">Total CFAR cost: 2.82% of device LUTs, 0.48% of FFs, 0.27% of BRAM, 0.41% of DSPs. Minimal impact on headroom.</p> 452 453 <!-- 15. Verification Summary --> 454 <h3>15. Verification Summary</h3> 455 <div class="table-wrap"> 456 <table> 457 <thead><tr><th>Test Suite</th><th>Tests</th><th>Checks</th><th>Status</th></tr></thead> 458 <tbody> 459 <tr><td>FPGA regression (run_regression.sh)</td><td>22</td><td>—</td><td>22/22 PASS</td></tr> 460 <tr><td>CFAR standalone (tb_cfar_ca.v)</td><td>14</td><td>23</td><td>23/23 PASS</td></tr> 461 <tr><td>Digital gain (tb_rx_gain_control.v)</td><td>—</td><td>32</td><td>32/32 PASS</td></tr> 462 <tr><td>Threshold fallback (tb_threshold_detector.v)</td><td>—</td><td>22</td><td>22/22 PASS</td></tr> 463 <tr><td>System E2E (tb_system_e2e.v, Group 14)</td><td>13</td><td>67</td><td>67/67 PASS</td></tr> 464 <tr><td>Real-data co-sim: Range FFT</td><td>1</td><td>1,024</td><td>1024/1024 exact</td></tr> 465 <tr><td>Real-data co-sim: Doppler</td><td>1</td><td>2,056</td><td>2056/2056 exact</td></tr> 466 <tr><td>Real-data co-sim: Full-chain</td><td>1</td><td>2,057</td><td>2057/2057 exact</td></tr> 467 <tr><td>MCU regression</td><td>20</td><td>—</td><td>20/20 PASS</td></tr> 468 </tbody> 469 </table> 470 </div> 471 <p class="muted">5,281 individual data checks across all RTL test suites. Zero failures. Real-data co-simulation confirms bit-exact match with Python golden reference across the entire signal processing chain.</p> 472 473 <h3>Build 24 Artifacts</h3> 474 <ul> 475 <li>Bitstream: <code>~/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top_build24.bit</code> (9.7 MB)</li> 476 <li>Reports: <code>~/PLFM_RADAR_work/vivado_project/reports_build24/</code> (21 report files)</li> 477 <li>Build log: <code>~/PLFM_RADAR_work/build24.log</code></li> 478 <li>TCL script: <code>~/PLFM_RADAR_work/vivado_project/build24_cfar.tcl</code></li> 479 </ul> 480 <p class="muted">Note: TCL crashed at step 13/15 (<code>extract_files</code> missing parameter) after all reports were generated. Non-critical scripting bug; all implementation, optimization, and bitstream generation completed successfully.</p> 481 </section> 482 483 <section class="card" style="margin-top:0.8rem;"> 484 <h2>Board-day artifact inventory</h2> 485 <div class="table-wrap"> 486 <table> 487 <thead> 488 <tr> 489 <th>Artifact</th> 490 <th>Source path</th> 491 <th>Day-0 use</th> 492 <th>Status / note</th> 493 </tr> 494 </thead> 495 <tbody> 496 <tr><td>Production-target XDC</td><td><code>9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc</code></td><td>Constraint source of truth for the production FPGA target</td><td>Tracked and validated after Build 16 cleanup port</td></tr> 497 <tr><td>FPGA programming flow</td><td><code>9_Firmware/9_2_FPGA/scripts/program_fpga.tcl</code></td><td>Programs the device and reports DONE / INIT_COMPLETE / probes presence</td><td>Primary operator-facing programming script</td></tr> 498 <tr><td>Debug probe insertion flow</td><td><code>9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl</code></td><td>Used when generating or refreshing debug-capable images</td><td>Keep matched with the selected debug bitstream</td></tr> 499 <tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>23 / 23 passing on the current tracked branch (includes CFAR + MTI + E2E tests)</td></tr> 500 <tr><td>MCU regression harness</td><td><code>9_Firmware/9_1_Microcontroller/tests/Makefile</code></td><td>Pre-arrival firmware regression evidence before flashing hardware</td><td>20 / 20 passing on the current tracked branch</td></tr> 501 <tr><td>Bring-up logging macros</td><td><code>9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h</code></td><td>Defines the main first-power-on log vocabulary used over USART3</td><td>Observation-only instrumentation layer</td></tr> 502 <tr><td>Board-day worksheet</td><td><code>docs/board-day-worksheet.html</code></td><td>Record pass/fail, measurements, and blockers during first sessions</td><td>Use with this page and the bring-up plan</td></tr> 503 <tr><td>Bring-up execution plan</td><td><code>docs/bring-up.html</code></td><td>Operator checklist, abort criteria, observability targets, and open risks</td><td>Primary readiness document</td></tr> 504 </tbody> 505 </table> 506 </div> 507 </section> 508 509 <section class="grid-2" style="margin-top:0.8rem;"> 510 <article class="card"> 511 <h2>Antenna Simulation Report</h2> 512 <p><span class="chip">Status: Mostly current (historical Phase-0 context)</span></p> 513 <p class="muted">File: <code>AERIS_Antenna_Report.pdf</code></p> 514 <p class="muted">Notes: Valid for 10.5 GHz patch-element simulation and array projection context. Treat as element-level evidence, not full current hardware bring-up sign-off.</p> 515 <p> 516 <a class="button" href="AERIS_Antenna_Report.pdf" target="_blank" rel="noopener">Open PDF</a> 517 <a class="button ghost" href="AERIS_Antenna_Report.pdf" download>Download</a> 518 </p> 519 </article> 520 <article class="card"> 521 <h2>Python Simulation Report</h2> 522 <p><span class="chip">Status: Legacy (needs refresh)</span></p> 523 <p class="muted">File: <code>AERIS_Simulation_Report.pdf</code></p> 524 <p class="muted">Notes: Contains older architecture assumptions (e.g., XC7A100T-centric narrative). Use as historical reference only until Simulation Report v2 is published.</p> 525 <p> 526 <a class="button" href="AERIS_Simulation_Report.pdf" target="_blank" rel="noopener">Open PDF</a> 527 <a class="button ghost" href="AERIS_Simulation_Report.pdf" download>Download</a> 528 </p> 529 </article> 530 </section> 531 532 <section class="card" style="margin-top:0.8rem;"> 533 <h2>FPGA implementation analysis</h2> 534 <p><span class="chip">Status: Current engineering baseline — Build 25 (MTI + DC notch)</span></p> 535 <p class="muted">Build 25 is the current production baseline. Includes MTI canceller (2-pulse clutter cancellation) and DC notch filter on top of CA-CFAR detector. Full 15-point report above. WNS +0.132 ns, WHS +0.058 ns. DSP count 142 (unchanged). BRAM 17 (unchanged). LUTs 9,252 (+694 from Build 24). FFs 12,488 (+2,104). Power 0.753 W (unchanged).</p> 536 <p class="muted">Build 24 (v0.1.5-cfar) integrated CA-CFAR with pipelined noise computation. Build 23 failed timing (WNS -0.309 ns) due to combinational critical path — fixed by pipelining.</p> 537 <p class="muted">Build 21 (v0.1.4-build21) retained as pre-CFAR reference. Build 20 (v0.1.3-build20) and earlier retained for historical reference.</p> 538 </section> 539 540 <section class="card" style="margin-top:0.8rem;"> 541 <h2>Latest Simulation Report (Recommended)</h2> 542 <p><span class="chip">Status: Current baseline (v2)</span></p> 543 <p class="muted">File: <code>AERIS_Simulation_Report_v2.pdf</code></p> 544 <p class="muted">Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.</p> 545 <p> 546 <a class="button" href="AERIS_Simulation_Report_v2.pdf" target="_blank" rel="noopener">Open PDF</a> 547 <a class="button ghost" href="AERIS_Simulation_Report_v2.pdf" download>Download</a> 548 </p> 549 </section> 550 551 <section class="card" style="margin-top:0.8rem;"> 552 <h2>Report Currency Notice</h2> 553 <ul> 554 <li>The current routed production-target baseline is <strong>Build 25</strong> with all timing constraints met. WNS +0.132 ns, WHS +0.058 ns, 142 DSP48E1, 17 BRAM, 0.753 W.</li> 555 <li>All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes (Build 24). MTI canceller + DC notch filter added in Build 25. Gaps 2–7 were closed prior to Build 21.</li> 556 <li>FPGA regression: 23/23 pass (includes CFAR + MTI + E2E tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).</li> 557 <li>MTI integration cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSPs. Backward-compatible: <code>host_mti_enable</code> and <code>host_dc_notch_width</code> default to disabled/off.</li> 558 <li>Detailed Build 25 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build25/</code>.</li> 559 <li>The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.</li> 560 </ul> 561 </section> 562 563 <section class="card" style="margin-top:0.8rem;"> 564 <h2>Antenna concept snapshot</h2> 565 <img class="diagram" src="assets/img/Antenna_Array.jpg" alt="Antenna array concept"> 566 </section> 567 </main> 568 569 <footer class="footer"> 570 <div class="container"><p>Add future report artifacts here to keep public references stable.</p></div> 571 </footer> 572 </body> 573 </html>