1  #ifndef _DRAGONMINT_T1_
  2  #define _DRAGONMINT_T1_
  3  
  4  #include "stdint.h"
  5  #include "stdbool.h"
  6  
  7  #include "util.h"
  8  #include "elist.h"
  9  
 10  #include "dm_compat.h"
 11  
 12  #define MAX_CHIP_NUM						(68)
 13  #define MAX_CHAIN_NUM						(3)
 14  #define MAX_CORE_NUM						(32)
 15  
 16  #define MAX_CORES						(MAX_CHIP_NUM * MAX_CORE_NUM)
 17  #define MAX_CMD_LENGTH						(JOB_LENGTH + MAX_CHIP_NUM * 2 * 2)
 18  
 19  #define CMD_TYPE_T1						(0x0)
 20  
 21  #define JOB_LENGTH						(162)
 22  #define NONCE_LEN						(6)
 23  
 24  #define T1_PLL_LV_NUM                  	(324)
 25  #define T1_PLL_SETSPI					(310)
 26  #define T1_PLL_SETVID					(1000)
 27  
 28  #define T1_SPI_SPEED_DEF				SPI_SPEED_390K
 29  
 30  #define STARTUP_VID						(0)
 31  #define DEFAULT_PLL						(1332)
 32  #define MIN_PLL							(1200)
 33  #define MAX_PLL							(1392)
 34  
 35  #define DEFAULT_VOLT						(404)
 36  #define TUNE_VOLT_START_EFF					(410)
 37  #define TUNE_VOLT_START_BAL					(415)
 38  #define TUNE_VOLT_START_PER					(420)
 39  
 40  #define TUNE_VOLT_STOP						(390)
 41  #define CHIP_VOLT_MAX						(445)
 42  #define CHIP_VOLT_MIN						(380)
 43  
 44  #define USE_BISTMASK
 45  //#define USE_AUTONONCE
 46  #define USE_AUTOCMD0A
 47  
 48  #define WEAK_CHIP_THRESHOLD 5
 49  #define BROKEN_CHIP_THRESHOLD 5
 50  
 51  #define DRAGONMINT_MINER_TYPE_FILE				"/tmp/type"
 52  #define DRAGONMINT_HARDWARE_VERSION_FILE			"/tmp/hwver"
 53  #define DRAGONMINT_CHIP_NUM_FILE				"/tmp/chip_nums"
 54  #define MINER_AGEING_STATUS_FILE				"/tmp/ageingStatus"
 55  
 56  #define T1_PLL(prediv,fbdiv,postdiv) ((prediv<<(89-64))|fbdiv<<(80-64)|0b010<<(77-64)|postdiv<<(70-64))
 57  
 58  #define T1_PLL_MIN						(0)	// 120 MHz
 59  #define T1_PLL_TUNE_MIN						(290)	// 1200 MHz
 60  #define T1_PLL_TUNE_MAX						(323)	// 1596 MHz
 61  #define T1_PLL_MAX						(323)	// 1596 MHz
 62  
 63  #define T1_PLL_TUNE_RANGE					(T1_PLL_TUNE_MAX - T1_PLL_TUNE_MIN + 1)
 64  
 65  /* Low iVid corresponds with high voltage */
 66  #define T1_VID_MIN						(0)
 67  #define T1_VID_MAX						(31)
 68  
 69  #define T1_VID_TUNE_RANGE					(T1_VID_MAX - T1_VID_MIN + 1)
 70  
 71  #define T1_CYCLES_CHAIN						(666)
 72  
 73  typedef enum {
 74  	HARDWARE_VERSION_NONE = 0x00,
 75  	HARDWARE_VERSION_G9 = 0x09,
 76  	HARDWARE_VERSION_G19 = 0x13,
 77  } hardware_version_e;
 78  
 79  typedef enum {
 80  	AGEING_BIST_START_FAILED = 1,
 81  	AGEING_BIST_FIX_FAILED,
 82  	AGEING_CONFIG_PLL_FAILED,
 83  	AGEING_PLUG_STATUS_ERROR,
 84  	AGEING_SPI_STATUS_ERROR,
 85  	AGEING_RUNNING_CONNECT_POOL_FAILED,
 86  	AGEING_INIT_CONNECT_POOL_FAILED,
 87  	AGEING_ALL_SPI_STATUS_ERROR,
 88  	AGEING_HW_VERSION_ERROR,
 89  	AGEING_TEMP_IS_OVERHEAT,
 90  	AGEING_STATUS_MAX,
 91  } MINER_AGEING_STATUS;
 92  
 93  typedef struct {
 94  	double highest_vol[MAX_CHAIN_NUM];    /* chip temp bits */;
 95  	double lowest_vol[MAX_CHAIN_NUM];    /* chip temp bits */;
 96  	double average_vol[MAX_CHAIN_NUM];    /* chip temp bits */;
 97  	int stat_val[MAX_CHAIN_NUM][MAX_CHIP_NUM];
 98  	int stat_cnt[MAX_CHAIN_NUM][MAX_CHIP_NUM];
 99  } dragonmint_reg_ctrl_t;
100  
101  struct work_ent {
102  	struct work *work;
103  	struct list_head head;
104  };
105  
106  struct work_queue {
107  	int num_elems;
108  	struct list_head head;
109  };
110  
111  struct T1_chip {
112  	uint8_t reg[REG_LENGTH];
113  	int num_cores;
114  	int last_queued_id;
115  	struct work *work[4];
116  	/* stats */
117  	int hw_errors;
118  	int stales;
119  	int dupes;
120  	int nonces_found;
121  	int nonce_ranges_done;
122  
123  	/* systime in ms when chip was disabled */
124  	int cooldown_begin;
125  	/* number of consecutive failures to access the chip */
126  	int fail_count;
127  	int fail_reset;
128  	/* mark chip disabled, do not try to re-enable it */
129  	bool disabled;
130  
131  	int temp;
132  	int nVol;
133  
134  	uint32_t last_nonce;
135  };
136  
137  struct T1_chain {
138  	int chain_id;
139  	struct cgpu_info *cgpu;
140  	int num_chips;
141  	int num_cores;
142  	int num_active_chips;
143  	int chain_skew;
144  	struct spi_ctx *spi_ctx;
145  	struct T1_chip *chips;
146  
147  	pthread_mutex_t lock;
148  	pthread_cond_t cond;
149  
150  	struct work_queue active_wq;
151  
152  	/* mark chain disabled, do not try to re-enable it */
153  	bool disabled;
154  	bool throttle; /* Needs throttling */
155  
156  	struct timeval cycle_start;
157  
158  	int cycles; /* Cycles used for iVid tuning */
159  	int hw_errors;
160  
161  	int pll; /* Current chain speed */
162  	int base_pll; /* Initial chain speed */
163  
164  	int iVid; /* Current actual iVid */
165  	int base_iVid; /* Initial iVid */
166  	int optimalVid; /* Vid after last tune */
167  	int optimal_vol; /* Optimal voltage found after VID tuning */
168  
169  	double vidproduct[T1_VID_TUNE_RANGE]; // Hashrate product vs vid level
170  	double vidhwerr[T1_VID_TUNE_RANGE]; // hwerr vs vid level
171  	/* Double may give more precision than int since it's an average voltage */
172  	double vidvol[T1_VID_TUNE_RANGE]; // What the voltage is per vid level
173  
174  	double pllproduct[T1_PLL_TUNE_RANGE]; // Hashrate product vs pll level
175  	double pllhwerr[T1_PLL_TUNE_RANGE]; // hwerr vs pll level
176  	int pllvid[T1_PLL_TUNE_RANGE]; // Associated VID per pll
177  
178  	bool VidOptimal; // We've stopped tuning voltage
179  	bool pllOptimal; // We've stopped tuning frequency
180  	bool sampling; // Results are valid for tuning
181  
182  	time_t throttled; // Currently throttled time for heat
183  	time_t lastshare;
184  
185  	cgtimer_t cgt; /* Main work loop reentrant timer */
186  };
187  
188  struct PLL_Clock {
189  	uint32_t num;   // divider 1000
190  	uint32_t speedMHz;      // unit MHz
191  	uint32_t pll_reg;
192  };
193  
194  struct T1_config_options {
195  	int ref_clk_khz;
196  	int sys_clk_khz;
197  	int spi_clk_khz;
198  	/* limit chip chain to this number of chips (testing only) */
199  	int override_chip_num;
200  	int wiper;
201  };
202  
203  unsigned short CRC16_2(unsigned char* pchMsg, unsigned short wDataLen);
204  void hexdump_error(char *prefix, uint8_t *buff, int len);
205  void hexdump(char *prefix, uint8_t *buff, int len);
206  
207  bool dm_cmd_resetall(uint8_t chain_id, uint8_t chip_id, uint8_t *result);
208  bool dm_cmd_resetjob(uint8_t chain_id, uint8_t chip_id, uint8_t *result);
209  bool dm_cmd_resetbist(uint8_t chain_id, uint8_t chip_id, uint8_t *result);
210  
211  bool dragonmint_check_voltage(struct T1_chain *t1, int chip_id, dragonmint_reg_ctrl_t *s_reg_ctrl);
212  
213  bool check_chip(struct T1_chain *t1, int i);
214  bool abort_work(struct T1_chain *t1);
215  
216  int get_current_ms(void);
217  bool is_chip_disabled(struct T1_chain *t1, uint8_t chip_id);
218  void disable_chip(struct T1_chain *t1, uint8_t chip_id);
219  
220  bool get_nonce(struct T1_chain *t1, uint8_t *nonce, uint8_t *chip_id, uint8_t *job_id, uint8_t *micro_job_id);
221  bool set_work(struct T1_chain *t1, uint8_t chip_id, struct work *work, uint8_t queue_states);
222  uint8_t *create_job(uint8_t chip_id, uint8_t job_id, struct work *work);
223  void test_bench_pll_config(struct T1_chain *t1,uint32_t uiPll);
224  
225  hardware_version_e dragonmint_get_hwver(void);
226  //dragonmint_type_e dragonmint_get_miner_type(void);
227  uint32_t dragonmint_get_chipnum(void);
228  
229  void chain_all_exit(void);
230  void power_down_all_chain(void);
231  void write_miner_ageing_status(uint32_t statusCode);
232  int dragonmint_get_voltage_stats(struct T1_chain *t1, dragonmint_reg_ctrl_t *s_reg_ctrl);
233  
234  bool t1_set_pll(struct T1_chain *t1, int chip_id, int target_pll);
235  
236  bool T1_SetT1PLLClock(struct T1_chain *t1,int pllClkIdx, int chip_id);
237  int T1_ConfigT1PLLClock(uint32_t optPll);
238  
239  extern const struct PLL_Clock PLL_Clk_12Mhz[T1_PLL_LV_NUM];
240  extern const uint8_t default_reg[T1_PLL_LV_NUM][REG_LENGTH];
241  
242  #endif
243