/ driver-avalon.c
driver-avalon.c
1 /* 2 * Copyright 2013-2015 Con Kolivas <kernel@kolivas.org> 3 * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com> 4 * Copyright 2012 Luke Dashjr 5 * Copyright 2012 Andrew Smith 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 3 of the License, or (at your option) 10 * any later version. See COPYING for more details. 11 */ 12 13 #include "config.h" 14 15 #include <limits.h> 16 #include <pthread.h> 17 #include <stdio.h> 18 #include <sys/time.h> 19 #include <sys/types.h> 20 #include <ctype.h> 21 #include <dirent.h> 22 #include <unistd.h> 23 #include <time.h> 24 #ifndef WIN32 25 #include <sys/select.h> 26 #include <termios.h> 27 #include <sys/stat.h> 28 #include <fcntl.h> 29 #ifndef O_CLOEXEC 30 #define O_CLOEXEC 0 31 #endif 32 #else 33 #include "compat.h" 34 #include <io.h> 35 #endif 36 37 #include "elist.h" 38 #include "miner.h" 39 #include "usbutils.h" 40 #include "driver-avalon.h" 41 #include "hexdump.c" 42 #include "util.h" 43 44 int opt_avalon_temp = AVALON_TEMP_TARGET; 45 int opt_avalon_overheat = AVALON_TEMP_OVERHEAT; 46 int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM; 47 int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM; 48 int opt_avalon_freq_min = AVALON_MIN_FREQUENCY; 49 int opt_avalon_freq_max = AVALON_MAX_FREQUENCY; 50 int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE; 51 int opt_bitburner_fury_core_voltage = BITBURNER_FURY_DEFAULT_CORE_VOLTAGE; 52 bool opt_avalon_auto; 53 54 static int option_offset = -1; 55 static int bbf_option_offset = -1; 56 57 static int avalon_init_task(struct avalon_task *at, 58 uint8_t reset, uint8_t ff, uint8_t fan, 59 uint8_t timeout, uint8_t asic_num, 60 uint8_t miner_num, uint8_t nonce_elf, 61 uint8_t gate_miner, int frequency, int asic) 62 { 63 uint16_t *lefreq16; 64 uint8_t *buf; 65 static bool first = true; 66 67 if (unlikely(!at)) 68 return -1; 69 70 if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0)) 71 return -1; 72 73 memset(at, 0, sizeof(struct avalon_task)); 74 75 if (unlikely(reset)) { 76 at->reset = 1; 77 at->fan_eft = 1; 78 at->timer_eft = 1; 79 first = true; 80 } 81 82 at->flush_fifo = (ff ? 1 : 0); 83 at->fan_eft = (fan ? 1 : 0); 84 85 if (unlikely(first && !at->reset)) { 86 at->fan_eft = 1; 87 at->timer_eft = 1; 88 first = false; 89 } 90 91 at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM); 92 at->timeout_data = timeout; 93 at->asic_num = asic_num; 94 at->miner_num = miner_num; 95 at->nonce_elf = nonce_elf; 96 97 at->gate_miner_elf = 1; 98 at->asic_pll = 1; 99 100 if (unlikely(gate_miner)) { 101 at-> gate_miner = 1; 102 at->asic_pll = 0; 103 } 104 105 buf = (uint8_t *)at; 106 buf[5] = 0x00; 107 buf[8] = 0x74; 108 buf[9] = 0x01; 109 buf[10] = 0x00; 110 buf[11] = 0x00; 111 112 /* With 55nm, this is the real clock in Mhz, 1Mhz means 2Mhs */ 113 lefreq16 = (uint16_t *)&buf[6]; 114 if (asic == AVALON_A3256) 115 frequency *= 8; 116 else 117 frequency = frequency * 32 / 50 + 0x7FE0; 118 *lefreq16 = htole16(frequency); 119 120 return 0; 121 } 122 123 static inline void avalon_create_task(struct avalon_task *at, 124 struct work *work) 125 { 126 memcpy(at->midstate, work->midstate, 32); 127 memcpy(at->data, work->data + 64, 12); 128 } 129 130 static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep) 131 { 132 int err, amount; 133 134 err = usb_write(avalon, buf, len, &amount, ep); 135 applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name, 136 avalon->device_id, err); 137 138 if (unlikely(err != 0)) { 139 applog(LOG_WARNING, "usb_write error on avalon_write"); 140 return AVA_SEND_ERROR; 141 } 142 if (amount != len) { 143 applog(LOG_WARNING, "usb_write length mismatch on avalon_write"); 144 return AVA_SEND_ERROR; 145 } 146 147 return AVA_SEND_OK; 148 } 149 150 static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon, 151 struct avalon_info *info) 152 153 { 154 uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM]; 155 int delay, ret, i, ep = C_AVALON_TASK; 156 uint32_t nonce_range; 157 size_t nr_len; 158 159 if (at->nonce_elf) 160 nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num; 161 else 162 nr_len = AVALON_WRITE_SIZE; 163 164 memcpy(buf, at, AVALON_WRITE_SIZE); 165 166 if (at->nonce_elf) { 167 nonce_range = (uint32_t)0xffffffff / at->asic_num; 168 for (i = 0; i < at->asic_num; i++) { 169 buf[AVALON_WRITE_SIZE + (i * 4) + 3] = 170 (i * nonce_range & 0xff000000) >> 24; 171 buf[AVALON_WRITE_SIZE + (i * 4) + 2] = 172 (i * nonce_range & 0x00ff0000) >> 16; 173 buf[AVALON_WRITE_SIZE + (i * 4) + 1] = 174 (i * nonce_range & 0x0000ff00) >> 8; 175 buf[AVALON_WRITE_SIZE + (i * 4) + 0] = 176 (i * nonce_range & 0x000000ff) >> 0; 177 } 178 } 179 #if defined(__BIG_ENDIAN__) || defined(MIPSEB) 180 uint8_t tt = 0; 181 182 tt = (buf[0] & 0x0f) << 4; 183 tt |= ((buf[0] & 0x10) ? (1 << 3) : 0); 184 tt |= ((buf[0] & 0x20) ? (1 << 2) : 0); 185 tt |= ((buf[0] & 0x40) ? (1 << 1) : 0); 186 tt |= ((buf[0] & 0x80) ? (1 << 0) : 0); 187 buf[0] = tt; 188 189 tt = (buf[4] & 0x0f) << 4; 190 tt |= ((buf[4] & 0x10) ? (1 << 3) : 0); 191 tt |= ((buf[4] & 0x20) ? (1 << 2) : 0); 192 tt |= ((buf[4] & 0x40) ? (1 << 1) : 0); 193 tt |= ((buf[4] & 0x80) ? (1 << 0) : 0); 194 buf[4] = tt; 195 #endif 196 delay = nr_len * 10 * 1000000; 197 delay = delay / info->baud; 198 delay += 4000; 199 200 if (at->reset) { 201 ep = C_AVALON_RESET; 202 nr_len = 1; 203 } 204 if (opt_debug) { 205 applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len); 206 hexdump(buf, nr_len); 207 } 208 /* Sleep from the last time we sent data */ 209 cgsleep_us_r(&info->cgsent, info->send_delay); 210 211 cgsleep_prepare_r(&info->cgsent); 212 ret = avalon_write(avalon, (char *)buf, nr_len, ep); 213 214 applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", info->send_delay); 215 info->send_delay = delay; 216 217 return ret; 218 } 219 220 static int bitburner_send_task(const struct avalon_task *at, struct cgpu_info *avalon) 221 222 { 223 uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM]; 224 int ret, ep = C_AVALON_TASK; 225 cgtimer_t ts_start; 226 size_t nr_len; 227 228 if (at->nonce_elf) 229 nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num; 230 else 231 nr_len = AVALON_WRITE_SIZE; 232 233 memset(buf, 0, nr_len); 234 memcpy(buf, at, AVALON_WRITE_SIZE); 235 236 #if defined(__BIG_ENDIAN__) || defined(MIPSEB) 237 uint8_t tt = 0; 238 239 tt = (buf[0] & 0x0f) << 4; 240 tt |= ((buf[0] & 0x10) ? (1 << 3) : 0); 241 tt |= ((buf[0] & 0x20) ? (1 << 2) : 0); 242 tt |= ((buf[0] & 0x40) ? (1 << 1) : 0); 243 tt |= ((buf[0] & 0x80) ? (1 << 0) : 0); 244 buf[0] = tt; 245 246 tt = (buf[4] & 0x0f) << 4; 247 tt |= ((buf[4] & 0x10) ? (1 << 3) : 0); 248 tt |= ((buf[4] & 0x20) ? (1 << 2) : 0); 249 tt |= ((buf[4] & 0x40) ? (1 << 1) : 0); 250 tt |= ((buf[4] & 0x80) ? (1 << 0) : 0); 251 buf[4] = tt; 252 #endif 253 254 if (at->reset) { 255 ep = C_AVALON_RESET; 256 nr_len = 1; 257 } 258 if (opt_debug) { 259 applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len); 260 hexdump(buf, nr_len); 261 } 262 cgsleep_prepare_r(&ts_start); 263 ret = avalon_write(avalon, (char *)buf, nr_len, ep); 264 cgsleep_us_r(&ts_start, 3000); // 3 ms = 333 tasks per second, or 1.4 TH/s 265 266 return ret; 267 } 268 269 static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon, 270 struct avalon_info *info, struct avalon_result *ar, 271 struct work *work) 272 { 273 uint32_t nonce; 274 275 info = avalon->device_data; 276 info->matching_work[work->subid]++; 277 nonce = htole32(ar->nonce); 278 if (info->asic == AVALON_A3255) 279 nonce -= 0xc0; 280 applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce); 281 return submit_nonce(thr, work, nonce); 282 } 283 284 /* Wait until the ftdi chip returns a CTS saying we can send more data. */ 285 static void wait_avalon_ready(struct cgpu_info *avalon) 286 { 287 while (avalon_buffer_full(avalon)) { 288 cgsleep_ms(40); 289 } 290 } 291 292 static int avalon_read(struct cgpu_info *avalon, char *buf, size_t bufsize, int ep) 293 { 294 size_t total = 0, readsize = bufsize + 2; 295 char readbuf[AVALON_READBUF_SIZE]; 296 int err, amount, ofs = 2, cp; 297 298 err = usb_read_once(avalon, readbuf, readsize, &amount, ep); 299 applog(LOG_DEBUG, "%s%i: Get avalon read got err %d", 300 avalon->drv->name, avalon->device_id, err); 301 if (err && err != LIBUSB_ERROR_TIMEOUT) 302 return err; 303 304 if (amount < 2) 305 goto out; 306 307 /* The first 2 of every 64 bytes are status on FTDIRL */ 308 while (amount > 2) { 309 cp = amount - 2; 310 if (cp > 62) 311 cp = 62; 312 memcpy(&buf[total], &readbuf[ofs], cp); 313 total += cp; 314 amount -= cp + 2; 315 ofs += 64; 316 } 317 out: 318 return total; 319 } 320 321 static int avalon_reset(struct cgpu_info *avalon, bool initial) 322 { 323 struct avalon_result ar; 324 int ret, i, spare; 325 struct avalon_task at; 326 uint8_t *buf, *tmp; 327 struct timespec p; 328 struct avalon_info *info = avalon->device_data; 329 330 /* Send reset, then check for result */ 331 avalon_init_task(&at, 1, 0, 332 AVALON_DEFAULT_FAN_MAX_PWM, 333 AVALON_DEFAULT_TIMEOUT, 334 AVALON_DEFAULT_ASIC_NUM, 335 AVALON_DEFAULT_MINER_NUM, 336 0, 0, 337 AVALON_DEFAULT_FREQUENCY, 338 AVALON_A3256); 339 340 wait_avalon_ready(avalon); 341 ret = avalon_send_task(&at, avalon, info); 342 if (unlikely(ret == AVA_SEND_ERROR)) 343 return -1; 344 345 if (!initial) { 346 applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id); 347 return 0; 348 } 349 350 ret = avalon_read(avalon, (char *)&ar, AVALON_READ_SIZE, C_GET_AVALON_RESET); 351 352 /* What do these sleeps do?? */ 353 p.tv_sec = 0; 354 p.tv_nsec = AVALON_RESET_PITCH; 355 nanosleep(&p, NULL); 356 357 /* Look for the first occurrence of 0xAA, the reset response should be: 358 * AA 55 AA 55 00 00 00 00 00 00 */ 359 spare = ret - 10; 360 buf = tmp = (uint8_t *)&ar; 361 if (opt_debug) { 362 applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id); 363 hexdump(tmp, AVALON_READ_SIZE); 364 } 365 366 for (i = 0; i <= spare; i++) { 367 buf = &tmp[i]; 368 if (buf[0] == 0xAA) 369 break; 370 } 371 i = 0; 372 373 if (buf[0] == 0xAA && buf[1] == 0x55 && 374 buf[2] == 0xAA && buf[3] == 0x55) { 375 for (i = 4; i < 11; i++) 376 if (buf[i] != 0) 377 break; 378 } 379 380 if (i != 11) { 381 applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?" 382 " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id, 383 i, buf[0], buf[1], buf[2], buf[3]); 384 /* FIXME: return 1; */ 385 } else { 386 /* buf[44]: minor 387 * buf[45]: day 388 * buf[46]: year,month, d6: 201306 389 */ 390 info->ctlr_ver = ((buf[46] >> 4) + 2000) * 1000000 + 391 (buf[46] & 0x0f) * 10000 + 392 buf[45] * 100 + buf[44]; 393 applog(LOG_WARNING, "%s%d: Reset succeeded (Controller version: %d)", 394 avalon->drv->name, avalon->device_id, info->ctlr_ver); 395 } 396 397 return 0; 398 } 399 400 static int avalon_calc_timeout(int frequency) 401 { 402 return AVALON_TIMEOUT_FACTOR / frequency; 403 } 404 405 static bool get_options(int this_option_offset, int *baud, int *miner_count, 406 int *asic_count, int *timeout, int *frequency, int *asic, 407 char *options) 408 { 409 char buf[BUFSIZ+1]; 410 char *ptr, *comma, *colon, *colon2, *colon3, *colon4, *colon5; 411 bool timeout_default; 412 size_t max; 413 int i, tmp; 414 415 if (options == NULL) 416 buf[0] = '\0'; 417 else { 418 ptr = options; 419 for (i = 0; i < this_option_offset; i++) { 420 comma = strchr(ptr, ','); 421 if (comma == NULL) 422 break; 423 ptr = comma + 1; 424 } 425 426 comma = strchr(ptr, ','); 427 if (comma == NULL) 428 max = strlen(ptr); 429 else 430 max = comma - ptr; 431 432 if (max > BUFSIZ) 433 max = BUFSIZ; 434 strncpy(buf, ptr, max); 435 buf[max] = '\0'; 436 } 437 438 if (!(*buf)) 439 return false; 440 441 colon = strchr(buf, ':'); 442 if (colon) 443 *(colon++) = '\0'; 444 445 tmp = atoi(buf); 446 switch (tmp) { 447 case 115200: 448 *baud = 115200; 449 break; 450 case 57600: 451 *baud = 57600; 452 break; 453 case 38400: 454 *baud = 38400; 455 break; 456 case 19200: 457 *baud = 19200; 458 break; 459 default: 460 quit(1, "Invalid avalon-options for baud (%s) " 461 "must be 115200, 57600, 38400 or 19200", buf); 462 } 463 464 if (colon && *colon) { 465 colon2 = strchr(colon, ':'); 466 if (colon2) 467 *(colon2++) = '\0'; 468 469 if (*colon) { 470 tmp = atoi(colon); 471 if (tmp > 0 && tmp <= AVALON_MAX_MINER_NUM) { 472 *miner_count = tmp; 473 } else { 474 quit(1, "Invalid avalon-options for " 475 "miner_count (%s) must be 1 ~ %d", 476 colon, AVALON_MAX_MINER_NUM); 477 } 478 } 479 480 if (colon2 && *colon2) { 481 colon3 = strchr(colon2, ':'); 482 if (colon3) 483 *(colon3++) = '\0'; 484 485 tmp = atoi(colon2); 486 if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM) 487 *asic_count = tmp; 488 else { 489 quit(1, "Invalid avalon-options for " 490 "asic_count (%s) must be 1 ~ %d", 491 colon2, AVALON_DEFAULT_ASIC_NUM); 492 } 493 494 timeout_default = false; 495 if (colon3 && *colon3) { 496 colon4 = strchr(colon3, ':'); 497 if (colon4) 498 *(colon4++) = '\0'; 499 500 if (tolower(*colon3) == 'd') 501 timeout_default = true; 502 else { 503 tmp = atoi(colon3); 504 if (tmp > 0 && tmp <= 0xff) 505 *timeout = tmp; 506 else { 507 quit(1, "Invalid avalon-options for " 508 "timeout (%s) must be 1 ~ %d", 509 colon3, 0xff); 510 } 511 } 512 if (colon4 && *colon4) { 513 colon5 = strchr(colon4, ':'); 514 if (colon5) 515 *(colon5++) = '\0'; 516 517 tmp = atoi(colon4); 518 if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) { 519 quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d", 520 AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY); 521 } 522 *frequency = tmp; 523 if (timeout_default) 524 *timeout = avalon_calc_timeout(*frequency); 525 if (colon5 && *colon5) { 526 tmp = atoi(colon5); 527 if (tmp != AVALON_A3256 && tmp != AVALON_A3255) 528 quit(1, "Invalid avalon-options for asic, must be 110 or 55"); 529 *asic = tmp; 530 } 531 } 532 } 533 } 534 } 535 return true; 536 } 537 538 char *set_avalon_fan(char *arg) 539 { 540 int val1, val2, ret; 541 542 ret = sscanf(arg, "%d-%d", &val1, &val2); 543 if (ret < 1) 544 return "No values passed to avalon-fan"; 545 if (ret == 1) 546 val2 = val1; 547 548 if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1) 549 return "Invalid value passed to avalon-fan"; 550 551 opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100; 552 opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100; 553 554 return NULL; 555 } 556 557 char *set_avalon_freq(char *arg) 558 { 559 int val1, val2, ret; 560 561 ret = sscanf(arg, "%d-%d", &val1, &val2); 562 if (ret < 1) 563 return "No values passed to avalon-freq"; 564 if (ret == 1) 565 val2 = val1; 566 567 if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY || 568 val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY || 569 val2 < val1) 570 return "Invalid value passed to avalon-freq"; 571 572 opt_avalon_freq_min = val1; 573 opt_avalon_freq_max = val2; 574 575 return NULL; 576 } 577 578 static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info) 579 { 580 int i; 581 582 wait_avalon_ready(avalon); 583 /* Send idle to all miners */ 584 for (i = 0; i < info->miner_count; i++) { 585 struct avalon_task at; 586 587 if (unlikely(avalon_buffer_full(avalon))) 588 break; 589 info->idle++; 590 avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout, 591 info->asic_count, info->miner_count, 1, 1, 592 info->frequency, info->asic); 593 if (avalon_send_task(&at, avalon, info) == AVA_SEND_ERROR) 594 break; 595 } 596 applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i); 597 wait_avalon_ready(avalon); 598 } 599 600 static void avalon_initialise(struct cgpu_info *avalon) 601 { 602 int err, interface; 603 604 if (avalon->usbinfo.nodev) 605 return; 606 607 interface = usb_interface(avalon); 608 // Reset 609 err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET, 610 FTDI_VALUE_RESET, interface, C_RESET); 611 612 applog(LOG_DEBUG, "%s%i: reset got err %d", 613 avalon->drv->name, avalon->device_id, err); 614 615 if (avalon->usbinfo.nodev) 616 return; 617 618 // Set latency 619 err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY, 620 AVALON_LATENCY, interface, C_LATENCY); 621 622 applog(LOG_DEBUG, "%s%i: latency got err %d", 623 avalon->drv->name, avalon->device_id, err); 624 625 if (avalon->usbinfo.nodev) 626 return; 627 628 // Set data 629 err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA, 630 FTDI_VALUE_DATA_AVA, interface, C_SETDATA); 631 632 applog(LOG_DEBUG, "%s%i: data got err %d", 633 avalon->drv->name, avalon->device_id, err); 634 635 if (avalon->usbinfo.nodev) 636 return; 637 638 // Set the baud 639 err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA, 640 (FTDI_INDEX_BAUD_AVA & 0xff00) | interface, 641 C_SETBAUD); 642 643 applog(LOG_DEBUG, "%s%i: setbaud got err %d", 644 avalon->drv->name, avalon->device_id, err); 645 646 if (avalon->usbinfo.nodev) 647 return; 648 649 // Set Modem Control 650 err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM, 651 FTDI_VALUE_MODEM, interface, C_SETMODEM); 652 653 applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d", 654 avalon->drv->name, avalon->device_id, err); 655 656 if (avalon->usbinfo.nodev) 657 return; 658 659 // Set Flow Control 660 err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW, 661 FTDI_VALUE_FLOW, interface, C_SETFLOW); 662 663 applog(LOG_DEBUG, "%s%i: setflowctrl got err %d", 664 avalon->drv->name, avalon->device_id, err); 665 666 if (avalon->usbinfo.nodev) 667 return; 668 669 /* Avalon repeats the following */ 670 // Set Modem Control 671 err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM, 672 FTDI_VALUE_MODEM, interface, C_SETMODEM); 673 674 applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d", 675 avalon->drv->name, avalon->device_id, err); 676 677 if (avalon->usbinfo.nodev) 678 return; 679 680 // Set Flow Control 681 err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW, 682 FTDI_VALUE_FLOW, interface, C_SETFLOW); 683 684 applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d", 685 avalon->drv->name, avalon->device_id, err); 686 } 687 688 static bool is_bitburner(struct cgpu_info *avalon) 689 { 690 enum sub_ident ident; 691 692 ident = usb_ident(avalon); 693 return ident == IDENT_BTB || ident == IDENT_BBF; 694 } 695 696 static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage) 697 { 698 uint8_t buf[2]; 699 int err; 700 701 if (is_bitburner(avalon)) { 702 buf[0] = (uint8_t)core_voltage; 703 buf[1] = (uint8_t)(core_voltage >> 8); 704 err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST, 705 BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE, 706 (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE); 707 if (unlikely(err < 0)) { 708 applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d", 709 avalon->drv->name, avalon->device_id, err); 710 return false; 711 } else { 712 applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts", 713 avalon->drv->name, avalon->device_id, 714 core_voltage); 715 } 716 return true; 717 } 718 return false; 719 } 720 721 static int bitburner_get_core_voltage(struct cgpu_info *avalon) 722 { 723 uint8_t buf[2]; 724 int err; 725 int amount; 726 727 if (is_bitburner(avalon)) { 728 err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST, 729 BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE, 730 (char *)buf, sizeof(buf), &amount, 731 C_BB_GET_VOLTAGE); 732 if (unlikely(err != 0 || amount != 2)) { 733 applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d", 734 avalon->drv->name, avalon->device_id, err, amount); 735 return 0; 736 } else { 737 return (int)(buf[0] + ((unsigned int)buf[1] << 8)); 738 } 739 } else { 740 return 0; 741 } 742 } 743 744 static void bitburner_get_version(struct cgpu_info *avalon) 745 { 746 struct avalon_info *info = avalon->device_data; 747 uint8_t buf[3]; 748 int err; 749 int amount; 750 751 err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST, 752 BITBURNER_VALUE, BITBURNER_INDEX_GET_VERSION, 753 (char *)buf, sizeof(buf), &amount, 754 C_GETVERSION); 755 if (unlikely(err != 0 || amount != sizeof(buf))) { 756 applog(LOG_DEBUG, "%s%i: GetVersion failed: err=%d, amt=%d assuming %d.%d.%d", 757 avalon->drv->name, avalon->device_id, err, amount, 758 BITBURNER_VERSION1, BITBURNER_VERSION2, BITBURNER_VERSION3); 759 info->version1 = BITBURNER_VERSION1; 760 info->version2 = BITBURNER_VERSION2; 761 info->version3 = BITBURNER_VERSION3; 762 } else { 763 info->version1 = buf[0]; 764 info->version2 = buf[1]; 765 info->version3 = buf[2]; 766 } 767 } 768 769 static struct cgpu_info *avalon_detect_one(libusb_device *dev, struct usb_find_devices *found) 770 { 771 int baud, miner_count, asic_count, timeout, frequency, asic; 772 int this_option_offset; 773 struct avalon_info *info; 774 struct cgpu_info *avalon; 775 bool configured; 776 int ret; 777 778 avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS); 779 780 baud = AVALON_IO_SPEED; 781 miner_count = AVALON_DEFAULT_MINER_NUM; 782 asic_count = AVALON_DEFAULT_ASIC_NUM; 783 timeout = AVALON_DEFAULT_TIMEOUT; 784 frequency = AVALON_DEFAULT_FREQUENCY; 785 asic = AVALON_A3256; 786 787 if (!usb_init(avalon, dev, found)) 788 goto shin; 789 790 this_option_offset = usb_ident(avalon) == IDENT_BBF ? ++bbf_option_offset : ++option_offset; 791 configured = get_options(this_option_offset, &baud, &miner_count, 792 &asic_count, &timeout, &frequency, &asic, 793 (usb_ident(avalon) == IDENT_BBF && opt_bitburner_fury_options != NULL) ? opt_bitburner_fury_options : opt_avalon_options); 794 795 /* Even though this is an FTDI type chip, we want to do the parsing 796 * all ourselves so set it to std usb type */ 797 avalon->usbdev->usb_type = USB_TYPE_STD; 798 799 /* We have a real Avalon! */ 800 avalon_initialise(avalon); 801 802 avalon->device_data = calloc(sizeof(struct avalon_info), 1); 803 if (unlikely(!(avalon->device_data))) 804 quit(1, "Failed to calloc avalon_info data"); 805 info = avalon->device_data; 806 807 if (configured) { 808 info->asic = asic; 809 info->baud = baud; 810 info->miner_count = miner_count; 811 info->asic_count = asic_count; 812 info->timeout = timeout; 813 info->frequency = frequency; 814 } else { 815 info->asic = AVALON_A3256; 816 info->baud = AVALON_IO_SPEED; 817 info->asic_count = AVALON_DEFAULT_ASIC_NUM; 818 switch (usb_ident(avalon)) { 819 case IDENT_BBF: 820 info->miner_count = BITBURNER_FURY_DEFAULT_MINER_NUM; 821 info->timeout = BITBURNER_FURY_DEFAULT_TIMEOUT; 822 info->frequency = BITBURNER_FURY_DEFAULT_FREQUENCY; 823 break; 824 default: 825 info->miner_count = AVALON_DEFAULT_MINER_NUM; 826 info->timeout = AVALON_DEFAULT_TIMEOUT; 827 info->frequency = AVALON_DEFAULT_FREQUENCY; 828 } 829 } 830 if (info->asic == AVALON_A3255) 831 info->increment = info->decrement = 50; 832 else { 833 info->increment = 2; 834 info->decrement = 1; 835 } 836 837 info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM; 838 /* This is for check the temp/fan every 3~4s */ 839 info->temp_history_count = 840 (4 / (float)((float)info->timeout * (AVALON_A3256 / info->asic) * ((float)1.67/0x32))) + 1; 841 if (info->temp_history_count <= 0) 842 info->temp_history_count = 1; 843 844 info->temp_history_index = 0; 845 info->temp_sum = 0; 846 info->temp_old = 0; 847 848 if (!add_cgpu(avalon)) 849 goto unshin; 850 851 ret = avalon_reset(avalon, true); 852 if (ret && !configured) 853 goto unshin; 854 855 update_usb_stats(avalon); 856 857 avalon_idle(avalon, info); 858 859 applog(LOG_DEBUG, "Avalon Detected: %s " 860 "(miner_count=%d asic_count=%d timeout=%d frequency=%d chip=%d)", 861 avalon->device_path, info->miner_count, info->asic_count, info->timeout, 862 info->frequency, info->asic); 863 864 if (usb_ident(avalon) == IDENT_BTB) { 865 if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV || 866 opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) { 867 quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv", 868 opt_bitburner_core_voltage, 869 BITBURNER_MIN_COREMV, 870 BITBURNER_MAX_COREMV); 871 } else 872 bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage); 873 } else if (usb_ident(avalon) == IDENT_BBF) { 874 if (opt_bitburner_fury_core_voltage < BITBURNER_FURY_MIN_COREMV || 875 opt_bitburner_fury_core_voltage > BITBURNER_FURY_MAX_COREMV) { 876 quit(1, "Invalid bitburner-fury-voltage %d must be %dmv - %dmv", 877 opt_bitburner_fury_core_voltage, 878 BITBURNER_FURY_MIN_COREMV, 879 BITBURNER_FURY_MAX_COREMV); 880 } else 881 bitburner_set_core_voltage(avalon, opt_bitburner_fury_core_voltage); 882 } 883 884 if (is_bitburner(avalon)) { 885 bitburner_get_version(avalon); 886 } 887 888 return avalon; 889 890 unshin: 891 892 usb_uninit(avalon); 893 894 shin: 895 896 free(avalon->device_data); 897 avalon->device_data = NULL; 898 899 avalon = usb_free_cgpu(avalon); 900 901 return NULL; 902 } 903 904 static void avalon_detect(bool __maybe_unused hotplug) 905 { 906 usb_detect(&avalon_drv, avalon_detect_one); 907 } 908 909 static void avalon_init(struct cgpu_info *avalon) 910 { 911 applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path); 912 } 913 914 static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar) 915 { 916 return clone_queued_work_bymidstate(avalon, (char *)ar->midstate, 32, 917 (char *)ar->data, 64, 12); 918 } 919 920 static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info, 921 struct avalon_result *ar); 922 923 static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr) 924 { 925 applog(LOG_INFO, "%s%d: No matching work - HW error", 926 thr->cgpu->drv->name, thr->cgpu->device_id); 927 928 inc_hw_errors(thr); 929 info->no_matching_work++; 930 } 931 932 static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info, 933 struct thr_info *thr, char *buf, int *offset) 934 { 935 int i, spare = *offset - AVALON_READ_SIZE; 936 bool found = false; 937 938 for (i = 0; i <= spare; i++) { 939 struct avalon_result *ar; 940 struct work *work; 941 942 ar = (struct avalon_result *)&buf[i]; 943 work = avalon_valid_result(avalon, ar); 944 if (work) { 945 bool gettemp = false; 946 947 found = true; 948 949 if (avalon_decode_nonce(thr, avalon, info, ar, work)) { 950 mutex_lock(&info->lock); 951 if (!info->nonces++) 952 gettemp = true; 953 info->auto_nonces++; 954 mutex_unlock(&info->lock); 955 } else if (opt_avalon_auto) { 956 mutex_lock(&info->lock); 957 info->auto_hw++; 958 mutex_unlock(&info->lock); 959 } 960 free_work(work); 961 962 if (gettemp) 963 avalon_update_temps(avalon, info, ar); 964 break; 965 } 966 } 967 968 if (!found) { 969 spare = *offset - AVALON_READ_SIZE; 970 /* We are buffering and haven't accumulated one more corrupt 971 * work result. */ 972 if (spare < (int)AVALON_READ_SIZE) 973 return; 974 avalon_inc_nvw(info, thr); 975 } else { 976 spare = AVALON_READ_SIZE + i; 977 if (i) { 978 if (i >= (int)AVALON_READ_SIZE) 979 avalon_inc_nvw(info, thr); 980 else 981 applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i); 982 } 983 } 984 985 *offset -= spare; 986 memmove(buf, buf + spare, *offset); 987 } 988 989 static void avalon_running_reset(struct cgpu_info *avalon, 990 struct avalon_info *info) 991 { 992 avalon_reset(avalon, false); 993 avalon_idle(avalon, info); 994 avalon->results = 0; 995 info->reset = false; 996 } 997 998 static void *avalon_get_results(void *userdata) 999 { 1000 struct cgpu_info *avalon = (struct cgpu_info *)userdata; 1001 struct avalon_info *info = avalon->device_data; 1002 const int rsize = AVALON_FTDI_READSIZE; 1003 char readbuf[AVALON_READBUF_SIZE]; 1004 struct thr_info *thr = info->thr; 1005 int offset = 0, ret = 0; 1006 char threadname[16]; 1007 1008 snprintf(threadname, sizeof(threadname), "%d/AvaRecv", avalon->device_id); 1009 RenameThread(threadname); 1010 1011 while (likely(!avalon->shutdown)) { 1012 char buf[rsize]; 1013 1014 if (offset >= (int)AVALON_READ_SIZE) 1015 avalon_parse_results(avalon, info, thr, readbuf, &offset); 1016 1017 if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) { 1018 /* This should never happen */ 1019 applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer"); 1020 offset = 0; 1021 } 1022 1023 if (unlikely(info->reset)) { 1024 avalon_running_reset(avalon, info); 1025 /* Discard anything in the buffer */ 1026 offset = 0; 1027 } 1028 1029 ret = avalon_read(avalon, buf, rsize, C_AVALON_READ); 1030 1031 if (unlikely(ret < 0)) 1032 break; 1033 1034 if (ret < 1) 1035 continue; 1036 1037 if (opt_debug) { 1038 applog(LOG_DEBUG, "Avalon: get:"); 1039 hexdump((uint8_t *)buf, ret); 1040 } 1041 1042 memcpy(&readbuf[offset], &buf, ret); 1043 offset += ret; 1044 } 1045 return NULL; 1046 } 1047 1048 static void avalon_rotate_array(struct cgpu_info *avalon, struct avalon_info *info) 1049 { 1050 mutex_lock(&info->qlock); 1051 avalon->queued = 0; 1052 if (++avalon->work_array >= AVALON_ARRAY_SIZE) 1053 avalon->work_array = 0; 1054 mutex_unlock(&info->qlock); 1055 } 1056 1057 static void bitburner_rotate_array(struct cgpu_info *avalon) 1058 { 1059 avalon->queued = 0; 1060 if (++avalon->work_array >= BITBURNER_ARRAY_SIZE) 1061 avalon->work_array = 0; 1062 } 1063 1064 static void avalon_set_timeout(struct avalon_info *info) 1065 { 1066 info->timeout = avalon_calc_timeout(info->frequency); 1067 } 1068 1069 static void avalon_set_freq(struct cgpu_info *avalon, int frequency) 1070 { 1071 struct avalon_info *info = avalon->device_data; 1072 1073 info->frequency = frequency; 1074 if (info->frequency > opt_avalon_freq_max) 1075 info->frequency = opt_avalon_freq_max; 1076 if (info->frequency < opt_avalon_freq_min) 1077 info->frequency = opt_avalon_freq_min; 1078 avalon_set_timeout(info); 1079 applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d", 1080 avalon->drv->name, avalon->device_id, 1081 info->frequency, info->timeout); 1082 } 1083 1084 static void avalon_inc_freq(struct avalon_info *info) 1085 { 1086 info->frequency += info->increment; 1087 if (info->frequency > opt_avalon_freq_max) 1088 info->frequency = opt_avalon_freq_max; 1089 avalon_set_timeout(info); 1090 applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d", 1091 info->frequency, info->timeout); 1092 } 1093 1094 static void avalon_dec_freq(struct avalon_info *info) 1095 { 1096 info->frequency -= info->decrement; 1097 if (info->frequency < opt_avalon_freq_min) 1098 info->frequency = opt_avalon_freq_min; 1099 avalon_set_timeout(info); 1100 applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d", 1101 info->frequency, info->timeout); 1102 } 1103 1104 static void avalon_reset_auto(struct avalon_info *info) 1105 { 1106 info->auto_queued = 1107 info->auto_nonces = 1108 info->auto_hw = 0; 1109 } 1110 1111 static void avalon_adjust_freq(struct avalon_info *info, struct cgpu_info *avalon) 1112 { 1113 if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) { 1114 mutex_lock(&info->lock); 1115 if (!info->optimal) { 1116 if (info->fan_pwm >= opt_avalon_fan_max) { 1117 applog(LOG_WARNING, 1118 "%s%i: Above optimal temperature, throttling", 1119 avalon->drv->name, avalon->device_id); 1120 avalon_dec_freq(info); 1121 } 1122 } else if (info->auto_nonces >= AVALON_AUTO_CYCLE / 2) { 1123 int total = info->auto_nonces + info->auto_hw; 1124 1125 /* Try to keep hw errors < 2% */ 1126 if (info->auto_hw * 100 < total) 1127 avalon_inc_freq(info); 1128 else if (info->auto_hw * 66 > total) 1129 avalon_dec_freq(info); 1130 } 1131 avalon_reset_auto(info); 1132 mutex_unlock(&info->lock); 1133 } 1134 } 1135 1136 static void *avalon_send_tasks(void *userdata) 1137 { 1138 struct cgpu_info *avalon = (struct cgpu_info *)userdata; 1139 struct avalon_info *info = avalon->device_data; 1140 const int avalon_get_work_count = info->miner_count; 1141 char threadname[16]; 1142 1143 snprintf(threadname, sizeof(threadname), "%d/AvaSend", avalon->device_id); 1144 RenameThread(threadname); 1145 1146 while (likely(!avalon->shutdown)) { 1147 int start_count, end_count, i, j, ret; 1148 cgtimer_t ts_start; 1149 struct avalon_task at; 1150 bool idled = false; 1151 int64_t us_timeout; 1152 1153 while (avalon_buffer_full(avalon)) 1154 cgsleep_ms(40); 1155 1156 avalon_adjust_freq(info, avalon); 1157 1158 /* A full nonce range */ 1159 us_timeout = 0x100000000ll / info->asic_count / info->frequency; 1160 cgsleep_prepare_r(&ts_start); 1161 1162 start_count = avalon->work_array * avalon_get_work_count; 1163 end_count = start_count + avalon_get_work_count; 1164 for (i = start_count, j = 0; i < end_count; i++, j++) { 1165 if (avalon_buffer_full(avalon)) { 1166 applog(LOG_INFO, 1167 "%s%i: Buffer full after only %d of %d work queued", 1168 avalon->drv->name, avalon->device_id, j, avalon_get_work_count); 1169 break; 1170 } 1171 1172 mutex_lock(&info->qlock); 1173 if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) { 1174 avalon_init_task(&at, 0, 0, info->fan_pwm, 1175 info->timeout, info->asic_count, 1176 info->miner_count, 1, 0, info->frequency, info->asic); 1177 avalon_create_task(&at, avalon->works[i]); 1178 info->auto_queued++; 1179 } else { 1180 int idle_freq = info->frequency; 1181 1182 if (!info->idle++) 1183 idled = true; 1184 if (unlikely(info->overheat && opt_avalon_auto)) 1185 idle_freq = AVALON_MIN_FREQUENCY; 1186 avalon_init_task(&at, 0, 0, info->fan_pwm, 1187 info->timeout, info->asic_count, 1188 info->miner_count, 1, 1, idle_freq, info->asic); 1189 /* Reset the auto_queued count if we end up 1190 * idling any miners. */ 1191 avalon_reset_auto(info); 1192 } 1193 mutex_unlock(&info->qlock); 1194 1195 ret = avalon_send_task(&at, avalon, info); 1196 1197 if (unlikely(ret == AVA_SEND_ERROR)) { 1198 /* Send errors are fatal */ 1199 applog(LOG_ERR, "%s%i: Comms error(buffer)", 1200 avalon->drv->name, avalon->device_id); 1201 dev_error(avalon, REASON_DEV_COMMS_ERROR); 1202 goto out; 1203 } 1204 } 1205 1206 avalon_rotate_array(avalon, info); 1207 1208 cgsem_post(&info->qsem); 1209 1210 if (unlikely(idled)) { 1211 applog(LOG_WARNING, "%s%i: Idled %d miners", 1212 avalon->drv->name, avalon->device_id, idled); 1213 } 1214 1215 /* Sleep how long it would take to complete a full nonce range 1216 * at the current frequency using the clock_nanosleep function 1217 * timed from before we started loading new work so it will 1218 * fall short of the full duration. */ 1219 cgsleep_us_r(&ts_start, us_timeout); 1220 } 1221 out: 1222 return NULL; 1223 } 1224 1225 static void *bitburner_send_tasks(void *userdata) 1226 { 1227 struct cgpu_info *avalon = (struct cgpu_info *)userdata; 1228 struct avalon_info *info = avalon->device_data; 1229 const int avalon_get_work_count = info->miner_count; 1230 char threadname[16]; 1231 1232 snprintf(threadname, sizeof(threadname), "%d/AvaSend", avalon->device_id); 1233 RenameThread(threadname); 1234 1235 while (likely(!avalon->shutdown)) { 1236 int start_count, end_count, i, j, ret; 1237 struct avalon_task at; 1238 bool idled = false; 1239 1240 while (avalon_buffer_full(avalon)) 1241 cgsleep_ms(40); 1242 1243 avalon_adjust_freq(info, avalon); 1244 1245 /* Give other threads a chance to acquire qlock. */ 1246 i = 0; 1247 do { 1248 cgsleep_ms(40); 1249 } while (!avalon->shutdown && i++ < 15 1250 && avalon->queued < avalon_get_work_count); 1251 1252 mutex_lock(&info->qlock); 1253 start_count = avalon->work_array * avalon_get_work_count; 1254 end_count = start_count + avalon_get_work_count; 1255 for (i = start_count, j = 0; i < end_count; i++, j++) { 1256 while (avalon_buffer_full(avalon)) 1257 cgsleep_ms(40); 1258 1259 if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) { 1260 avalon_init_task(&at, 0, 0, info->fan_pwm, 1261 info->timeout, info->asic_count, 1262 info->miner_count, 1, 0, info->frequency, info->asic); 1263 avalon_create_task(&at, avalon->works[i]); 1264 info->auto_queued++; 1265 } else { 1266 int idle_freq = info->frequency; 1267 1268 if (!info->idle++) 1269 idled = true; 1270 if (unlikely(info->overheat && opt_avalon_auto)) 1271 idle_freq = AVALON_MIN_FREQUENCY; 1272 avalon_init_task(&at, 0, 0, info->fan_pwm, 1273 info->timeout, info->asic_count, 1274 info->miner_count, 1, 1, idle_freq, info->asic); 1275 /* Reset the auto_queued count if we end up 1276 * idling any miners. */ 1277 avalon_reset_auto(info); 1278 } 1279 1280 ret = bitburner_send_task(&at, avalon); 1281 1282 if (unlikely(ret == AVA_SEND_ERROR)) { 1283 applog(LOG_ERR, "%s%i: Comms error(buffer)", 1284 avalon->drv->name, avalon->device_id); 1285 dev_error(avalon, REASON_DEV_COMMS_ERROR); 1286 info->reset = true; 1287 break; 1288 } 1289 } 1290 1291 bitburner_rotate_array(avalon); 1292 mutex_unlock(&info->qlock); 1293 1294 cgsem_post(&info->qsem); 1295 1296 if (unlikely(idled)) { 1297 applog(LOG_WARNING, "%s%i: Idled %d miners", 1298 avalon->drv->name, avalon->device_id, idled); 1299 } 1300 } 1301 return NULL; 1302 } 1303 1304 static bool avalon_prepare(struct thr_info *thr) 1305 { 1306 struct cgpu_info *avalon = thr->cgpu; 1307 struct avalon_info *info = avalon->device_data; 1308 int array_size = AVALON_ARRAY_SIZE; 1309 void *(*write_thread_fn)(void *) = avalon_send_tasks; 1310 1311 if (is_bitburner(avalon)) { 1312 array_size = BITBURNER_ARRAY_SIZE; 1313 write_thread_fn = bitburner_send_tasks; 1314 } 1315 1316 free(avalon->works); 1317 avalon->works = calloc(info->miner_count * sizeof(struct work *), 1318 array_size); 1319 if (!avalon->works) 1320 quit(1, "Failed to calloc avalon works in avalon_prepare"); 1321 1322 info->thr = thr; 1323 mutex_init(&info->lock); 1324 mutex_init(&info->qlock); 1325 cgsem_init(&info->qsem); 1326 1327 if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon)) 1328 quit(1, "Failed to create avalon read_thr"); 1329 1330 if (pthread_create(&info->write_thr, NULL, write_thread_fn, (void *)avalon)) 1331 quit(1, "Failed to create avalon write_thr"); 1332 1333 avalon_init(avalon); 1334 1335 return true; 1336 } 1337 1338 static inline void record_temp_fan(struct cgpu_info *avalon, struct avalon_info *info, 1339 struct avalon_result *ar) 1340 { 1341 double temp_max; 1342 1343 info->fan0 = ar->fan0 * AVALON_FAN_FACTOR; 1344 info->fan1 = ar->fan1 * AVALON_FAN_FACTOR; 1345 info->fan2 = ar->fan2 * AVALON_FAN_FACTOR; 1346 1347 info->temp0 = ar->temp0; 1348 info->temp1 = ar->temp1; 1349 info->temp2 = ar->temp2; 1350 if (ar->temp0 & 0x80) { 1351 ar->temp0 &= 0x7f; 1352 info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1); 1353 } 1354 if (ar->temp1 & 0x80) { 1355 ar->temp1 &= 0x7f; 1356 info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1); 1357 } 1358 if (ar->temp2 & 0x80) { 1359 ar->temp2 &= 0x7f; 1360 info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1); 1361 } 1362 1363 temp_max = info->temp0; 1364 if (info->temp1 > temp_max) 1365 temp_max = info->temp1; 1366 if (info->temp2 > temp_max) 1367 temp_max = info->temp2; 1368 avalon->temp = avalon->temp * 0.63 + temp_max * 0.37; 1369 } 1370 1371 static void temp_rise(struct avalon_info *info, int temp) 1372 { 1373 if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) { 1374 info->fan_pwm = AVALON_PWM_MAX; 1375 return; 1376 } 1377 if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2) 1378 info->fan_pwm += 10; 1379 else if (temp > opt_avalon_temp) 1380 info->fan_pwm += 5; 1381 else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS) 1382 info->fan_pwm += 1; 1383 else 1384 return; 1385 1386 if (info->fan_pwm > opt_avalon_fan_max) 1387 info->fan_pwm = opt_avalon_fan_max; 1388 } 1389 1390 static void temp_drop(struct avalon_info *info, int temp) 1391 { 1392 if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) { 1393 info->fan_pwm = opt_avalon_fan_min; 1394 return; 1395 } 1396 if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2) 1397 info->fan_pwm -= 10; 1398 else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS) 1399 info->fan_pwm -= 5; 1400 else if (temp < opt_avalon_temp) 1401 info->fan_pwm -= 1; 1402 1403 if (info->fan_pwm < opt_avalon_fan_min) 1404 info->fan_pwm = opt_avalon_fan_min; 1405 } 1406 1407 static inline void adjust_fan(struct avalon_info *info) 1408 { 1409 int temp_new; 1410 1411 temp_new = info->temp_sum / info->temp_history_count; 1412 1413 if (temp_new > info->temp_old) 1414 temp_rise(info, temp_new); 1415 else if (temp_new < info->temp_old) 1416 temp_drop(info, temp_new); 1417 else { 1418 /* temp_new == info->temp_old */ 1419 if (temp_new > opt_avalon_temp) 1420 temp_rise(info, temp_new); 1421 else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS) 1422 temp_drop(info, temp_new); 1423 } 1424 info->temp_old = temp_new; 1425 if (info->temp_old <= opt_avalon_temp) 1426 info->optimal = true; 1427 else 1428 info->optimal = false; 1429 } 1430 1431 static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info, 1432 struct avalon_result *ar) 1433 { 1434 record_temp_fan(avalon, info, ar); 1435 applog(LOG_INFO, 1436 "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t" 1437 "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %.0fC", 1438 info->fan0, info->fan1, info->fan2, 1439 info->temp0, info->temp1, info->temp2, avalon->temp); 1440 info->temp_history_index++; 1441 info->temp_sum += avalon->temp; 1442 applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d", 1443 info->temp_history_index, info->temp_history_count, info->temp_old); 1444 if (is_bitburner(avalon)) { 1445 info->core_voltage = bitburner_get_core_voltage(avalon); 1446 } 1447 if (info->temp_history_index == info->temp_history_count) { 1448 adjust_fan(info); 1449 info->temp_history_index = 0; 1450 info->temp_sum = 0; 1451 } 1452 if (unlikely(info->temp_old >= opt_avalon_overheat)) { 1453 applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id); 1454 info->overheat = true; 1455 } else if (info->overheat && info->temp_old <= opt_avalon_temp) { 1456 applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id); 1457 info->overheat = false; 1458 } 1459 } 1460 1461 static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon) 1462 { 1463 struct avalon_info *info = avalon->device_data; 1464 int lowfan = 10000; 1465 1466 if (is_bitburner(avalon)) { 1467 int temp = info->temp0; 1468 if (info->temp2 > temp) 1469 temp = info->temp2; 1470 if (temp > 99) 1471 temp = 99; 1472 if (temp < 0) 1473 temp = 0; 1474 tailsprintf(buf, bufsiz, "%2dC %3dMHz %4dmV", temp, info->frequency, info->core_voltage); 1475 } else { 1476 /* Find the lowest fan speed of the ASIC cooling fans. */ 1477 if (info->fan1 >= 0 && info->fan1 < lowfan) 1478 lowfan = info->fan1; 1479 if (info->fan2 >= 0 && info->fan2 < lowfan) 1480 lowfan = info->fan2; 1481 1482 tailsprintf(buf, bufsiz, "%2dC/%3dC %04dR", info->temp0, info->temp2, lowfan); 1483 } 1484 } 1485 1486 /* We use a replacement algorithm to only remove references to work done from 1487 * the buffer when we need the extra space for new work. */ 1488 static bool avalon_fill(struct cgpu_info *avalon) 1489 { 1490 struct avalon_info *info = avalon->device_data; 1491 int subid, slot, mc; 1492 struct work *work; 1493 bool ret = true; 1494 1495 mc = info->miner_count; 1496 mutex_lock(&info->qlock); 1497 if (avalon->queued >= mc) 1498 goto out_unlock; 1499 work = get_queued(avalon); 1500 if (unlikely(!work)) { 1501 ret = false; 1502 goto out_unlock; 1503 } 1504 subid = avalon->queued++; 1505 work->subid = subid; 1506 slot = avalon->work_array * mc + subid; 1507 if (likely(avalon->works[slot])) 1508 work_completed(avalon, avalon->works[slot]); 1509 avalon->works[slot] = work; 1510 if (avalon->queued < mc) 1511 ret = false; 1512 out_unlock: 1513 mutex_unlock(&info->qlock); 1514 1515 return ret; 1516 } 1517 1518 static int64_t avalon_scanhash(struct thr_info *thr) 1519 { 1520 struct cgpu_info *avalon = thr->cgpu; 1521 struct avalon_info *info = avalon->device_data; 1522 const int miner_count = info->miner_count; 1523 int64_t hash_count, ms_timeout; 1524 1525 /* Half nonce range */ 1526 ms_timeout = 0x80000000ll / info->asic_count / info->frequency / 1000; 1527 1528 /* Wait until avalon_send_tasks signals us that it has completed 1529 * sending its work or a full nonce range timeout has occurred. We use 1530 * cgsems to never miss a wakeup. */ 1531 cgsem_mswait(&info->qsem, ms_timeout); 1532 1533 mutex_lock(&info->lock); 1534 hash_count = 0xffffffffull * (uint64_t)info->nonces; 1535 avalon->results += info->nonces; 1536 if (avalon->results > miner_count || info->idle) 1537 avalon->results = miner_count; 1538 if (!info->reset) 1539 avalon->results--; 1540 info->nonces = info->idle = 0; 1541 mutex_unlock(&info->lock); 1542 1543 /* Check for nothing but consecutive bad results or consistently less 1544 * results than we should be getting and reset the FPGA if necessary */ 1545 if (!is_bitburner(avalon)) { 1546 if (avalon->results < -miner_count && !info->reset) { 1547 applog(LOG_ERR, "%s%d: Result return rate low, resetting!", 1548 avalon->drv->name, avalon->device_id); 1549 avalon->results = miner_count; 1550 info->reset = true; 1551 } 1552 } 1553 1554 if (unlikely(avalon->usbinfo.nodev)) { 1555 applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread", 1556 avalon->drv->name, avalon->device_id); 1557 hash_count = -1; 1558 } 1559 1560 /* This hashmeter is just a utility counter based on returned shares */ 1561 return hash_count; 1562 } 1563 1564 static void avalon_flush_work(struct cgpu_info *avalon) 1565 { 1566 struct avalon_info *info = avalon->device_data; 1567 1568 /* Will overwrite any work queued. Do this unlocked since it's just 1569 * changing a single non-critical value and prevents deadlocks */ 1570 avalon->queued = 0; 1571 1572 /* Signal main loop we need more work */ 1573 cgsem_post(&info->qsem); 1574 } 1575 1576 static struct api_data *avalon_api_stats(struct cgpu_info *cgpu) 1577 { 1578 struct api_data *root = NULL; 1579 struct avalon_info *info = cgpu->device_data; 1580 char buf[64]; 1581 int i; 1582 double hwp = (cgpu->hw_errors + cgpu->diff1) ? 1583 (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0; 1584 1585 root = api_add_int(root, "baud", &(info->baud), false); 1586 root = api_add_int(root, "miner_count", &(info->miner_count),false); 1587 root = api_add_int(root, "asic_count", &(info->asic_count), false); 1588 root = api_add_int(root, "timeout", &(info->timeout), false); 1589 root = api_add_int(root, "frequency", &(info->frequency), false); 1590 1591 root = api_add_int(root, "fan1", &(info->fan0), false); 1592 root = api_add_int(root, "fan2", &(info->fan1), false); 1593 root = api_add_int(root, "fan3", &(info->fan2), false); 1594 1595 root = api_add_int(root, "temp1", &(info->temp0), false); 1596 root = api_add_int(root, "temp2", &(info->temp1), false); 1597 root = api_add_int(root, "temp3", &(info->temp2), false); 1598 root = api_add_double(root, "temp_max", &cgpu->temp, false); 1599 1600 root = api_add_percent(root, "Device Hardware%", &hwp, true); 1601 root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false); 1602 for (i = 0; i < info->miner_count; i++) { 1603 char mcw[24]; 1604 1605 sprintf(mcw, "match_work_count%d", i + 1); 1606 root = api_add_int(root, mcw, &(info->matching_work[i]), false); 1607 } 1608 if (is_bitburner(cgpu)) { 1609 root = api_add_int(root, "core_voltage", &(info->core_voltage), false); 1610 snprintf(buf, sizeof(buf), "%"PRIu8".%"PRIu8".%"PRIu8, 1611 info->version1, info->version2, info->version3); 1612 root = api_add_string(root, "version", buf, true); 1613 } 1614 root = api_add_uint32(root, "Controller Version", &(info->ctlr_ver), false); 1615 root = api_add_uint32(root, "Avalon Chip", &(info->asic), false); 1616 1617 return root; 1618 } 1619 1620 static void avalon_shutdown(struct thr_info *thr) 1621 { 1622 struct cgpu_info *avalon = thr->cgpu; 1623 struct avalon_info *info = avalon->device_data; 1624 1625 pthread_join(info->read_thr, NULL); 1626 pthread_join(info->write_thr, NULL); 1627 avalon_running_reset(avalon, info); 1628 cgsem_destroy(&info->qsem); 1629 mutex_destroy(&info->qlock); 1630 mutex_destroy(&info->lock); 1631 free(avalon->works); 1632 avalon->works = NULL; 1633 } 1634 1635 static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf) 1636 { 1637 int val; 1638 1639 if (strcasecmp(option, "help") == 0) { 1640 sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d", 1641 AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY, 1642 BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV); 1643 return replybuf; 1644 } 1645 1646 if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) { 1647 if (!is_bitburner(avalon)) { 1648 sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name); 1649 return replybuf; 1650 } 1651 1652 if (!setting || !*setting) { 1653 sprintf(replybuf, "missing millivolts setting"); 1654 return replybuf; 1655 } 1656 1657 val = atoi(setting); 1658 if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) { 1659 sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d", 1660 setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV); 1661 return replybuf; 1662 } 1663 1664 if (bitburner_set_core_voltage(avalon, val)) 1665 return NULL; 1666 else { 1667 sprintf(replybuf, "Set millivolts failed"); 1668 return replybuf; 1669 } 1670 } 1671 1672 if (strcasecmp(option, "freq") == 0) { 1673 if (!setting || !*setting) { 1674 sprintf(replybuf, "missing freq setting"); 1675 return replybuf; 1676 } 1677 1678 val = atoi(setting); 1679 if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) { 1680 sprintf(replybuf, "invalid freq: '%s' valid range %d-%d", 1681 setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY); 1682 return replybuf; 1683 } 1684 1685 avalon_set_freq(avalon, val); 1686 return NULL; 1687 } 1688 1689 sprintf(replybuf, "Unknown option: %s", option); 1690 return replybuf; 1691 } 1692 1693 struct device_drv avalon_drv = { 1694 .drv_id = DRIVER_avalon, 1695 .dname = "avalon", 1696 .name = "AVA", 1697 .drv_detect = avalon_detect, 1698 .thread_prepare = avalon_prepare, 1699 1700 .hash_work = hash_queued_work, 1701 .queue_full = avalon_fill, 1702 .scanwork = avalon_scanhash, 1703 .flush_work = avalon_flush_work, 1704 1705 .get_api_stats = avalon_api_stats, 1706 .get_statline_before = get_avalon_statline_before, 1707 .set_device = avalon_set_device, 1708 .reinit_device = avalon_init, 1709 .thread_shutdown = avalon_shutdown, 1710 };