/ driver-avalon4.c
driver-avalon4.c
1 /* 2 * Copyright 2014-2015 Mikeqin <Fengling.Qin@gmail.com> 3 * Copyright 2013-2015 Con Kolivas <kernel@kolivas.org> 4 * Copyright 2012-2015 Xiangfu <xiangfu@openmobilefree.com> 5 * Copyright 2012 Luke Dashjr 6 * Copyright 2012 Andrew Smith 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the Free 10 * Software Foundation; either version 3 of the License, or (at your option) 11 * any later version. See COPYING for more details. 12 */ 13 #include <math.h> 14 #include "config.h" 15 16 #include "miner.h" 17 #include "driver-avalon4.h" 18 #include "crc.h" 19 #include "sha2.h" 20 #include "hexdump.c" 21 22 #define get_fan_pwm(v) (AVA4_PWM_MAX - (v) * AVA4_PWM_MAX / 100) 23 24 int opt_avalon4_temp_target = AVA4_DEFAULT_TEMP_TARGET; 25 int opt_avalon4_overheat = AVA4_DEFAULT_TEMP_OVERHEAT; 26 27 int opt_avalon4_fan_min = AVA4_DEFAULT_FAN_MIN; 28 int opt_avalon4_fan_max = AVA4_DEFAULT_FAN_MAX; 29 30 bool opt_avalon4_autov; 31 bool opt_avalon4_freezesafe; 32 int opt_avalon4_voltage_min = AVA4_DEFAULT_VOLTAGE; 33 int opt_avalon4_voltage_max = AVA4_DEFAULT_VOLTAGE; 34 unsigned int opt_avalon4_freq[3] = {AVA4_DEFAULT_FREQUENCY, 35 AVA4_DEFAULT_FREQUENCY, 36 AVA4_DEFAULT_FREQUENCY}; 37 38 int opt_avalon4_polling_delay = AVA4_DEFAULT_POLLING_DELAY; 39 40 int opt_avalon4_aucspeed = AVA4_AUC_SPEED; 41 int opt_avalon4_aucxdelay = AVA4_AUC_XDELAY; 42 43 int opt_avalon4_ntime_offset = AVA4_DEFAULT_ASIC_MAX; 44 int opt_avalon4_miningmode = AVA4_MOD_CUSTOM; 45 46 int opt_avalon4_ntcb = AVA4_DEFAULT_NTCB; 47 int opt_avalon4_freq_min = AVA4_DEFAULT_FREQUENCY_MIN; 48 int opt_avalon4_freq_max = AVA4_DEFAULT_FREQUENCY_MAX; 49 bool opt_avalon4_noncecheck = AVA4_DEFAULT_NCHECK; 50 int opt_avalon4_smart_speed = AVA4_DEFAULT_SMART_SPEED; 51 /* 52 * smart speed have 3 modes 53 * 1. auto speed by A3218 chips 54 * 2. option 1 + adjust by least pll count 55 * option 1 + adjust by most pll count 56 * 3. option 1 + adjust by average frequency 57 */ 58 int opt_avalon4_least_pll_check = AVA4_DEFAULT_LEAST_PLL; 59 int opt_avalon4_most_pll_check = AVA4_DEFAULT_MOST_PLL; 60 int opt_avalon4_speed_bingo = AVA4_DEFAULT_SPEED_BINGO; 61 int opt_avalon4_speed_error = AVA4_DEFAULT_SPEED_ERROR; 62 bool opt_avalon4_iic_detect = AVA4_DEFAULT_IIC_DETECT; 63 int opt_avalon4_freqadj_time = AVA4_DEFAULT_FREQADJ_TIME; 64 int opt_avalon4_delta_temp = AVA4_DEFAULT_DELTA_T; 65 int opt_avalon4_delta_freq = AVA4_DEFAULT_DELTA_FREQ; 66 int opt_avalon4_freqadj_temp = AVA4_MM60_TEMP_FREQADJ; 67 68 static uint8_t avalon4_freezsafemode = 0; 69 /* Only for Avalon4 */ 70 static uint32_t g_freq_array[][2] = { 71 {100, 0x1e678447}, 72 {113, 0x22688447}, 73 {125, 0x1c470447}, 74 {138, 0x2a6a8447}, 75 {150, 0x22488447}, 76 {163, 0x326c8447}, 77 {175, 0x1a268447}, 78 {188, 0x1c270447}, 79 {200, 0x1e278447}, 80 {213, 0x20280447}, 81 {225, 0x22288447}, 82 {238, 0x24290447}, 83 {250, 0x26298447}, 84 {263, 0x282a0447}, 85 {275, 0x2a2a8447}, 86 {288, 0x2c2b0447}, 87 {300, 0x2e2b8447}, 88 {313, 0x302c0447}, 89 {325, 0x322c8447}, 90 {338, 0x342d0447}, 91 {350, 0x1a068447}, 92 {363, 0x382e0447}, 93 {375, 0x1c070447}, 94 {388, 0x3c2f0447}, 95 {400, 0x1e078447}, 96 {413, 0x40300447}, 97 {425, 0x20080447}, 98 {438, 0x44310447}, 99 {450, 0x22088447}, 100 {463, 0x48320447}, 101 {475, 0x24090447}, 102 {488, 0x4c330447}, 103 {500, 0x26098447}, 104 {513, 0x50340447}, 105 {525, 0x280a0447}, 106 {538, 0x54350447}, 107 {550, 0x2a0a8447}, 108 {563, 0x58360447}, 109 {575, 0x2c0b0447}, 110 {588, 0x5c370447}, 111 {600, 0x2e0b8447}, 112 {613, 0x60380447}, 113 {625, 0x300c0447}, 114 {638, 0x64390447}, 115 {650, 0x320c8447}, 116 {663, 0x683a0447}, 117 {675, 0x340d0447}, 118 {688, 0x6c3b0447}, 119 {700, 0x360d8447}, 120 {713, 0x703c0447}, 121 {725, 0x380e0447}, 122 {738, 0x743d0447}, 123 {750, 0x3a0e8447}, 124 {763, 0x783e0447}, 125 {775, 0x3c0f0447}, 126 {788, 0x7c3f0447}, 127 {800, 0x3e0f8447}, 128 {813, 0x3e0f8447}, 129 {825, 0x40100447}, 130 {838, 0x40100447}, 131 {850, 0x42108447}, 132 {863, 0x42108447}, 133 {875, 0x44110447}, 134 {888, 0x44110447}, 135 {900, 0x46118447}, 136 {913, 0x46118447}, 137 {925, 0x48120447}, 138 {938, 0x48120447}, 139 {950, 0x4a128447}, 140 {963, 0x4a128447}, 141 {975, 0x4c130447}, 142 {988, 0x4c130447}, 143 {1000, 0x4e138447} 144 }; 145 146 #define UNPACK32(x, str) \ 147 { \ 148 *((str) + 3) = (uint8_t) ((x) ); \ 149 *((str) + 2) = (uint8_t) ((x) >> 8); \ 150 *((str) + 1) = (uint8_t) ((x) >> 16); \ 151 *((str) + 0) = (uint8_t) ((x) >> 24); \ 152 } 153 154 static inline void sha256_prehash(const unsigned char *message, unsigned int len, unsigned char *digest) 155 { 156 sha256_ctx ctx; 157 int i; 158 sha256_init(&ctx); 159 sha256_update(&ctx, message, len); 160 161 for (i = 0; i < 8; i++) { 162 UNPACK32(ctx.h[i], &digest[i << 2]); 163 } 164 } 165 166 static inline uint8_t rev8(uint8_t d) 167 { 168 int i; 169 uint8_t out = 0; 170 171 /* (from left to right) */ 172 for (i = 0; i < 8; i++) 173 if (d & (1 << i)) 174 out |= (1 << (7 - i)); 175 176 return out; 177 } 178 179 #define R_REF 10000 180 #define R0 10000 181 #define T0 25 182 static float convert_temp(uint16_t adc) 183 { 184 float ret, resistance; 185 186 if (!adc || adc >= AVA4_ADC_MAX) 187 return -273.15; 188 189 resistance = (AVA4_ADC_MAX * 1.0 / adc) - 1; 190 resistance = R_REF / resistance; 191 ret = resistance / R0; 192 ret = logf(ret); 193 ret /= opt_avalon4_ntcb; 194 ret += 1.0 / (T0 + 273.15); 195 ret = 1.0 / ret; 196 ret -= 273.15; 197 198 return ret; 199 } 200 201 #define V_REF 3.3 202 static float convert_voltage(uint16_t adc, float percent) 203 { 204 float voltage; 205 206 voltage = adc * V_REF * 1.0 / AVA4_ADC_MAX / percent; 207 return voltage + 0.4; 208 } 209 210 char *set_avalon4_fan(char *arg) 211 { 212 int val1, val2, ret; 213 214 ret = sscanf(arg, "%d-%d", &val1, &val2); 215 if (ret < 1) 216 return "No values passed to avalon4-fan"; 217 if (ret == 1) 218 val2 = val1; 219 220 if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1) 221 return "Invalid value passed to avalon4-fan"; 222 223 opt_avalon4_fan_min = val1; 224 opt_avalon4_fan_max = val2; 225 226 return NULL; 227 } 228 229 char *set_avalon4_freq(char *arg) 230 { 231 char *colon1, *colon2; 232 int val1 = 0, val2 = 0, val3 = 0; 233 234 if (!(*arg)) 235 return NULL; 236 237 colon1 = strchr(arg, ':'); 238 if (colon1) 239 *(colon1++) = '\0'; 240 241 if (*arg) { 242 val1 = atoi(arg); 243 if (val1 < AVA4_DEFAULT_FREQUENCY_MIN || val1 > AVA4_DEFAULT_FREQUENCY_MAX) 244 return "Invalid value1 passed to avalon4-freq"; 245 } 246 247 if (colon1 && *colon1) { 248 colon2 = strchr(colon1, ':'); 249 if (colon2) 250 *(colon2++) = '\0'; 251 252 if (*colon1) { 253 val2 = atoi(colon1); 254 if (val2 < AVA4_DEFAULT_FREQUENCY_MIN || val2 > AVA4_DEFAULT_FREQUENCY_MAX) 255 return "Invalid value2 passed to avalon4-freq"; 256 } 257 258 if (colon2 && *colon2) { 259 val3 = atoi(colon2); 260 if (val3 < AVA4_DEFAULT_FREQUENCY_MIN || val3 > AVA4_DEFAULT_FREQUENCY_MAX) 261 return "Invalid value3 passed to avalon4-freq"; 262 } 263 } 264 265 if (!val1) 266 val3 = val2 = val1 = AVA4_DEFAULT_FREQUENCY; 267 268 if (!val2) 269 val3 = val2 = val1; 270 271 if (!val3) 272 val3 = val2; 273 274 opt_avalon4_freq[0] = val1; 275 opt_avalon4_freq[1] = val2; 276 opt_avalon4_freq[2] = val3; 277 278 return NULL; 279 } 280 281 char *set_avalon4_voltage(char *arg) 282 { 283 int val1, val2, ret; 284 285 ret = sscanf(arg, "%d-%d", &val1, &val2); 286 if (ret < 1) 287 return "No values passed to avalon4-voltage"; 288 if (ret == 1) 289 val2 = val1; 290 291 if (val1 < AVA4_DEFAULT_VOLTAGE_MIN || val1 > AVA4_DEFAULT_VOLTAGE_MAX || 292 val2 < AVA4_DEFAULT_VOLTAGE_MIN || val2 > AVA4_DEFAULT_VOLTAGE_MAX || 293 val2 < val1) 294 return "Invalid value passed to avalon4-voltage"; 295 296 opt_avalon4_voltage_min = val1; 297 opt_avalon4_voltage_max = val2; 298 299 return NULL; 300 } 301 302 static int avalon4_init_pkg(struct avalon4_pkg *pkg, uint8_t type, uint8_t idx, uint8_t cnt) 303 { 304 unsigned short crc; 305 306 pkg->head[0] = AVA4_H1; 307 pkg->head[1] = AVA4_H2; 308 309 pkg->type = type; 310 pkg->opt = 0; 311 pkg->idx = idx; 312 pkg->cnt = cnt; 313 314 crc = crc16(pkg->data, AVA4_P_DATA_LEN); 315 316 pkg->crc[0] = (crc & 0xff00) >> 8; 317 pkg->crc[1] = crc & 0x00ff; 318 return 0; 319 } 320 321 static int job_idcmp(uint8_t *job_id, char *pool_job_id) 322 { 323 int job_id_len; 324 unsigned short crc, crc_expect; 325 326 if (!pool_job_id) 327 return 1; 328 329 job_id_len = strlen(pool_job_id); 330 crc_expect = crc16((unsigned char *)pool_job_id, job_id_len); 331 332 crc = job_id[0] << 8 | job_id[1]; 333 334 if (crc_expect == crc) 335 return 0; 336 337 applog(LOG_DEBUG, "Avalon4: job_id doesn't match! [%04x:%04x (%s)]", 338 crc, crc_expect, pool_job_id); 339 340 return 1; 341 } 342 343 static inline int get_current_temp_max(struct avalon4_info *info) 344 { 345 int i; 346 int t = info->temp[0]; 347 348 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 349 if (info->enable[i] && info->temp[i] > t) 350 t = info->temp[i]; 351 } 352 return t; 353 } 354 355 static inline int get_temp_max(struct avalon4_info *info, int addr) 356 { 357 int i; 358 int t = -273, t1 = -273; 359 360 if (info->enable[addr]) { 361 t = info->temp[addr]; 362 363 for (i = 0; i < 2; i++) { 364 t1 = convert_temp(info->adc[addr][i]); 365 if (t1 > t) 366 t = t1; 367 } 368 } 369 return t; 370 } 371 372 /* http://www.onsemi.com/pub_link/Collateral/ADP3208D.PDF */ 373 static uint32_t encode_voltage_adp3208d(uint32_t v) 374 { 375 return rev8((0x78 - v / 125) << 1 | 1) << 8; 376 } 377 378 static uint32_t decode_voltage_adp3208d(uint32_t v) 379 { 380 return (0x78 - (rev8(v >> 8) >> 1)) * 125; 381 } 382 383 /* http://www.onsemi.com/pub/Collateral/NCP5392P-D.PDF */ 384 static uint32_t encode_voltage_ncp5392p(uint32_t v) 385 { 386 if (v == 0) 387 return 0xff00; 388 389 return rev8(((0x59 - (v - 5000) / 125) & 0xff) << 1 | 1) << 8; 390 } 391 392 static uint32_t decode_voltage_ncp5392p(uint32_t v) 393 { 394 if (v == 0xff00) 395 return 0; 396 397 return (0x59 - (rev8(v >> 8) >> 1)) * 125 + 5000; 398 } 399 400 static inline uint32_t adjust_fan(struct avalon4_info *info, int id) 401 { 402 uint32_t pwm; 403 int t = info->temp[id], diff, fandiff = opt_avalon4_fan_max - opt_avalon4_fan_min;; 404 405 if (info->mod_type[id] == AVA4_TYPE_MM60) { 406 int t1, t2; 407 t1 = (int)convert_temp(info->adc[id][0]), 408 t2 = (int)convert_temp(info->adc[id][1]), 409 410 t = t > t1 ? t : t1; 411 t = t > t2 ? t : t2; 412 } 413 414 if (avalon4_freezsafemode) { 415 pwm = get_fan_pwm(AVA4_FREEZESAFE_FAN); 416 return pwm; 417 } 418 419 /* Scale fan% non linearly relatively to target temperature. It will 420 * not try to keep the temperature at temp_target that accurately but 421 * avoids temperature overshoot in both directions. */ 422 diff = t - opt_avalon4_temp_target + 30; 423 if (diff > 32) 424 diff = 32; 425 else if (diff < 0) 426 diff = 0; 427 diff *= diff; 428 fandiff = fandiff * diff / 1024; 429 info->fan_pct[id] = opt_avalon4_fan_min + fandiff; 430 431 pwm = get_fan_pwm(info->fan_pct[id]); 432 433 if ((info->mod_type[id] == AVA4_TYPE_MM60) && 434 (info->freq_mode[id] == AVA4_FREQ_TEMPADJ_MODE)) 435 pwm = get_fan_pwm(opt_avalon4_fan_max); 436 437 if (info->cutoff[id]) 438 pwm = get_fan_pwm(opt_avalon4_fan_max); 439 440 applog(LOG_DEBUG, "[%d], Adjust_fan: %dC-%d%%(%03x)", id, t, info->fan_pct[id], pwm); 441 442 return pwm; 443 } 444 445 static int decode_pkg(struct thr_info *thr, struct avalon4_ret *ar, int modular_id) 446 { 447 struct cgpu_info *avalon4 = thr->cgpu; 448 struct avalon4_info *info = avalon4->device_data; 449 struct pool *pool, *real_pool; 450 struct pool *pool_stratum0 = &info->pool0; 451 struct pool *pool_stratum1 = &info->pool1; 452 struct pool *pool_stratum2 = &info->pool2; 453 454 unsigned int expected_crc; 455 unsigned int actual_crc; 456 uint32_t nonce, nonce2, ntime, miner, chip_id, volt, tmp; 457 uint8_t job_id[4]; 458 int pool_no, i; 459 uint32_t val[AVA4_DEFAULT_MINER_MAX]; 460 461 if (ar->head[0] != AVA4_H1 && ar->head[1] != AVA4_H2) { 462 applog(LOG_DEBUG, "%s-%d-%d: H1 %02x, H2 %02x", 463 avalon4->drv->name, avalon4->device_id, modular_id, 464 ar->head[0], ar->head[1]); 465 hexdump(ar->data, 32); 466 return 1; 467 } 468 469 expected_crc = crc16(ar->data, AVA4_P_DATA_LEN); 470 actual_crc = (ar->crc[0] & 0xff) | ((ar->crc[1] & 0xff) << 8); 471 if (expected_crc != actual_crc) { 472 applog(LOG_DEBUG, "%s-%d-%d: %02x: expected crc(%04x), actual_crc(%04x)", 473 avalon4->drv->name, avalon4->device_id, modular_id, 474 ar->type, expected_crc, actual_crc); 475 return 1; 476 } 477 478 switch(ar->type) { 479 case AVA4_P_NONCE: 480 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_NONCE", avalon4->drv->name, avalon4->device_id, modular_id); 481 memcpy(&miner, ar->data + 0, 4); 482 memcpy(&pool_no, ar->data + 4, 4); 483 memcpy(&nonce2, ar->data + 8, 4); 484 memcpy(&ntime, ar->data + 12, 4); 485 memcpy(&nonce, ar->data + 16, 4); 486 memcpy(job_id, ar->data + 20, 4); 487 488 miner = be32toh(miner); 489 chip_id = (miner >> 16) & 0xffff; 490 miner &= 0xffff; 491 pool_no = be32toh(pool_no); 492 ntime = be32toh(ntime); 493 if (miner >= info->miner_count[modular_id] || 494 pool_no >= total_pools || pool_no < 0) { 495 applog(LOG_DEBUG, "%s-%d-%d: Wrong miner/pool_no %d/%d", 496 avalon4->drv->name, avalon4->device_id, modular_id, 497 miner, pool_no); 498 break; 499 } 500 nonce2 = be32toh(nonce2); 501 nonce = be32toh(nonce); 502 503 if ((info->mod_type[modular_id] == AVA4_TYPE_MM40) || 504 (info->mod_type[modular_id] == AVA4_TYPE_MM41) || 505 (info->mod_type[modular_id] == AVA4_TYPE_MM50)) 506 nonce -= 0x4000; 507 508 applog(LOG_DEBUG, "%s-%d-%d: Found! P:%d - N2:%08x N:%08x NR:%d [M:%d - MW: %d(%d,%d,%d,%d)]", 509 avalon4->drv->name, avalon4->device_id, modular_id, 510 pool_no, nonce2, nonce, ntime, 511 miner, info->matching_work[modular_id][miner], 512 info->chipmatching_work[modular_id][miner][0], 513 info->chipmatching_work[modular_id][miner][1], 514 info->chipmatching_work[modular_id][miner][2], 515 info->chipmatching_work[modular_id][miner][3]); 516 517 real_pool = pool = pools[pool_no]; 518 if (job_idcmp(job_id, pool->swork.job_id)) { 519 if (!job_idcmp(job_id, pool_stratum0->swork.job_id)) { 520 applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum0! (%s)", 521 avalon4->drv->name, avalon4->device_id, modular_id, 522 pool_stratum0->swork.job_id); 523 pool = pool_stratum0; 524 } else if (!job_idcmp(job_id, pool_stratum1->swork.job_id)) { 525 applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum1! (%s)", 526 avalon4->drv->name, avalon4->device_id, modular_id, 527 pool_stratum1->swork.job_id); 528 pool = pool_stratum1; 529 } else if (!job_idcmp(job_id, pool_stratum2->swork.job_id)) { 530 applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum2! (%s)", 531 avalon4->drv->name, avalon4->device_id, modular_id, 532 pool_stratum2->swork.job_id); 533 pool = pool_stratum2; 534 } else { 535 applog(LOG_ERR, "%s-%d-%d: Cannot match to any stratum! (%s)", 536 avalon4->drv->name, avalon4->device_id, modular_id, 537 pool->swork.job_id); 538 inc_hw_errors(thr); 539 if (info->mod_type[modular_id] == AVA4_TYPE_MM60) { 540 info->hw_works_i[modular_id][miner]++; 541 info->hw5_i[modular_id][miner][info->i_5s]++; 542 } 543 break; 544 } 545 } 546 547 if (!submit_nonce2_nonce(thr, pool, real_pool, nonce2, nonce, ntime)) { 548 if (info->mod_type[modular_id] == AVA4_TYPE_MM60) { 549 info->hw_works_i[modular_id][miner]++; 550 info->hw5_i[modular_id][miner][info->i_5s]++; 551 } 552 } else { 553 info->matching_work[modular_id][miner]++; 554 info->chipmatching_work[modular_id][miner][chip_id]++; 555 } 556 break; 557 case AVA4_P_STATUS: 558 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS", avalon4->drv->name, avalon4->device_id, modular_id); 559 hexdump(ar->data, 32); 560 memcpy(&tmp, ar->data, 4); 561 tmp = be32toh(tmp); 562 info->temp[modular_id] = tmp; 563 564 memcpy(&tmp, ar->data + 4, 4); 565 tmp = be32toh(tmp); 566 info->fan[modular_id] = tmp; 567 568 memcpy(&(info->get_frequency[modular_id]), ar->data + 8, 4); 569 memcpy(&(info->get_voltage[modular_id]), ar->data + 12, 4); 570 memcpy(&(info->local_work[modular_id]), ar->data + 16, 4); 571 memcpy(&(info->hw_work[modular_id]), ar->data + 20, 4); 572 memcpy(&(info->power_good[modular_id]), ar->data + 24, 4); 573 memcpy(&(info->error_code[modular_id]), ar->data + 28, 4); 574 575 if (info->mod_type[modular_id] == AVA4_TYPE_MM60) { 576 if (info->total_asics[modular_id]) 577 info->get_frequency[modular_id] = be32toh(info->get_frequency[modular_id]) / info->total_asics[modular_id]; 578 } else 579 info->get_frequency[modular_id] = be32toh(info->get_frequency[modular_id]) * 3968 / 65; 580 info->get_voltage[modular_id] = be32toh(info->get_voltage[modular_id]); 581 info->local_work[modular_id] = be32toh(info->local_work[modular_id]); 582 info->hw_work[modular_id] = be32toh(info->hw_work[modular_id]); 583 info->power_good[modular_id] = be32toh(info->power_good[modular_id]); 584 info->error_code[modular_id] = be32toh(info->error_code[modular_id]); 585 586 volt = info->get_voltage[modular_id]; 587 if (info->mod_type[modular_id] == AVA4_TYPE_MM40) 588 tmp = decode_voltage_adp3208d(volt); 589 if (info->mod_type[modular_id] == AVA4_TYPE_MM41) 590 tmp = decode_voltage_ncp5392p(volt); 591 if (info->mod_type[modular_id] == AVA4_TYPE_MM50) 592 tmp = decode_voltage_ncp5392p(volt); 593 /* TODO: fix it with the actual board */ 594 if (info->mod_type[modular_id] == AVA4_TYPE_MM60) 595 tmp = decode_voltage_ncp5392p(volt); 596 597 info->get_voltage[modular_id] = tmp; 598 599 info->local_works[modular_id] += info->local_work[modular_id]; 600 info->hw_works[modular_id] += info->hw_work[modular_id]; 601 602 info->lw5[modular_id][info->i_5s] += info->local_work[modular_id]; 603 info->hw5[modular_id][info->i_5s] += info->hw_work[modular_id]; 604 605 avalon4->temp = get_current_temp_max(info); 606 break; 607 case AVA4_P_STATUS_LW: 608 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_LW", avalon4->drv->name, avalon4->device_id, modular_id); 609 for (i = 0; i < info->miner_count[modular_id]; i++) { 610 info->local_works_i[modular_id][i] += ((ar->data[i * 3] << 16) | 611 (ar->data[i * 3 + 1] << 8) | 612 (ar->data[i * 3 + 2])); 613 info->lw5_i[modular_id][i][info->i_5s] += ((ar->data[i * 3] << 16) | 614 (ar->data[i * 3 + 1] << 8) | 615 (ar->data[i * 3 + 2])); 616 } 617 break; 618 case AVA4_P_STATUS_HW: 619 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_HW", avalon4->drv->name, avalon4->device_id, modular_id); 620 if (info->mod_type[modular_id] == AVA4_TYPE_MM60) { 621 applog(LOG_NOTICE, "%s-%d-%d: AVA4_P_STATUS_HW found on Avalon6!", avalon4->drv->name, avalon4->device_id, modular_id); 622 break; 623 } 624 625 for (i = 0; i < info->miner_count[modular_id]; i++) { 626 info->hw_works_i[modular_id][i] += ((ar->data[i * 3] << 16) | 627 (ar->data[i * 3 + 1] << 8) | 628 (ar->data[i * 3 + 2])); 629 info->hw5_i[modular_id][i][info->i_5s] += ((ar->data[i * 3] << 16) | 630 (ar->data[i * 3 + 1] << 8) | 631 (ar->data[i * 3 + 2])); 632 } 633 break; 634 case AVA4_P_ACKDETECT: 635 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_ACKDETECT", avalon4->drv->name, avalon4->device_id, modular_id); 636 break; 637 case AVA4_P_STATUS_VOLT: 638 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_VOLT", avalon4->drv->name, avalon4->device_id, modular_id); 639 hexdump(ar->data, 32); 640 for(i = 0; i < info->miner_count[modular_id]; i++) { 641 tmp = (ar->data[i * 2] << 8) + ar->data[i * 2 + 1]; 642 643 if (info->mod_type[modular_id] == AVA4_TYPE_MM40) 644 tmp = decode_voltage_adp3208d(tmp); 645 if (info->mod_type[modular_id] == AVA4_TYPE_MM41) 646 tmp = decode_voltage_ncp5392p(tmp); 647 if (info->mod_type[modular_id] == AVA4_TYPE_MM50) 648 tmp = decode_voltage_ncp5392p(tmp); 649 /* TODO: fix it with the actual board */ 650 if (info->mod_type[modular_id] == AVA4_TYPE_MM60) 651 tmp = decode_voltage_ncp5392p(tmp); 652 653 if (tmp < AVA4_DEFAULT_VOLTAGE_MIN || tmp > AVA4_DEFAULT_VOLTAGE_MAX) { 654 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_VOLT invalid voltage %d", avalon4->drv->name, avalon4->device_id, modular_id, tmp); 655 return 1; 656 } 657 val[((4 + i / 5 * 5) - i + (i / 5 * 5))] = tmp; 658 } 659 660 if (i == info->miner_count[modular_id]) { 661 for (i = 0; i < info->miner_count[modular_id]; i++) { 662 info->get_voltage_i[modular_id][i] = val[i]; 663 } 664 } 665 break; 666 case AVA4_P_STATUS_MA: 667 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_MA", avalon4->drv->name, avalon4->device_id, modular_id); 668 for (i = 0; i < info->asic_count[modular_id]; i++) 669 info->ma_sum[modular_id][ar->opt][i] = ar->data[i]; 670 break; 671 case AVA4_P_STATUS_M: 672 applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_M", avalon4->drv->name, avalon4->device_id, modular_id); 673 for (i = 0; i < AVA4_DEFAULT_ADC_MAX; i++) 674 info->adc[modular_id][i] = (ar->data[2 * i] << 8) | ar->data[(2 * i) + 1]; 675 676 /* MCU LED status --> data[2 * AVA4_DEFAULT_ADC : 2 * AVA4_DEFAULT_ADC_MAX + 3] */ 677 for (i = 0; i < AVA4_DEFAULT_PLL_MAX; i++) 678 info->pll_sel[modular_id][i] = (ar->data[2 * (AVA4_DEFAULT_ADC_MAX + 2 + i)] << 8) | 679 ar->data[(2 * (AVA4_DEFAULT_ADC_MAX + 2 + i)) + 1]; 680 break; 681 default: 682 applog(LOG_DEBUG, "%s-%d-%d: Unknown response", avalon4->drv->name, avalon4->device_id, modular_id); 683 break; 684 } 685 return 0; 686 } 687 688 /* 689 # IIC packet format: length[1]+transId[1]+sesId[1]+req[1]+data[60] 690 # length: 4+len(data) 691 # transId: 0 692 # sesId: 0 693 # req: checkout the header file 694 # data: 695 # INIT: clock_rate[4] + reserved[4] + payload[52] 696 # XFER: txSz[1]+rxSz[1]+options[1]+slaveAddr[1] + payload[56] 697 */ 698 static int avalon4_auc_init_pkg(uint8_t *iic_pkg, struct avalon4_iic_info *iic_info, uint8_t *buf, int wlen, int rlen) 699 { 700 memset(iic_pkg, 0, AVA4_AUC_P_SIZE); 701 702 switch (iic_info->iic_op) { 703 case AVA4_IIC_INIT: 704 iic_pkg[0] = 12; /* 4 bytes IIC header + 4 bytes speed + 4 bytes xfer delay */ 705 iic_pkg[3] = AVA4_IIC_INIT; 706 iic_pkg[4] = iic_info->iic_param.aucParam[0] & 0xff; 707 iic_pkg[5] = (iic_info->iic_param.aucParam[0] >> 8) & 0xff; 708 iic_pkg[6] = (iic_info->iic_param.aucParam[0] >> 16) & 0xff; 709 iic_pkg[7] = iic_info->iic_param.aucParam[0] >> 24; 710 iic_pkg[8] = iic_info->iic_param.aucParam[1] & 0xff; 711 iic_pkg[9] = (iic_info->iic_param.aucParam[1] >> 8) & 0xff; 712 iic_pkg[10] = (iic_info->iic_param.aucParam[1] >> 16) & 0xff; 713 iic_pkg[11] = iic_info->iic_param.aucParam[1] >> 24; 714 break; 715 case AVA4_IIC_XFER: 716 iic_pkg[0] = 8 + wlen; 717 iic_pkg[3] = AVA4_IIC_XFER; 718 iic_pkg[4] = wlen; 719 iic_pkg[5] = rlen; 720 iic_pkg[7] = iic_info->iic_param.slave_addr; 721 if (buf && wlen) 722 memcpy(iic_pkg + 8, buf, wlen); 723 break; 724 case AVA4_IIC_RESET: 725 case AVA4_IIC_DEINIT: 726 case AVA4_IIC_INFO: 727 iic_pkg[0] = 4; 728 iic_pkg[3] = iic_info->iic_op; 729 break; 730 731 default: 732 break; 733 } 734 735 return 0; 736 } 737 738 static int avalon4_iic_xfer(struct cgpu_info *avalon4, uint8_t slave_addr, 739 uint8_t *wbuf, int wlen, 740 uint8_t *rbuf, int rlen) 741 { 742 struct avalon4_info *info = avalon4->device_data; 743 struct i2c_ctx *pctx = NULL; 744 int err = 1; 745 bool ret = false; 746 747 pctx = info->i2c_slaves[slave_addr]; 748 if (!pctx) { 749 applog(LOG_ERR, "%s-%d: IIC xfer i2c slaves null!", avalon4->drv->name, avalon4->device_id); 750 goto out; 751 } 752 753 if (wbuf) { 754 ret = pctx->write_raw(pctx, wbuf, wlen); 755 if (!ret) { 756 applog(LOG_DEBUG, "%s-%d: IIC xfer write raw failed!", avalon4->drv->name, avalon4->device_id); 757 goto out; 758 } 759 } 760 761 cgsleep_ms(5); 762 763 if (rbuf) { 764 ret = pctx->read_raw(pctx, rbuf, rlen); 765 if (!ret) { 766 applog(LOG_DEBUG, "%s-%d: IIC xfer read raw failed!", avalon4->drv->name, avalon4->device_id); 767 hexdump(rbuf, rlen); 768 goto out; 769 } 770 } 771 772 return 0; 773 out: 774 return err; 775 } 776 777 static int avalon4_auc_xfer(struct cgpu_info *avalon4, 778 uint8_t *wbuf, int wlen, int *write, 779 uint8_t *rbuf, int rlen, int *read) 780 { 781 int err = -1; 782 783 if (unlikely(avalon4->usbinfo.nodev)) 784 goto out; 785 786 usb_buffer_clear(avalon4); 787 err = usb_write(avalon4, (char *)wbuf, wlen, write, C_AVA4_WRITE); 788 if (err || *write != wlen) { 789 applog(LOG_DEBUG, "%s-%d: AUC xfer %d, w(%d-%d)!", avalon4->drv->name, avalon4->device_id, err, wlen, *write); 790 usb_nodev(avalon4); 791 goto out; 792 } 793 794 cgsleep_ms(opt_avalon4_aucxdelay / 4800 + 1); 795 796 rlen += 4; /* Add 4 bytes IIC header */ 797 err = usb_read(avalon4, (char *)rbuf, rlen, read, C_AVA4_READ); 798 if (err || *read != rlen || *read != rbuf[0]) { 799 applog(LOG_DEBUG, "%s-%d: AUC xfer %d, r(%d-%d-%d)!", avalon4->drv->name, avalon4->device_id, err, rlen - 4, *read, rbuf[0]); 800 hexdump(rbuf, rlen); 801 return -1; 802 } 803 *read = rbuf[0] - 4; /* Remove 4 bytes IIC header */ 804 out: 805 return err; 806 } 807 808 static int avalon4_auc_init(struct cgpu_info *avalon4, char *ver) 809 { 810 struct avalon4_iic_info iic_info; 811 int err, wlen, rlen; 812 uint8_t wbuf[AVA4_AUC_P_SIZE]; 813 uint8_t rbuf[AVA4_AUC_P_SIZE]; 814 815 if (unlikely(avalon4->usbinfo.nodev)) 816 return 1; 817 818 /* Try to clean the AUC buffer */ 819 usb_buffer_clear(avalon4); 820 err = usb_read(avalon4, (char *)rbuf, AVA4_AUC_P_SIZE, &rlen, C_AVA4_READ); 821 applog(LOG_DEBUG, "%s-%d: AUC usb_read %d, %d!", avalon4->drv->name, avalon4->device_id, err, rlen); 822 hexdump(rbuf, AVA4_AUC_P_SIZE); 823 824 /* Reset */ 825 iic_info.iic_op = AVA4_IIC_RESET; 826 rlen = 0; 827 avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen); 828 829 memset(rbuf, 0, AVA4_AUC_P_SIZE); 830 err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen); 831 if (err) { 832 applog(LOG_ERR, "%s-%d: Failed to reset Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id); 833 return 1; 834 } 835 836 /* Deinit */ 837 iic_info.iic_op = AVA4_IIC_DEINIT; 838 rlen = 0; 839 avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen); 840 841 memset(rbuf, 0, AVA4_AUC_P_SIZE); 842 err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen); 843 if (err) { 844 applog(LOG_ERR, "%s-%d: Failed to deinit Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id); 845 return 1; 846 } 847 848 /* Init */ 849 iic_info.iic_op = AVA4_IIC_INIT; 850 iic_info.iic_param.aucParam[0] = opt_avalon4_aucspeed; 851 iic_info.iic_param.aucParam[1] = opt_avalon4_aucxdelay; 852 rlen = AVA4_AUC_VER_LEN; 853 avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen); 854 855 memset(rbuf, 0, AVA4_AUC_P_SIZE); 856 err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen); 857 if (err) { 858 applog(LOG_ERR, "%s-%d: Failed to init Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id); 859 return 1; 860 } 861 862 hexdump(rbuf, AVA4_AUC_P_SIZE); 863 864 memcpy(ver, rbuf + 4, AVA4_AUC_VER_LEN); 865 ver[AVA4_AUC_VER_LEN] = '\0'; 866 867 applog(LOG_DEBUG, "%s-%d: USB2IIC Converter version: %s!", avalon4->drv->name, avalon4->device_id, ver); 868 return 0; 869 } 870 871 static int avalon4_auc_getinfo(struct cgpu_info *avalon4) 872 { 873 struct avalon4_iic_info iic_info; 874 int err, wlen, rlen; 875 uint8_t wbuf[AVA4_AUC_P_SIZE]; 876 uint8_t rbuf[AVA4_AUC_P_SIZE]; 877 uint8_t *pdata = rbuf + 4; 878 uint16_t adc_val; 879 struct avalon4_info *info = avalon4->device_data; 880 881 iic_info.iic_op = AVA4_IIC_INFO; 882 /* Device info: (9 bytes) 883 * tempadc(2), reqRdIndex, reqWrIndex, 884 * respRdIndex, respWrIndex, tx_flags, state 885 * */ 886 rlen = 7; 887 avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen); 888 889 memset(rbuf, 0, AVA4_AUC_P_SIZE); 890 err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen); 891 if (err) { 892 applog(LOG_ERR, "%s-%d: AUC Failed to get info ", avalon4->drv->name, avalon4->device_id); 893 return 1; 894 } 895 896 applog(LOG_DEBUG, "%s-%d: AUC tempADC(%03d), reqcnt(%d), respcnt(%d), txflag(%d), state(%d)", 897 avalon4->drv->name, avalon4->device_id, 898 pdata[1] << 8 | pdata[0], 899 pdata[2], 900 pdata[3], 901 pdata[5] << 8 | pdata[4], 902 pdata[6]); 903 904 adc_val = pdata[1] << 8 | pdata[0]; 905 906 info->auc_temp = 3.3 * adc_val * 10000 / 1023; 907 return 0; 908 } 909 910 static int avalon4_iic_xfer_pkg(struct cgpu_info *avalon4, uint8_t slave_addr, 911 const struct avalon4_pkg *pkg, struct avalon4_ret *ret) 912 { 913 struct avalon4_iic_info iic_info; 914 int err, wcnt, rcnt, rlen = 0; 915 uint8_t wbuf[AVA4_AUC_P_SIZE]; 916 uint8_t rbuf[AVA4_AUC_P_SIZE]; 917 918 struct avalon4_info *info = avalon4->device_data; 919 920 if (ret) 921 rlen = AVA4_READ_SIZE; 922 923 if (info->connecter == AVA4_CONNECTER_AUC) { 924 if (unlikely(avalon4->usbinfo.nodev)) 925 return AVA4_SEND_ERROR; 926 927 iic_info.iic_op = AVA4_IIC_XFER; 928 iic_info.iic_param.slave_addr = slave_addr; 929 930 avalon4_auc_init_pkg(wbuf, &iic_info, (uint8_t *)pkg, AVA4_WRITE_SIZE, rlen); 931 err = avalon4_auc_xfer(avalon4, wbuf, wbuf[0], &wcnt, rbuf, rlen, &rcnt); 932 if ((pkg->type != AVA4_P_DETECT) && err == -7 && !rcnt && rlen) { 933 avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen); 934 err = avalon4_auc_xfer(avalon4, wbuf, wbuf[0], &wcnt, rbuf, rlen, &rcnt); 935 applog(LOG_DEBUG, "%s-%d-%d: AUC read again!(type:0x%x, err:%d)", avalon4->drv->name, avalon4->device_id, slave_addr, pkg->type, err); 936 } 937 if (err || rcnt != rlen) { 938 if (info->xfer_err_cnt++ == 100) { 939 applog(LOG_DEBUG, "%s-%d-%d: AUC xfer_err_cnt reach err = %d, rcnt = %d, rlen = %d", 940 avalon4->drv->name, avalon4->device_id, slave_addr, 941 err, rcnt, rlen); 942 943 cgsleep_ms(5 * 1000); /* Wait MM reset */ 944 avalon4_auc_init(avalon4, info->auc_version); 945 } 946 return AVA4_SEND_ERROR; 947 } 948 949 if (ret) 950 memcpy((char *)ret, rbuf + 4, AVA4_READ_SIZE); 951 952 info->xfer_err_cnt = 0; 953 } 954 955 if (info->connecter == AVA4_CONNECTER_IIC) { 956 err = avalon4_iic_xfer(avalon4, slave_addr, (uint8_t *)pkg, AVA4_WRITE_SIZE, (uint8_t *)ret, AVA4_READ_SIZE); 957 if ((pkg->type != AVA4_P_DETECT) && err) { 958 err = avalon4_iic_xfer(avalon4, slave_addr, (uint8_t *)pkg, AVA4_WRITE_SIZE, (uint8_t *)ret, AVA4_READ_SIZE); 959 applog(LOG_DEBUG, "%s-%d-%d: IIC read again!(type:0x%x, err:%d)", avalon4->drv->name, avalon4->device_id, slave_addr, pkg->type, err); 960 } 961 if (err) { 962 /* FIXME: Don't care broadcast message with no reply, or it will block other thread when called by avalon4_send_bc_pkgs */ 963 if ((pkg->type != AVA4_P_DETECT) && (slave_addr == AVA4_MODULE_BROADCAST)) 964 return AVA4_SEND_OK; 965 966 if (info->xfer_err_cnt++ == 100) { 967 info->xfer_err_cnt = 0; 968 applog(LOG_DEBUG, "%s-%d-%d: IIC xfer_err_cnt reach err = %d, rcnt = %d, rlen = %d", 969 avalon4->drv->name, avalon4->device_id, slave_addr, 970 err, rcnt, rlen); 971 972 cgsleep_ms(5 * 1000); /* Wait MM reset */ 973 } 974 return AVA4_SEND_ERROR; 975 } 976 977 info->xfer_err_cnt = 0; 978 } 979 return AVA4_SEND_OK; 980 } 981 982 static int avalon4_send_bc_pkgs(struct cgpu_info *avalon4, const struct avalon4_pkg *pkg) 983 { 984 int ret; 985 986 do { 987 ret = avalon4_iic_xfer_pkg(avalon4, AVA4_MODULE_BROADCAST, pkg, NULL); 988 } while (ret != AVA4_SEND_OK); 989 990 return 0; 991 } 992 993 static void avalon4_stratum_pkgs(struct cgpu_info *avalon4, struct pool *pool) 994 { 995 struct avalon4_info *info = avalon4->device_data; 996 const int merkle_offset = 36; 997 struct avalon4_pkg pkg; 998 int i, a, b, tmp; 999 unsigned char target[32]; 1000 int job_id_len, n2size; 1001 unsigned short crc; 1002 1003 int coinbase_len_posthash, coinbase_len_prehash; 1004 uint8_t coinbase_prehash[32]; 1005 1006 /* Send out the first stratum message STATIC */ 1007 applog(LOG_DEBUG, "%s-%d: Pool stratum message STATIC: %d, %d, %d, %d, %d", 1008 avalon4->drv->name, avalon4->device_id, 1009 pool->coinbase_len, 1010 pool->nonce2_offset, 1011 pool->n2size, 1012 merkle_offset, 1013 pool->merkles); 1014 memset(pkg.data, 0, AVA4_P_DATA_LEN); 1015 tmp = be32toh(pool->coinbase_len); 1016 memcpy(pkg.data, &tmp, 4); 1017 1018 tmp = be32toh(pool->nonce2_offset); 1019 memcpy(pkg.data + 4, &tmp, 4); 1020 1021 n2size = pool->n2size >= 4 ? 4 : pool->n2size; 1022 tmp = be32toh(n2size); 1023 memcpy(pkg.data + 8, &tmp, 4); 1024 1025 tmp = be32toh(merkle_offset); 1026 memcpy(pkg.data + 12, &tmp, 4); 1027 1028 tmp = be32toh(pool->merkles); 1029 memcpy(pkg.data + 16, &tmp, 4); 1030 1031 tmp = be32toh((int)pool->swork.diff); 1032 memcpy(pkg.data + 20, &tmp, 4); 1033 1034 tmp = be32toh((int)pool->pool_no); 1035 memcpy(pkg.data + 24, &tmp, 4); 1036 1037 avalon4_init_pkg(&pkg, AVA4_P_STATIC, 1, 1); 1038 if (avalon4_send_bc_pkgs(avalon4, &pkg)) 1039 return; 1040 1041 if (pool->sdiff <= AVA4_DRV_DIFFMAX) 1042 set_target(target, pool->sdiff); 1043 else 1044 set_target(target, AVA4_DRV_DIFFMAX); 1045 1046 memcpy(pkg.data, target, 32); 1047 if (opt_debug) { 1048 char *target_str; 1049 target_str = bin2hex(target, 32); 1050 applog(LOG_DEBUG, "%s-%d: Pool stratum target: %s", avalon4->drv->name, avalon4->device_id, target_str); 1051 free(target_str); 1052 } 1053 avalon4_init_pkg(&pkg, AVA4_P_TARGET, 1, 1); 1054 if (avalon4_send_bc_pkgs(avalon4, &pkg)) 1055 return; 1056 1057 memset(pkg.data, 0, AVA4_P_DATA_LEN); 1058 1059 job_id_len = strlen(pool->swork.job_id); 1060 crc = crc16((unsigned char *)pool->swork.job_id, job_id_len); 1061 applog(LOG_DEBUG, "%s-%d: Pool stratum message JOBS_ID[%04x]: %s", 1062 avalon4->drv->name, avalon4->device_id, 1063 crc, pool->swork.job_id); 1064 1065 pkg.data[0] = (crc & 0xff00) >> 8; 1066 pkg.data[1] = crc & 0x00ff; 1067 avalon4_init_pkg(&pkg, AVA4_P_JOB_ID, 1, 1); 1068 if (avalon4_send_bc_pkgs(avalon4, &pkg)) 1069 return; 1070 1071 coinbase_len_prehash = pool->nonce2_offset - (pool->nonce2_offset % SHA256_BLOCK_SIZE); 1072 coinbase_len_posthash = pool->coinbase_len - coinbase_len_prehash; 1073 sha256_prehash(pool->coinbase, coinbase_len_prehash, coinbase_prehash); 1074 1075 a = (coinbase_len_posthash / AVA4_P_DATA_LEN) + 1; 1076 b = coinbase_len_posthash % AVA4_P_DATA_LEN; 1077 memcpy(pkg.data, coinbase_prehash, 32); 1078 avalon4_init_pkg(&pkg, AVA4_P_COINBASE, 1, a + (b ? 1 : 0)); 1079 if (avalon4_send_bc_pkgs(avalon4, &pkg)) 1080 return; 1081 applog(LOG_DEBUG, "%s-%d: Pool stratum message modified COINBASE: %d %d", 1082 avalon4->drv->name, avalon4->device_id, 1083 a, b); 1084 for (i = 1; i < a; i++) { 1085 memcpy(pkg.data, pool->coinbase + coinbase_len_prehash + i * 32 - 32, 32); 1086 avalon4_init_pkg(&pkg, AVA4_P_COINBASE, i + 1, a + (b ? 1 : 0)); 1087 if (avalon4_send_bc_pkgs(avalon4, &pkg)) 1088 return; 1089 } 1090 if (b) { 1091 memset(pkg.data, 0, AVA4_P_DATA_LEN); 1092 memcpy(pkg.data, pool->coinbase + coinbase_len_prehash + i * 32 - 32, b); 1093 avalon4_init_pkg(&pkg, AVA4_P_COINBASE, i + 1, i + 1); 1094 if (avalon4_send_bc_pkgs(avalon4, &pkg)) 1095 return; 1096 } 1097 1098 b = pool->merkles; 1099 applog(LOG_DEBUG, "%s-%d: Pool stratum message MERKLES: %d", avalon4->drv->name, avalon4->device_id, b); 1100 for (i = 0; i < b; i++) { 1101 memset(pkg.data, 0, AVA4_P_DATA_LEN); 1102 memcpy(pkg.data, pool->swork.merkle_bin[i], 32); 1103 avalon4_init_pkg(&pkg, AVA4_P_MERKLES, i + 1, b); 1104 if (avalon4_send_bc_pkgs(avalon4, &pkg)) 1105 return; 1106 } 1107 1108 applog(LOG_DEBUG, "%s-%d: Pool stratum message HEADER: 4", avalon4->drv->name, avalon4->device_id); 1109 for (i = 0; i < 4; i++) { 1110 memset(pkg.data, 0, AVA4_P_DATA_LEN); 1111 memcpy(pkg.data, pool->header_bin + i * 32, 32); 1112 avalon4_init_pkg(&pkg, AVA4_P_HEADER, i + 1, 4); 1113 if (avalon4_send_bc_pkgs(avalon4, &pkg)) 1114 return; 1115 } 1116 1117 if (info->connecter == AVA4_CONNECTER_AUC) 1118 avalon4_auc_getinfo(avalon4); 1119 } 1120 1121 static struct cgpu_info *avalon4_iic_detect(void) 1122 { 1123 int i; 1124 struct avalon4_info *info; 1125 struct cgpu_info *avalon4 = NULL; 1126 struct i2c_ctx *i2c_slave = NULL; 1127 1128 i2c_slave = i2c_slave_open(I2C_BUS, 0); 1129 if (!i2c_slave) { 1130 applog(LOG_ERR, "Avalon4 init iic failed\n"); 1131 return NULL; 1132 } 1133 1134 i2c_slave->exit(i2c_slave); 1135 i2c_slave = NULL; 1136 1137 avalon4 = cgcalloc(1, sizeof(*avalon4)); 1138 avalon4->drv = &avalon4_drv; 1139 avalon4->deven = DEV_ENABLED; 1140 avalon4->threads = 1; 1141 add_cgpu(avalon4); 1142 1143 applog(LOG_INFO, "%s-%d: Found at %s", avalon4->drv->name, avalon4->device_id, 1144 I2C_BUS); 1145 1146 avalon4->device_data = cgcalloc(sizeof(struct avalon4_info), 1); 1147 info = avalon4->device_data; 1148 1149 info->polling_first = 1; 1150 info->newnonce = 0; 1151 1152 for (i = 0; i < AVA4_DEFAULT_MODULARS; i++) { 1153 info->enable[i] = 0; 1154 info->mod_type[i] = AVA4_TYPE_NULL; 1155 info->fan_pct[i] = AVA4_DEFAULT_FAN_START; 1156 info->set_voltage[i] = opt_avalon4_voltage_min; 1157 memcpy(info->set_smart_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq)); 1158 memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq)); 1159 info->i2c_slaves[i] = i2c_slave_open(I2C_BUS, i); 1160 if (!info->i2c_slaves[i]) { 1161 applog(LOG_ERR, "Avalon4 init i2c slaves failed\n"); 1162 free(avalon4->device_data); 1163 avalon4->device_data = NULL; 1164 free(avalon4); 1165 avalon4 = NULL; 1166 return NULL; 1167 } 1168 } 1169 1170 info->enable[0] = 1; 1171 info->mod_type[0] = AVA4_TYPE_MM40; 1172 info->temp[0] = -273; 1173 1174 info->speed_bingo[0] = opt_avalon4_speed_bingo; 1175 info->speed_error[0] = opt_avalon4_speed_error; 1176 info->connecter = AVA4_CONNECTER_IIC; 1177 1178 return avalon4; 1179 } 1180 1181 static struct cgpu_info *avalon4_auc_detect(struct libusb_device *dev, struct usb_find_devices *found) 1182 { 1183 int i; 1184 struct avalon4_info *info; 1185 struct cgpu_info *avalon4 = usb_alloc_cgpu(&avalon4_drv, 1); 1186 char auc_ver[AVA4_AUC_VER_LEN]; 1187 1188 if (!usb_init(avalon4, dev, found)) { 1189 applog(LOG_ERR, "Avalon4 failed usb_init"); 1190 avalon4 = usb_free_cgpu(avalon4); 1191 return NULL; 1192 } 1193 1194 /* Avalon4 prefers not to use zero length packets */ 1195 avalon4->nozlp = true; 1196 1197 /* We try twice on AUC init */ 1198 if (avalon4_auc_init(avalon4, auc_ver) && avalon4_auc_init(avalon4, auc_ver)) 1199 return NULL; 1200 1201 /* We have an Avalon4 AUC connected */ 1202 avalon4->threads = 1; 1203 add_cgpu(avalon4); 1204 1205 update_usb_stats(avalon4); 1206 applog(LOG_INFO, "%s-%d: Found at %s", avalon4->drv->name, avalon4->device_id, 1207 avalon4->device_path); 1208 1209 avalon4->device_data = cgcalloc(sizeof(struct avalon4_info), 1); 1210 info = avalon4->device_data; 1211 memcpy(info->auc_version, auc_ver, AVA4_AUC_VER_LEN); 1212 info->auc_version[AVA4_AUC_VER_LEN] = '\0'; 1213 info->auc_speed = opt_avalon4_aucspeed; 1214 info->auc_xdelay = opt_avalon4_aucxdelay; 1215 1216 info->polling_first = 1; 1217 info->newnonce = 0; 1218 1219 for (i = 0; i < AVA4_DEFAULT_MODULARS; i++) { 1220 info->enable[i] = 0; 1221 info->mod_type[i] = AVA4_TYPE_NULL; 1222 info->fan_pct[i] = AVA4_DEFAULT_FAN_START; 1223 info->set_voltage[i] = opt_avalon4_voltage_min; 1224 memcpy(info->set_smart_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq)); 1225 memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq)); 1226 } 1227 1228 info->enable[0] = 1; 1229 info->mod_type[0] = AVA4_TYPE_MM40; 1230 info->temp[0] = -273; 1231 1232 info->speed_bingo[0] = opt_avalon4_speed_bingo; 1233 info->speed_error[0] = opt_avalon4_speed_error; 1234 info->connecter = AVA4_CONNECTER_AUC; 1235 return avalon4; 1236 } 1237 1238 static inline void avalon4_detect(bool __maybe_unused hotplug) 1239 { 1240 usb_detect(&avalon4_drv, avalon4_auc_detect); 1241 if (!hotplug && opt_avalon4_iic_detect) 1242 avalon4_iic_detect(); 1243 } 1244 1245 static bool avalon4_prepare(struct thr_info *thr) 1246 { 1247 int i; 1248 struct cgpu_info *avalon4 = thr->cgpu; 1249 struct avalon4_info *info = avalon4->device_data; 1250 1251 info->polling_first = 1; 1252 1253 memset(&(info->firsthash), 0, sizeof(info->firsthash)); 1254 cgtime(&(info->last_fan)); 1255 cgtime(&(info->last_30s)); 1256 cgtime(&(info->last_5s)); 1257 cgtime(&info->last_stratum); 1258 cgtime(&info->last_fadj); 1259 cgtime(&info->last_tcheck); 1260 1261 cglock_init(&info->update_lock); 1262 cglock_init(&info->pool0.data_lock); 1263 cglock_init(&info->pool1.data_lock); 1264 cglock_init(&info->pool2.data_lock); 1265 1266 for (i = 0; i < AVA4_DEFAULT_MODULARS; i++) 1267 info->fan_pct[i] = AVA4_DEFAULT_FAN_START; 1268 1269 switch (opt_avalon4_miningmode) { 1270 case AVA4_MOD_ECO: 1271 opt_avalon4_fan_min = 20; 1272 opt_avalon4_overheat = 60; 1273 break; 1274 case AVA4_MOD_NORMAL: 1275 opt_avalon4_fan_min = 30; 1276 opt_avalon4_overheat = 50; 1277 break; 1278 case AVA4_MOD_TURBO: 1279 opt_avalon4_fan_min = 60; 1280 opt_avalon4_overheat = 49; 1281 break; 1282 default: 1283 break; 1284 } 1285 1286 return true; 1287 } 1288 1289 static int check_module_exits(struct cgpu_info *avalon4, uint8_t mm_dna[AVA4_MM_DNA_LEN + 1]) 1290 { 1291 struct avalon4_info *info = avalon4->device_data; 1292 int i; 1293 1294 for (i = 0; i < AVA4_DEFAULT_MODULARS; i++) { 1295 if (info->enable[i]) { 1296 /* last byte is \0 */ 1297 if (!memcmp(info->mm_dna[i], mm_dna, AVA4_MM_DNA_LEN)) 1298 return 1; 1299 } 1300 } 1301 1302 return 0; 1303 } 1304 1305 static void detect_modules(struct cgpu_info *avalon4) 1306 { 1307 struct avalon4_info *info = avalon4->device_data; 1308 struct thr_info *thr = avalon4->thr[0]; 1309 1310 struct avalon4_pkg send_pkg; 1311 struct avalon4_ret ret_pkg; 1312 uint32_t tmp; 1313 int i, j, k, err; 1314 1315 /* Detect new modules here */ 1316 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 1317 if (info->enable[i]) 1318 continue; 1319 1320 /* Send out detect pkg */ 1321 applog(LOG_DEBUG, "%s-%d: AVA4_P_DETECT ID[%d]", 1322 avalon4->drv->name, avalon4->device_id, i); 1323 memset(send_pkg.data, 0, AVA4_P_DATA_LEN); 1324 tmp = be32toh(opt_avalon4_freq_min); 1325 memcpy(send_pkg.data, &tmp, 4); 1326 tmp = be32toh(opt_avalon4_freq_max); 1327 memcpy(send_pkg.data + 4, &tmp, 4); 1328 send_pkg.data[8] = opt_avalon4_ntcb >> 8; 1329 send_pkg.data[9] = opt_avalon4_ntcb & 0xff; 1330 tmp = be32toh(i); /* ID */ 1331 memcpy(send_pkg.data + 28, &tmp, 4); 1332 avalon4_init_pkg(&send_pkg, AVA4_P_DETECT, 1, 1); 1333 err = avalon4_iic_xfer_pkg(avalon4, AVA4_MODULE_BROADCAST, &send_pkg, &ret_pkg); 1334 if (err == AVA4_SEND_OK) { 1335 if (decode_pkg(thr, &ret_pkg, AVA4_MODULE_BROADCAST)) { 1336 applog(LOG_DEBUG, "%s-%d: Should be AVA4_P_ACKDETECT(%d), but %d", 1337 avalon4->drv->name, avalon4->device_id, AVA4_P_ACKDETECT, ret_pkg.type); 1338 continue; 1339 } 1340 } 1341 1342 if (err != AVA4_SEND_OK) { 1343 applog(LOG_DEBUG, "%s-%d: AVA4_P_DETECT: Failed AUC xfer data with err %d", 1344 avalon4->drv->name, avalon4->device_id, err); 1345 break; 1346 } 1347 1348 applog(LOG_DEBUG, "%s-%d: Module detect ID[%d]: %d", 1349 avalon4->drv->name, avalon4->device_id, i, ret_pkg.type); 1350 if (ret_pkg.type != AVA4_P_ACKDETECT) 1351 break; 1352 1353 if (check_module_exits(avalon4, ret_pkg.data)) 1354 continue; 1355 1356 cgtime(&info->elapsed[i]); 1357 cgtime(&info->last_finc[i]); 1358 cgtime(&info->last_fdec[i]); 1359 cgtime(&info->last_favg[i]); 1360 info->enable[i] = 1; 1361 memcpy(info->mm_dna[i], ret_pkg.data, AVA4_MM_DNA_LEN); 1362 info->mm_dna[i][AVA4_MM_DNA_LEN] = '\0'; 1363 memcpy(info->mm_version[i], ret_pkg.data + AVA4_MM_DNA_LEN, AVA4_MM_VER_LEN); 1364 memcpy(&tmp, ret_pkg.data + AVA4_MM_DNA_LEN + AVA4_MM_VER_LEN, 4); 1365 tmp = be32toh(tmp); 1366 info->mm_version[i][AVA4_MM_VER_LEN] = '\0'; 1367 info->miner_count[i] = AVA4_DEFAULT_MINER_CNT; 1368 info->asic_count[i] = AVA4_DEFAULT_ASIC_CNT; 1369 info->total_asics[i] = tmp; 1370 info->autov[i] = opt_avalon4_autov; 1371 info->toverheat[i] = opt_avalon4_overheat; 1372 if (info->toverheat[i] > AVA4_MM40_TEMP_OVERHEAT) 1373 info->toverheat[i] = AVA4_MM40_TEMP_OVERHEAT; 1374 info->temp_target[i] = opt_avalon4_temp_target; 1375 if (info->temp_target[i] > AVA4_MM40_TEMP_TARGET) 1376 info->temp_target[i] = AVA4_MM40_TEMP_TARGET; 1377 1378 if (!strncmp((char *)&(info->mm_version[i]), AVA4_MM40_PREFIXSTR, 2)) 1379 info->mod_type[i] = AVA4_TYPE_MM40; 1380 if (!strncmp((char *)&(info->mm_version[i]), AVA4_MM41_PREFIXSTR, 2)) 1381 info->mod_type[i] = AVA4_TYPE_MM41; 1382 if (!strncmp((char *)&(info->mm_version[i]), AVA4_MM50_PREFIXSTR, 2)) { 1383 info->miner_count[i] = AVA4_MM50_MINER_CNT; 1384 info->asic_count[i] = AVA4_MM50_ASIC_CNT; 1385 if (opt_avalon4_autov) 1386 applog(LOG_NOTICE, "%s-%d-%d: Module do not support autov", 1387 avalon4->drv->name, avalon4->device_id, i); 1388 info->autov[i] = false; 1389 info->mod_type[i] = AVA4_TYPE_MM50; 1390 } 1391 if (!strncmp((char *)&(info->mm_version[i]), AVA4_MM60_PREFIXSTR, 2)) { 1392 info->miner_count[i] = AVA4_MM60_MINER_CNT; 1393 info->asic_count[i] = AVA4_MM60_ASIC_CNT; 1394 if (opt_avalon4_autov) 1395 applog(LOG_NOTICE, "%s-%d-%d: Module do not support autov", 1396 avalon4->drv->name, avalon4->device_id, i); 1397 info->autov[i] = false; 1398 info->toverheat[i] = opt_avalon4_overheat; 1399 if (info->toverheat[i] > AVA4_DEFAULT_TEMP_OVERHEAT) 1400 info->toverheat[i] = AVA4_DEFAULT_TEMP_OVERHEAT; 1401 1402 info->temp_target[i] = opt_avalon4_temp_target; 1403 if (info->temp_target[i] > AVA4_DEFAULT_TEMP_TARGET) 1404 info->temp_target[i] = AVA4_DEFAULT_TEMP_TARGET; 1405 info->mod_type[i] = AVA4_TYPE_MM60; 1406 } 1407 info->ntime_offset[i] = (opt_avalon4_ntime_offset > info->asic_count[i]) ? info->asic_count[i] : opt_avalon4_ntime_offset; 1408 info->fan_pct[i] = AVA4_DEFAULT_FAN_START; 1409 info->set_voltage[i] = opt_avalon4_voltage_min; 1410 for (j = 0; j < info->miner_count[i]; j++) { 1411 info->set_voltage_i[i][j] = opt_avalon4_voltage_min; 1412 info->set_voltage_offset[i][j] = 0; 1413 info->adjflag[i][j] = 0; 1414 memset(info->ma_sum[i][j], 0, sizeof(uint8_t) * info->asic_count[i]); 1415 1416 for (k = 0; k < info->asic_count[i]; k++) 1417 memset(info->set_frequency_i[i][j][k], 0, sizeof(int) * 3); 1418 } 1419 info->led_red[i] = 0; 1420 for (j = 0; j < AVA4_DEFAULT_ADC_MAX; j++) 1421 info->adc[i][j] = AVA4_ADC_MAX; 1422 memset(info->pll_sel, 0, sizeof(info->pll_sel)); 1423 info->saved[i] = 0; 1424 info->cutoff[i] = 0; 1425 info->get_frequency[i] = 0; 1426 memcpy(info->set_smart_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq)); 1427 info->speed_bingo[i] = opt_avalon4_speed_bingo; 1428 info->speed_error[i] = opt_avalon4_speed_error; 1429 info->freq_mode[i] = AVA4_FREQ_INIT_MODE; 1430 applog(LOG_NOTICE, "%s-%d: New module detect! ID[%d]", 1431 avalon4->drv->name, avalon4->device_id, i); 1432 1433 if (opt_avalon4_miningmode != AVA4_MOD_CUSTOM) { 1434 applog(LOG_DEBUG, "%s-%d-%d: Load mm config", 1435 avalon4->drv->name, avalon4->device_id, i); 1436 1437 memset(send_pkg.data, 0, AVA4_P_DATA_LEN); 1438 avalon4_init_pkg(&send_pkg, AVA4_P_GET_VOLT, 1, 1); 1439 send_pkg.opt = ((1 << 4) | opt_avalon4_miningmode); 1440 err = avalon4_iic_xfer_pkg(avalon4, i, &send_pkg, &ret_pkg); 1441 if (err == AVA4_SEND_OK) { 1442 err = decode_pkg(thr, &ret_pkg, i); 1443 if (err == 0 && ret_pkg.type == AVA4_P_STATUS_VOLT) { 1444 applog(LOG_DEBUG, "%s-%d-%d: Load mm config success", 1445 avalon4->drv->name, avalon4->device_id, i); 1446 1447 for (j = 0; j < info->miner_count[i]; j++) { 1448 applog(LOG_DEBUG, "%s-%d-%d: vol-%d = %d", 1449 avalon4->drv->name, avalon4->device_id, i, 1450 j, info->get_voltage_i[i][j]); 1451 1452 info->set_voltage_i[i][j] = info->get_voltage_i[i][j]; 1453 } 1454 } else { 1455 applog(LOG_DEBUG, "%s-%d-%d: Load mm config invalid! err = %d, ret_pkg.type 0x%x", 1456 avalon4->drv->name, avalon4->device_id, i, 1457 err, ret_pkg.type); 1458 } 1459 } else { 1460 applog(LOG_DEBUG, "%s-%d-%d: Load mm config failed!", 1461 avalon4->drv->name, avalon4->device_id, i); 1462 } 1463 } 1464 } 1465 } 1466 1467 static void detach_module(struct cgpu_info *avalon4, int addr) 1468 { 1469 struct avalon4_info *info = avalon4->device_data; 1470 int i, j; 1471 1472 info->polling_err_cnt[addr] = 0; 1473 info->mod_type[addr] = AVA4_TYPE_NULL; 1474 info->enable[addr] = 0; 1475 info->get_voltage[addr] = 0; 1476 info->get_frequency[addr] = 0; 1477 info->power_good[addr] = 0; 1478 info->error_code[addr] = 0; 1479 info->local_work[addr] = 0; 1480 info->local_works[addr] = 0; 1481 info->hw_work[addr] = 0; 1482 info->hw_works[addr] = 0; 1483 info->total_asics[addr] = 0; 1484 info->toverheat[addr] = opt_avalon4_overheat; 1485 info->temp_target[addr] = opt_avalon4_temp_target; 1486 info->speed_bingo[addr] = opt_avalon4_speed_bingo; 1487 info->speed_error[addr] = opt_avalon4_speed_error; 1488 memset(info->set_frequency[addr], 0, sizeof(int) * 3); 1489 for (i = 0; i < AVA4_DEFAULT_ADJ_TIMES; i++) { 1490 info->lw5[addr][i] = 0; 1491 info->hw5[addr][i] = 0; 1492 } 1493 1494 for (i = 0; i < info->miner_count[addr]; i++) { 1495 info->matching_work[addr][i] = 0; 1496 memset(info->chipmatching_work[addr][i], 0, sizeof(int) * info->asic_count[addr]); 1497 info->local_works_i[addr][i] = 0; 1498 info->hw_works_i[addr][i] = 0; 1499 memset(info->lw5_i[addr][i], 0, AVA4_DEFAULT_ADJ_TIMES * sizeof(uint32_t)); 1500 memset(info->hw5_i[addr][i], 0, AVA4_DEFAULT_ADJ_TIMES * sizeof(uint32_t)); 1501 memset(info->ma_sum[addr][i], 0, sizeof(uint8_t) * info->asic_count[addr]); 1502 for (j = 0; j < info->asic_count[addr]; j++) 1503 memset(info->set_frequency_i[addr][i][j], 0, sizeof(int) * 3); 1504 } 1505 info->freq_mode[addr] = AVA4_FREQ_INIT_MODE; 1506 applog(LOG_NOTICE, "%s-%d: Module detached! ID[%d]", 1507 avalon4->drv->name, avalon4->device_id, addr); 1508 } 1509 1510 static int polling(struct cgpu_info *avalon4) 1511 { 1512 struct avalon4_info *info = avalon4->device_data; 1513 struct thr_info *thr = avalon4->thr[0]; 1514 struct avalon4_pkg send_pkg; 1515 struct avalon4_ret ar; 1516 int i, tmp, ret, decode_err = 0, do_polling = 0; 1517 struct timeval current_fan; 1518 int do_adjust_fan = 0; 1519 uint32_t fan_pwm; 1520 double device_tdiff; 1521 1522 if (info->polling_first) { 1523 cgsleep_ms(600); 1524 info->polling_first = 0; 1525 } 1526 1527 cgtime(¤t_fan); 1528 device_tdiff = tdiff(¤t_fan, &(info->last_fan)); 1529 if (device_tdiff > 2.0 || device_tdiff < 0) { 1530 cgtime(&info->last_fan); 1531 do_adjust_fan = 1; 1532 } 1533 1534 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 1535 if (!info->enable[i]) 1536 continue; 1537 1538 do_polling = 1; 1539 cgsleep_ms(opt_avalon4_polling_delay); 1540 1541 memset(send_pkg.data, 0, AVA4_P_DATA_LEN); 1542 /* Red LED */ 1543 tmp = be32toh(info->led_red[i]); 1544 memcpy(send_pkg.data, &tmp, 4); 1545 1546 /* Adjust fan every 10 seconds*/ 1547 if (do_adjust_fan) { 1548 fan_pwm = adjust_fan(info, i); 1549 fan_pwm |= 0x80000000; 1550 tmp = be32toh(fan_pwm); 1551 memcpy(send_pkg.data + 4, &tmp, 4); 1552 } 1553 1554 avalon4_init_pkg(&send_pkg, AVA4_P_POLLING, 1, 1); 1555 ret = avalon4_iic_xfer_pkg(avalon4, i, &send_pkg, &ar); 1556 if (ret == AVA4_SEND_OK) 1557 decode_err = decode_pkg(thr, &ar, i); 1558 1559 if (ret != AVA4_SEND_OK || decode_err) { 1560 info->polling_err_cnt[i]++; 1561 memset(send_pkg.data, 0, AVA4_P_DATA_LEN); 1562 avalon4_init_pkg(&send_pkg, AVA4_P_RSTMMTX, 1, 1); 1563 avalon4_iic_xfer_pkg(avalon4, i, &send_pkg, NULL); 1564 if (info->polling_err_cnt[i] >= 4) 1565 detach_module(avalon4, i); 1566 } 1567 1568 if (ret == AVA4_SEND_OK && !decode_err) { 1569 info->polling_err_cnt[i] = 0; 1570 1571 if (info->mm_dna[i][AVA4_MM_DNA_LEN - 1] != ar.opt) { 1572 applog(LOG_ERR, "%s-%d-%d: Dup address found %d-%d", 1573 avalon4->drv->name, avalon4->device_id, i, 1574 info->mm_dna[i][AVA4_MM_DNA_LEN - 1], ar.opt); 1575 hexdump((uint8_t *)&ar, sizeof(ar)); 1576 detach_module(avalon4, i); 1577 } 1578 } 1579 } 1580 1581 if (!do_polling) 1582 detect_modules(avalon4); 1583 1584 return 0; 1585 } 1586 1587 static void copy_pool_stratum(struct pool *pool_stratum, struct pool *pool) 1588 { 1589 int i; 1590 int merkles = pool->merkles, job_id_len; 1591 size_t coinbase_len = pool->coinbase_len; 1592 unsigned short crc; 1593 1594 if (!pool->swork.job_id) 1595 return; 1596 1597 if (pool_stratum->swork.job_id) { 1598 job_id_len = strlen(pool->swork.job_id); 1599 crc = crc16((unsigned char *)pool->swork.job_id, job_id_len); 1600 job_id_len = strlen(pool_stratum->swork.job_id); 1601 1602 if (crc16((unsigned char *)pool_stratum->swork.job_id, job_id_len) == crc) 1603 return; 1604 } 1605 1606 cg_wlock(&pool_stratum->data_lock); 1607 free(pool_stratum->swork.job_id); 1608 free(pool_stratum->nonce1); 1609 free(pool_stratum->coinbase); 1610 1611 pool_stratum->coinbase = cgcalloc(coinbase_len, 1); 1612 memcpy(pool_stratum->coinbase, pool->coinbase, coinbase_len); 1613 1614 for (i = 0; i < pool_stratum->merkles; i++) 1615 free(pool_stratum->swork.merkle_bin[i]); 1616 if (merkles) { 1617 pool_stratum->swork.merkle_bin = cgrealloc(pool_stratum->swork.merkle_bin, 1618 sizeof(char *) * merkles + 1); 1619 for (i = 0; i < merkles; i++) { 1620 pool_stratum->swork.merkle_bin[i] = cgmalloc(32); 1621 memcpy(pool_stratum->swork.merkle_bin[i], pool->swork.merkle_bin[i], 32); 1622 } 1623 } 1624 1625 pool_stratum->sdiff = pool->sdiff; 1626 pool_stratum->coinbase_len = pool->coinbase_len; 1627 pool_stratum->nonce2_offset = pool->nonce2_offset; 1628 pool_stratum->n2size = pool->n2size; 1629 pool_stratum->merkles = pool->merkles; 1630 1631 pool_stratum->swork.job_id = strdup(pool->swork.job_id); 1632 pool_stratum->nonce1 = strdup(pool->nonce1); 1633 1634 memcpy(pool_stratum->ntime, pool->ntime, sizeof(pool_stratum->ntime)); 1635 memcpy(pool_stratum->header_bin, pool->header_bin, sizeof(pool_stratum->header_bin)); 1636 cg_wunlock(&pool_stratum->data_lock); 1637 } 1638 1639 static inline int mm_cmp_1512(struct avalon4_info *info, int addr) 1640 { 1641 /* >= 1512 return 1 */ 1642 return strncmp(info->mm_version[addr] + 2, "1512", 4) >= 0 ? 1 : 0; 1643 } 1644 1645 static inline int mm_cmp_1501(struct avalon4_info *info, int addr) 1646 { 1647 /* >= 1501 return 1 */ 1648 return strncmp(info->mm_version[addr] + 2, "1501", 4) >= 0 ? 1 : 0; 1649 } 1650 1651 static inline int mm_cmp_d17f4a(struct avalon4_info *info, int addr) 1652 { 1653 /* == d17f4a return 1 */ 1654 return strncmp(info->mm_version[addr] + 7, "d17f4a", 6) == 0 ? 1 : 0; 1655 } 1656 1657 static void avalon4_set_voltage(struct cgpu_info *avalon4, int addr, int opt) 1658 { 1659 struct avalon4_info *info = avalon4->device_data; 1660 struct avalon4_pkg send_pkg; 1661 uint16_t tmp; 1662 uint8_t i; 1663 1664 memset(send_pkg.data, 0, AVA4_P_DATA_LEN); 1665 1666 /* Use shifter to set voltage */ 1667 for (i = 0; i < info->miner_count[addr]; i++) { 1668 tmp = info->set_voltage_i[addr][i] + info->set_voltage_offset[addr][i]; 1669 if (avalon4_freezsafemode) 1670 tmp = AVA4_FREEZESAFE_VOLTAGE; 1671 1672 if (info->cutoff[addr]) 1673 tmp = 0; 1674 1675 if (info->mod_type[addr] == AVA4_TYPE_MM40) 1676 tmp = encode_voltage_adp3208d(tmp); 1677 if (info->mod_type[addr] == AVA4_TYPE_MM41) 1678 tmp = encode_voltage_ncp5392p(tmp); 1679 if (info->mod_type[addr] == AVA4_TYPE_MM50) 1680 tmp = encode_voltage_ncp5392p(tmp); 1681 /* TODO: fix it with the actual board */ 1682 if (info->mod_type[addr] == AVA4_TYPE_MM60) 1683 tmp = encode_voltage_ncp5392p(tmp); 1684 1685 tmp = htobe16(tmp); 1686 memcpy(send_pkg.data + 2 * ((4 + i / 5 * 5) - i + (i / 5 * 5)), &tmp, 2); 1687 } 1688 1689 /* Package the data */ 1690 avalon4_init_pkg(&send_pkg, AVA4_P_SET_VOLT, 1, 1); 1691 send_pkg.opt = opt; 1692 if (addr == AVA4_MODULE_BROADCAST) 1693 avalon4_send_bc_pkgs(avalon4, &send_pkg); 1694 else 1695 avalon4_iic_xfer_pkg(avalon4, addr, &send_pkg, NULL); 1696 } 1697 1698 static uint32_t avalon4_get_cpm(unsigned int freq) 1699 { 1700 unsigned int i; 1701 1702 for (i = 0; i < sizeof(g_freq_array) / sizeof(g_freq_array[0]); i++) 1703 if (freq >= g_freq_array[i][0] && freq < g_freq_array[i+1][0]) 1704 return g_freq_array[i][1]; 1705 1706 /* return the lowest freq if not found */ 1707 return g_freq_array[0][1]; 1708 } 1709 1710 static void avalon4_set_freq(struct cgpu_info *avalon4, int addr, uint8_t miner_id, uint8_t chip_id, unsigned int freq[]) 1711 { 1712 struct avalon4_info *info = avalon4->device_data; 1713 struct avalon4_pkg send_pkg; 1714 uint32_t tmp; 1715 uint8_t set = 0; 1716 int i, j; 1717 1718 /* Note: 0 (miner_id and chip_id) is reserved for all devices */ 1719 if (!miner_id || !chip_id) { 1720 if (memcmp(freq, info->set_frequency[addr], sizeof(int) * 3) || !info->get_frequency[addr]) { 1721 memcpy(info->set_frequency[addr], freq, sizeof(int) * 3); 1722 for (i = 0; i < info->miner_count[addr]; i++) { 1723 for (j = 0; j < info->asic_count[addr]; j++) 1724 memcpy(info->set_frequency_i[addr][i][j], info->set_frequency[addr], sizeof(int) * 3); 1725 } 1726 set = 1; 1727 } 1728 } else { 1729 if (memcmp(freq, info->set_frequency_i[addr][miner_id - 1][chip_id - 1], sizeof(int) * 3)) { 1730 memcpy(info->set_frequency_i[addr][miner_id - 1][chip_id - 1], freq, sizeof(int) * 3); 1731 set = 1; 1732 } 1733 } 1734 1735 if (avalon4_freezsafemode) { 1736 info->set_frequency[addr][0] = info->set_frequency[addr][1] = info->set_frequency[addr][2] = AVA4_FREEZESAFE_FREQUENCY; 1737 memcpy(freq, info->set_frequency[addr], sizeof(int) * 3); 1738 miner_id = 0; 1739 chip_id = 0; 1740 set = 1; 1741 } 1742 1743 if (info->cutoff[addr]) { 1744 info->set_frequency[addr][0] = AVA4_DEFAULT_FREQUENCY_MIN; 1745 info->set_frequency[addr][1] = AVA4_DEFAULT_FREQUENCY_MIN; 1746 info->set_frequency[addr][2] = AVA4_DEFAULT_FREQUENCY_MIN; 1747 memcpy(freq, info->set_frequency[addr], sizeof(int) * 3); 1748 miner_id = 0; 1749 chip_id = 0; 1750 set = 1; 1751 } 1752 1753 if (!set) 1754 return; 1755 1756 memset(send_pkg.data, 0, AVA4_P_DATA_LEN); 1757 if (info->mod_type[addr] == AVA4_TYPE_MM60) { 1758 tmp = be32toh(freq[0]); 1759 memcpy(send_pkg.data, &tmp, 4); 1760 tmp = be32toh(freq[1]); 1761 memcpy(send_pkg.data + 4, &tmp, 4); 1762 tmp = be32toh(freq[2]); 1763 memcpy(send_pkg.data + 8, &tmp, 4); 1764 } else { 1765 tmp = avalon4_get_cpm(freq[0]); 1766 tmp = be32toh(tmp); 1767 memcpy(send_pkg.data, &tmp, 4); 1768 tmp = avalon4_get_cpm(freq[1]); 1769 tmp = be32toh(tmp); 1770 memcpy(send_pkg.data + 4, &tmp, 4); 1771 tmp = avalon4_get_cpm(freq[2]); 1772 tmp = be32toh(tmp); 1773 memcpy(send_pkg.data + 8, &tmp, 4); 1774 } 1775 applog(LOG_DEBUG, "%s-%d-%d: avalon4 set freq (%d-%d-%d)", 1776 avalon4->drv->name, avalon4->device_id, addr, 1777 freq[0], 1778 freq[1], 1779 freq[2]); 1780 send_pkg.data[12] = miner_id; 1781 1782 /* Package the data */ 1783 avalon4_init_pkg(&send_pkg, AVA4_P_SET_FREQ, 1, 1); 1784 send_pkg.opt = chip_id; 1785 1786 if (addr == AVA4_MODULE_BROADCAST) 1787 avalon4_send_bc_pkgs(avalon4, &send_pkg); 1788 else 1789 avalon4_iic_xfer_pkg(avalon4, addr, &send_pkg, NULL); 1790 } 1791 1792 static void avalon4_stratum_set(struct cgpu_info *avalon4, struct pool *pool, int addr) 1793 { 1794 struct avalon4_info *info = avalon4->device_data; 1795 struct avalon4_pkg send_pkg; 1796 uint32_t tmp = 0, range, start, volt; 1797 1798 /* Set the NTime, Voltage and Frequency */ 1799 memset(send_pkg.data, 0, AVA4_P_DATA_LEN); 1800 1801 if (info->ntime_offset[addr] != info->asic_count[addr]) { 1802 tmp = info->ntime_offset[addr] | 0x80000000; 1803 tmp = be32toh(tmp); 1804 memcpy(send_pkg.data, &tmp, 4); 1805 } 1806 1807 volt = info->set_voltage[addr]; 1808 if (avalon4_freezsafemode) 1809 volt = AVA4_FREEZESAFE_VOLTAGE; 1810 1811 if (info->cutoff[addr]) 1812 volt = 0; 1813 1814 if (info->mod_type[addr] == AVA4_TYPE_MM40) 1815 tmp = encode_voltage_adp3208d(volt); 1816 if (info->mod_type[addr] == AVA4_TYPE_MM41) 1817 tmp = encode_voltage_ncp5392p(volt); 1818 if (info->mod_type[addr] == AVA4_TYPE_MM50) 1819 tmp = encode_voltage_ncp5392p(volt); 1820 /* TODO: fix it with the actual board */ 1821 if (info->mod_type[addr] == AVA4_TYPE_MM60) 1822 tmp = encode_voltage_ncp5392p(volt); 1823 tmp = be32toh(tmp); 1824 memcpy(send_pkg.data + 4, &tmp, 4); 1825 1826 tmp = info->set_frequency[addr][0] | (info->set_frequency[addr][1] << 10) | (info->set_frequency[addr][2] << 20); 1827 if (avalon4_freezsafemode) 1828 tmp = AVA4_FREEZESAFE_FREQUENCY | (AVA4_FREEZESAFE_FREQUENCY << 10) | (AVA4_FREEZESAFE_FREQUENCY << 20); 1829 1830 if (info->cutoff[addr]) 1831 tmp = AVA4_DEFAULT_FREQUENCY_MIN | (AVA4_DEFAULT_FREQUENCY_MIN << 10) | (AVA4_DEFAULT_FREQUENCY_MIN << 20); 1832 1833 tmp = be32toh(tmp); 1834 memcpy(send_pkg.data + 8, &tmp, 4); 1835 1836 /* Configure the nonce2 offset and range */ 1837 if (pool->n2size == 3) 1838 range = 0xffffff / (total_devices ? total_devices : 1); 1839 else 1840 range = 0xffffffff / (total_devices ? total_devices : 1); 1841 start = range * avalon4->device_id; 1842 1843 tmp = be32toh(start); 1844 memcpy(send_pkg.data + 12, &tmp, 4); 1845 1846 tmp = be32toh(range); 1847 memcpy(send_pkg.data + 16, &tmp, 4); 1848 1849 /* adjust flag [0-5]: reserved, 6: nonce check, 7: autof*/ 1850 tmp = 1; 1851 if (!opt_avalon4_smart_speed) 1852 tmp = 0; 1853 if (opt_avalon4_noncecheck) 1854 tmp |= 2; 1855 send_pkg.data[20] = tmp & 0xff; 1856 send_pkg.data[21] = info->speed_bingo[addr]; 1857 send_pkg.data[22] = info->speed_error[addr]; 1858 1859 /* Package the data */ 1860 avalon4_init_pkg(&send_pkg, AVA4_P_SET, 1, 1); 1861 if (addr == AVA4_MODULE_BROADCAST) 1862 avalon4_send_bc_pkgs(avalon4, &send_pkg); 1863 else 1864 avalon4_iic_xfer_pkg(avalon4, addr, &send_pkg, NULL); 1865 } 1866 1867 static void avalon4_stratum_finish(struct cgpu_info *avalon4) 1868 { 1869 struct avalon4_pkg send_pkg; 1870 1871 memset(send_pkg.data, 0, AVA4_P_DATA_LEN); 1872 avalon4_init_pkg(&send_pkg, AVA4_P_FINISH, 1, 1); 1873 avalon4_send_bc_pkgs(avalon4, &send_pkg); 1874 } 1875 1876 static void avalon4_adjust_vf(struct cgpu_info *avalon4, int addr, uint8_t save) 1877 { 1878 struct avalon4_info *info = avalon4->device_data; 1879 1880 if (info->mod_type[addr] == AVA4_TYPE_MM50) { 1881 avalon4_set_voltage(avalon4, addr, ((save << 4) | opt_avalon4_miningmode)); 1882 avalon4_set_freq(avalon4, addr, 0, 0, opt_avalon4_freq); 1883 } 1884 1885 if ((info->mod_type[addr] == AVA4_TYPE_MM41) && 1886 mm_cmp_1501(info, addr)) { 1887 avalon4_set_voltage(avalon4, addr, ((save << 4) | opt_avalon4_miningmode)); 1888 avalon4_set_freq(avalon4, addr, 0, 0, opt_avalon4_freq); 1889 } 1890 1891 if ((info->mod_type[addr] == AVA4_TYPE_MM40) && 1892 mm_cmp_1501(info, addr)) { 1893 if (!mm_cmp_d17f4a(info, addr)) { 1894 avalon4_set_voltage(avalon4, addr, ((save << 4) | opt_avalon4_miningmode)); 1895 avalon4_set_freq(avalon4, addr, 0, 0, opt_avalon4_freq); 1896 } 1897 } 1898 } 1899 1900 static void avalon4_freq_inc(struct cgpu_info *avalon4, int addr, unsigned int freq[], unsigned int val) 1901 { 1902 struct avalon4_info *info = avalon4->device_data; 1903 int i; 1904 1905 if (info->mod_type[addr] == AVA4_TYPE_MM60) { 1906 for (i = 0; i < 3; i++) { 1907 if ((freq[i] + val) < AVA4_MM60_FREQUENCY_MAX) 1908 freq[i] += val; 1909 else 1910 freq[i] = AVA4_MM60_FREQUENCY_MAX; 1911 } 1912 } 1913 } 1914 1915 static void avalon4_freq_dec(struct cgpu_info *avalon4, int addr, unsigned int freq[], unsigned int val) 1916 { 1917 struct avalon4_info *info = avalon4->device_data; 1918 int i; 1919 1920 if (info->mod_type[addr] == AVA4_TYPE_MM60) { 1921 for (i = 0; i < 3; i++) { 1922 if (freq[i] <= val) { 1923 freq[i] = AVA4_DEFAULT_FREQUENCY_MIN; 1924 continue; 1925 } 1926 1927 if ((freq[i] - val) >= AVA4_DEFAULT_FREQUENCY_MIN) 1928 freq[i] -= val; 1929 else 1930 freq[i] = AVA4_DEFAULT_FREQUENCY_MIN; 1931 } 1932 } 1933 } 1934 1935 static void avalon4_update(struct cgpu_info *avalon4) 1936 { 1937 struct avalon4_info *info = avalon4->device_data; 1938 struct thr_info *thr = avalon4->thr[0]; 1939 struct work *work; 1940 struct pool *pool; 1941 int coinbase_len_posthash, coinbase_len_prehash; 1942 int i; 1943 int max_temp; 1944 1945 applog(LOG_DEBUG, "%s-%d: New stratum: restart: %d, update: %d", 1946 avalon4->drv->name, avalon4->device_id, 1947 thr->work_restart, thr->work_update); 1948 thr->work_update = false; 1949 thr->work_restart = false; 1950 1951 /* Step 1: Make sure pool is ready */ 1952 work = get_work(thr, thr->id); 1953 discard_work(work); /* Don't leak memory */ 1954 1955 /* Step 2: MM protocol check */ 1956 pool = current_pool(); 1957 if (!pool->has_stratum) 1958 quit(1, "%s-%d: MM has to use stratum pools", avalon4->drv->name, avalon4->device_id); 1959 1960 coinbase_len_prehash = pool->nonce2_offset - (pool->nonce2_offset % SHA256_BLOCK_SIZE); 1961 coinbase_len_posthash = pool->coinbase_len - coinbase_len_prehash; 1962 1963 if (coinbase_len_posthash + SHA256_BLOCK_SIZE > AVA4_P_COINBASE_SIZE) { 1964 applog(LOG_ERR, "%s-%d: MM pool modified coinbase length(%d) is more than %d", 1965 avalon4->drv->name, avalon4->device_id, 1966 coinbase_len_posthash + SHA256_BLOCK_SIZE, AVA4_P_COINBASE_SIZE); 1967 return; 1968 } 1969 if (pool->merkles > AVA4_P_MERKLES_COUNT) { 1970 applog(LOG_ERR, "%s-%d: MM merkles has to be less then %d", avalon4->drv->name, avalon4->device_id, AVA4_P_MERKLES_COUNT); 1971 return; 1972 } 1973 if (pool->n2size < 3) { 1974 applog(LOG_ERR, "%s-%d: MM nonce2 size has to be >= 3 (%d)", avalon4->drv->name, avalon4->device_id, pool->n2size); 1975 return; 1976 } 1977 1978 cg_wlock(&info->update_lock); 1979 /* Step 3: Try to detect new modules */ 1980 detect_modules(avalon4); 1981 1982 /* Step 4: Send out stratum pkgs */ 1983 cg_rlock(&pool->data_lock); 1984 cgtime(&info->last_stratum); 1985 info->pool_no = pool->pool_no; 1986 copy_pool_stratum(&info->pool2, &info->pool1); 1987 copy_pool_stratum(&info->pool1, &info->pool0); 1988 copy_pool_stratum(&info->pool0, pool); 1989 1990 avalon4_stratum_pkgs(avalon4, pool); 1991 cg_runlock(&pool->data_lock); 1992 1993 /* Step 5: Configure the parameter from outside */ 1994 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 1995 if (!info->enable[i]) 1996 continue; 1997 1998 max_temp = get_temp_max(info, i); 1999 if (max_temp >= info->toverheat[i]) 2000 info->cutoff[i] = 1; 2001 2002 if (info->cutoff[i] && (max_temp <= (info->toverheat[i] - 10))) 2003 info->cutoff[i] = 0; 2004 2005 if (info->cutoff[i]) 2006 info->polling_first = 1; 2007 2008 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2009 switch (info->freq_mode[i]) { 2010 case AVA4_FREQ_INIT_MODE: 2011 memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq)); 2012 memcpy(info->set_smart_frequency[i], info->set_frequency[i], sizeof(info->set_frequency[i])); 2013 if (info->cutoff[i]) { 2014 info->set_frequency[i][0] = AVA4_DEFAULT_FREQUENCY_MIN; 2015 info->set_frequency[i][1] = AVA4_DEFAULT_FREQUENCY_MIN; 2016 info->set_frequency[i][2] = AVA4_DEFAULT_FREQUENCY_MIN; 2017 info->freq_mode[i] = AVA4_FREQ_CUTOFF_MODE; 2018 break; 2019 } 2020 if (mm_cmp_1512(info, i) && (opt_avalon4_smart_speed != AVA4_DEFAULT_SMARTSPEED_OFF)) 2021 info->freq_mode[i] = AVA4_FREQ_PLLADJ_MODE; 2022 break; 2023 case AVA4_FREQ_CUTOFF_MODE: 2024 info->set_frequency[i][0] = AVA4_DEFAULT_FREQUENCY_MIN; 2025 info->set_frequency[i][1] = AVA4_DEFAULT_FREQUENCY_MIN; 2026 info->set_frequency[i][2] = AVA4_DEFAULT_FREQUENCY_MIN; 2027 if (!info->cutoff[i]) { 2028 memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq)); 2029 memcpy(info->set_smart_frequency[i], info->set_frequency[i], sizeof(info->set_frequency[i])); 2030 info->freq_mode[i] = AVA4_FREQ_INIT_MODE; 2031 } 2032 break; 2033 case AVA4_FREQ_TEMPADJ_MODE: 2034 if (info->cutoff[i]) { 2035 info->set_frequency[i][0] = AVA4_DEFAULT_FREQUENCY_MIN; 2036 info->set_frequency[i][1] = AVA4_DEFAULT_FREQUENCY_MIN; 2037 info->set_frequency[i][2] = AVA4_DEFAULT_FREQUENCY_MIN; 2038 info->freq_mode[i] = AVA4_FREQ_CUTOFF_MODE; 2039 break; 2040 } 2041 2042 if (get_temp_max(info, i) <= (info->temp_target[i] - opt_avalon4_delta_temp)) { 2043 memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq)); 2044 memcpy(info->set_smart_frequency[i], info->set_frequency[i], sizeof(info->set_frequency[i])); 2045 info->freq_mode[i] = AVA4_FREQ_INIT_MODE; 2046 break; 2047 } 2048 /* Adjust frequency when scanhash */ 2049 break; 2050 case AVA4_FREQ_PLLADJ_MODE: 2051 if (info->cutoff[i]) { 2052 info->set_frequency[i][0] = AVA4_DEFAULT_FREQUENCY_MIN; 2053 info->set_frequency[i][1] = AVA4_DEFAULT_FREQUENCY_MIN; 2054 info->set_frequency[i][2] = AVA4_DEFAULT_FREQUENCY_MIN; 2055 info->freq_mode[i] = AVA4_FREQ_CUTOFF_MODE; 2056 break; 2057 } 2058 2059 break; 2060 default: 2061 applog(LOG_ERR, "%s-%d-%d: Invalid frequency mode %d", 2062 avalon4->drv->name, avalon4->device_id, i, info->freq_mode[i]); 2063 break; 2064 } 2065 avalon4_stratum_set(avalon4, pool, i); 2066 } else { 2067 avalon4_stratum_set(avalon4, pool, i); 2068 avalon4_adjust_vf(avalon4, i, 0); 2069 } 2070 } 2071 2072 /* Step 6: Send out finish pkg */ 2073 avalon4_stratum_finish(avalon4); 2074 cg_wunlock(&info->update_lock); 2075 } 2076 2077 static int64_t avalon4_scanhash(struct thr_info *thr) 2078 { 2079 struct cgpu_info *avalon4 = thr->cgpu; 2080 struct avalon4_info *info = avalon4->device_data; 2081 struct timeval current; 2082 double device_tdiff, hwp; 2083 uint32_t a = 0, b = 0; 2084 int64_t h; 2085 int i, j, k, count = 0; 2086 uint32_t tmp; 2087 int max_temp; 2088 2089 if ((info->connecter == AVA4_CONNECTER_AUC) && 2090 (unlikely(avalon4->usbinfo.nodev))) { 2091 applog(LOG_ERR, "%s-%d: Device disappeared, shutting down thread", 2092 avalon4->drv->name, avalon4->device_id); 2093 return -1; 2094 } 2095 2096 /* Step 1: Stop polling the device if there is no stratum in 3 minutes, network is down */ 2097 cgtime(¤t); 2098 avalon4_freezsafemode = 0; 2099 if (tdiff(¤t, &(info->last_stratum)) > 180.0) { 2100 if(!opt_avalon4_freezesafe) 2101 return 0; 2102 2103 if(opt_avalon4_freezesafe) 2104 avalon4_freezsafemode = 1; 2105 } 2106 2107 /* Step 2: Polling */ 2108 cg_rlock(&info->update_lock); 2109 polling(avalon4); 2110 cg_runlock(&info->update_lock); 2111 2112 /* Step 3: Adjust voltage */ 2113 cgtime(¤t); 2114 device_tdiff = tdiff(¤t, &(info->last_5s)); 2115 if (device_tdiff >= 5.0 || device_tdiff < 0) { 2116 copy_time(&info->last_5s, ¤t); 2117 if (++info->i_5s >= AVA4_DEFAULT_ADJ_TIMES) 2118 info->i_5s = 0; 2119 2120 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2121 if (!info->enable[i]) 2122 continue; 2123 2124 info->lw5[i][info->i_5s] = 0; 2125 info->hw5[i][info->i_5s] = 0; 2126 2127 for(j = 0; j < info->miner_count[i]; j++) { 2128 info->lw5_i[i][j][info->i_5s] = 0; 2129 info->hw5_i[i][j][info->i_5s] = 0; 2130 } 2131 } 2132 } 2133 2134 cgtime(¤t); 2135 device_tdiff = tdiff(¤t, &(info->last_30s)); 2136 if (opt_avalon4_autov && (device_tdiff > 30.0 || device_tdiff < 0)) { 2137 copy_time(&info->last_30s, ¤t); 2138 2139 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2140 uint8_t individual = 0; 2141 2142 if (!info->enable[i]) 2143 continue; 2144 2145 if (!info->autov[i]) 2146 continue; 2147 2148 if (info->mod_type[i] == AVA4_TYPE_MM60) 2149 continue; 2150 2151 if (info->mod_type[i] == AVA4_TYPE_MM50) 2152 individual = 1; 2153 2154 if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i)) 2155 individual = 1; 2156 2157 if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) { 2158 if (!mm_cmp_d17f4a(info, i)) 2159 individual = 1; 2160 } 2161 2162 if (info->cutoff[i]) { 2163 for (j = 0; j < info->miner_count[i]; j++) 2164 info->adjflag[i][j] = 0; 2165 continue; 2166 } 2167 2168 if (!individual) { 2169 a = 0; 2170 b = 0; 2171 for (j = 0; j < AVA4_DEFAULT_ADJ_TIMES; j++) { 2172 a += info->lw5[i][j]; 2173 b += info->hw5[i][j]; 2174 } 2175 2176 hwp = a ? (double)b / (double)a : 0; 2177 if (hwp > AVA4_DH_INC && (info->set_voltage[i] < info->set_voltage[0] + 125)) { 2178 info->set_voltage[i] += 125; 2179 for (j = 0; j < info->miner_count[i]; j++) { 2180 info->set_voltage_i[i][j] += 125; 2181 } 2182 info->adjflag[i][0] = 1; 2183 applog(LOG_NOTICE, "%s-%d: Automatic increase module[%d] voltage to %d", 2184 avalon4->drv->name, avalon4->device_id, i, info->set_voltage[i]); 2185 } 2186 if (!info->adjflag[i][0] && hwp < AVA4_DH_DEC && (info->set_voltage[i] > info->set_voltage[0] - (4 * 125))) { 2187 info->set_voltage[i] -= 125; 2188 for (j = 0; j < info->miner_count[i]; j++) { 2189 info->set_voltage_i[i][j] -= 125; 2190 } 2191 2192 applog(LOG_NOTICE, "%s-%d: Automatic decrease module[%d] voltage to %d", 2193 avalon4->drv->name, avalon4->device_id, i, info->set_voltage[i]); 2194 } 2195 } else { 2196 for (j = 0; j < info->miner_count[i]; j++) { 2197 a = 0; 2198 b = 0; 2199 2200 for (k = 0; k < AVA4_DEFAULT_ADJ_TIMES; k++) { 2201 a += info->lw5_i[i][j][k]; 2202 b += info->hw5_i[i][j][k]; 2203 } 2204 2205 hwp = a ? (double)b / (double)a : 0; 2206 if (hwp > AVA4_DH_INC && (info->set_voltage_i[i][j] < info->set_voltage[0] + (2 * 125))) { 2207 //FIX ME: How to deal with set_voltage ? 2208 info->set_voltage_i[i][j] += 125; 2209 info->adjflag[i][j] = 1; 2210 applog(LOG_NOTICE, "%s-%d: Automatic increase module[%d-%d] voltage to %d", 2211 avalon4->drv->name, avalon4->device_id, i, j, info->set_voltage_i[i][j]); 2212 2213 } 2214 if (!info->adjflag[i][j] && hwp < AVA4_DH_DEC && (info->set_voltage_i[i][j] > info->set_voltage[0] - (12 * 125))) { 2215 //FIX ME: How to deal with set_voltage ? 2216 info->set_voltage_i[i][j] -= 125; 2217 applog(LOG_NOTICE, "%s-%d: Automatic decrease module[%d-%d] voltage to %d", 2218 avalon4->drv->name, avalon4->device_id, i, j, info->set_voltage_i[i][j]); 2219 } 2220 } 2221 } 2222 2223 /* Save config when run 10m */ 2224 cgtime(¤t); 2225 device_tdiff = tdiff(¤t, &(info->elapsed[i])); 2226 if (device_tdiff >= 600.0) { 2227 if (!info->saved[i]) { 2228 applog(LOG_NOTICE, "%s-%d-%d: Avalon4 saved voltage !", 2229 avalon4->drv->name, avalon4->device_id, i); 2230 avalon4_adjust_vf(avalon4, i, 1); 2231 info->saved[i] = 1; 2232 } else 2233 avalon4_adjust_vf(avalon4, i, 0); 2234 2235 } else 2236 avalon4_adjust_vf(avalon4, i, 0); 2237 2238 if (((int)device_tdiff % 3600) >= 0 || ((int)device_tdiff % 3600) < 3) { 2239 for (j = 0; j < info->miner_count[i]; j++) 2240 info->adjflag[i][j] = 0; 2241 } 2242 } 2243 } 2244 2245 /* Step 4: Adjust frequency */ 2246 cgtime(¤t); 2247 device_tdiff = tdiff(¤t, &(info->last_tcheck)); 2248 if (device_tdiff > 3.0 || device_tdiff < 0) { 2249 copy_time(&info->last_tcheck, ¤t); 2250 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2251 if (!info->enable[i]) 2252 continue; 2253 2254 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2255 max_temp = get_temp_max(info, i); 2256 if (info->freq_mode[i] != AVA4_FREQ_TEMPADJ_MODE) { 2257 if (max_temp >= opt_avalon4_freqadj_temp) { 2258 info->last_maxtemp[i] = max_temp; 2259 cg_wlock(&info->update_lock); 2260 avalon4_freq_dec(avalon4, i, info->set_smart_frequency[i], opt_avalon4_delta_freq + 50); 2261 avalon4_set_freq(avalon4, i, 0, 0, info->set_smart_frequency[i]); 2262 applog(LOG_DEBUG, "%s-%d-%d: set freq after temp check (%d-%d-%d)", 2263 avalon4->drv->name, avalon4->device_id, i, 2264 info->set_smart_frequency[i][0], 2265 info->set_smart_frequency[i][1], 2266 info->set_smart_frequency[i][2]); 2267 info->freq_mode[i] = AVA4_FREQ_TEMPADJ_MODE; 2268 /* Update time for frequency adjustment */ 2269 copy_time(&info->last_fadj, ¤t); 2270 cg_wunlock(&info->update_lock); 2271 } 2272 } 2273 } 2274 } 2275 } 2276 2277 device_tdiff = tdiff(¤t, &(info->last_fadj)); 2278 if (device_tdiff > opt_avalon4_freqadj_time || device_tdiff < 0) { 2279 copy_time(&info->last_fadj, ¤t); 2280 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2281 if (!info->enable[i]) 2282 continue; 2283 2284 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2285 switch (info->freq_mode[i]) { 2286 case AVA4_FREQ_TEMPADJ_MODE: 2287 if (info->cutoff[i]) 2288 break; 2289 2290 max_temp = get_temp_max(info, i); 2291 if (max_temp <= info->temp_target[i]) { 2292 applog(LOG_DEBUG, "AVA4_FREQ_TEMPADJ_MODE -> AVA4_FREQ_INIT_MODE"); 2293 break; 2294 } 2295 /* if max_temp goes down ,then we don't need adjust frequency */ 2296 if (info->last_maxtemp[i] > max_temp) { 2297 applog(LOG_DEBUG, "AVA4_FREQ_TEMPADJ_MODE temp goes down"); 2298 info->last_maxtemp[i] = get_temp_max(info, i); 2299 break; 2300 } 2301 2302 info->last_maxtemp[i] = get_temp_max(info, i); 2303 cg_wlock(&info->update_lock); 2304 avalon4_freq_dec(avalon4, i, info->set_smart_frequency[i], opt_avalon4_delta_freq); 2305 avalon4_set_freq(avalon4, i, 0, 0, info->set_smart_frequency[i]); 2306 applog(LOG_DEBUG, "%s-%d-%d: update freq (%d-%d-%d) AVA4_FREQ_PLLADJ_MODE", 2307 avalon4->drv->name, avalon4->device_id, i, 2308 info->set_smart_frequency[i][0], 2309 info->set_smart_frequency[i][1], 2310 info->set_smart_frequency[i][2]); 2311 cg_wunlock(&info->update_lock); 2312 break; 2313 case AVA4_FREQ_PLLADJ_MODE: 2314 /* AVA4_DEFAULT_SMARTSPEED_MODE1: auto speed by A3218 chips */ 2315 cgtime(¤t); 2316 if (opt_avalon4_smart_speed == AVA4_DEFAULT_SMARTSPEED_MODE2) { 2317 device_tdiff = tdiff(¤t, &(info->last_fdec[i])); 2318 if ((device_tdiff >= AVA4_DEFAULT_FDEC_TIME) || 2319 (device_tdiff < 0)) { 2320 copy_time(&info->last_fdec[i], ¤t); 2321 if ((opt_avalon4_least_pll_check && (info->pll_sel[i][0] >= opt_avalon4_least_pll_check)) || 2322 (opt_avalon4_most_pll_check && (info->pll_sel[i][AVA4_DEFAULT_PLL_MAX - 1] <= opt_avalon4_most_pll_check))) 2323 avalon4_freq_dec(avalon4, i, info->set_smart_frequency[i], 25); 2324 } 2325 2326 device_tdiff = tdiff(¤t, &(info->last_finc[i])); 2327 if ((device_tdiff >= AVA4_DEFAULT_FINC_TIME) || 2328 (device_tdiff < 0)) { 2329 copy_time(&info->last_finc[i], ¤t); 2330 if ((opt_avalon4_least_pll_check && (info->pll_sel[i][0] < opt_avalon4_least_pll_check)) || 2331 (opt_avalon4_most_pll_check && (info->pll_sel[i][AVA4_DEFAULT_PLL_MAX - 1] > opt_avalon4_most_pll_check))) 2332 avalon4_freq_inc(avalon4, i, info->set_smart_frequency[i], 25); 2333 } 2334 } 2335 2336 if (opt_avalon4_smart_speed == AVA4_DEFAULT_SMARTSPEED_MODE3) { 2337 device_tdiff = tdiff(¤t, &(info->last_favg[i])); 2338 if ((device_tdiff >= AVA4_DEFAULT_FAVG_TIME) || 2339 (device_tdiff < 0)) { 2340 copy_time(&info->last_favg[i], ¤t); 2341 tmp = (info->get_frequency[i] / 96); 2342 tmp = (uint32_t)ceil(tmp / 25.0) * 25 + 25; 2343 if (tmp < AVA4_DEFAULT_FREQUENCY_MIN) 2344 tmp = AVA4_DEFAULT_FREQUENCY_MIN; 2345 if (tmp > AVA4_MM60_FREQUENCY_MAX) 2346 tmp = AVA4_MM60_FREQUENCY_MAX; 2347 info->set_smart_frequency[i][0] = info->set_smart_frequency[i][1] = info->set_smart_frequency[i][2] = tmp; 2348 } 2349 } 2350 cg_wlock(&info->update_lock); 2351 avalon4_set_freq(avalon4, i, 0, 0, info->set_smart_frequency[i]); 2352 applog(LOG_DEBUG, "%s-%d-%d: update freq (%d-%d-%d) AVA4_FREQ_PLLADJ_MODE", 2353 avalon4->drv->name, avalon4->device_id, i, 2354 info->set_smart_frequency[i][0], 2355 info->set_smart_frequency[i][1], 2356 info->set_smart_frequency[i][2]); 2357 cg_wunlock(&info->update_lock); 2358 break; 2359 default: 2360 break; 2361 } 2362 } 2363 } 2364 } 2365 2366 /* Step 5: Calculate mm count and hash */ 2367 h = 0; 2368 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2369 if (info->enable[i]) { 2370 count++; 2371 if (info->local_work[i] > info->hw_work[i]) { 2372 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2373 h += avalon4->diff1 - info->newnonce; 2374 info->newnonce = avalon4->diff1; 2375 } else { 2376 h += (info->local_work[i] - info->hw_work[i]); 2377 info->local_work[i] = 0; 2378 info->hw_work[i] = 0; 2379 } 2380 } 2381 } 2382 } 2383 info->mm_count = count; 2384 2385 if (h && !info->firsthash.tv_sec) { 2386 cgtime(&info->firsthash); 2387 copy_time(&(avalon4->dev_start_tv), &(info->firsthash)); 2388 } 2389 2390 return h * 0xffffffffull; 2391 } 2392 2393 #define STATBUFLEN (6 * 1024) 2394 static struct api_data *avalon4_api_stats(struct cgpu_info *cgpu) 2395 { 2396 struct api_data *root = NULL; 2397 struct avalon4_info *info = cgpu->device_data; 2398 int i, j, k; 2399 uint32_t a, b, lw5_i[AVA4_DEFAULT_MINER_MAX], hw5_i[AVA4_DEFAULT_MINER_MAX]; 2400 double hwp, diff; 2401 char buf[256]; 2402 char statbuf[AVA4_DEFAULT_MODULARS][STATBUFLEN]; 2403 struct timeval current; 2404 bool has_a6 = false; 2405 2406 memset(statbuf, 0, AVA4_DEFAULT_MODULARS * STATBUFLEN); 2407 2408 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2409 if (info->mod_type[i] == AVA4_TYPE_NULL) 2410 continue; 2411 2412 if (info->mod_type[i] == AVA4_TYPE_MM60) 2413 has_a6 = true; 2414 2415 sprintf(buf, "Ver[%s]", info->mm_version[i]); 2416 strcat(statbuf[i], buf); 2417 } 2418 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2419 if (info->mod_type[i] == AVA4_TYPE_NULL) 2420 continue; 2421 2422 sprintf(buf, " DNA[%02x%02x%02x%02x%02x%02x%02x%02x]", 2423 info->mm_dna[i][0], 2424 info->mm_dna[i][1], 2425 info->mm_dna[i][2], 2426 info->mm_dna[i][3], 2427 info->mm_dna[i][4], 2428 info->mm_dna[i][5], 2429 info->mm_dna[i][6], 2430 info->mm_dna[i][7]); 2431 strcat(statbuf[i], buf); 2432 } 2433 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2434 struct timeval now; 2435 if (info->mod_type[i] == AVA4_TYPE_NULL) 2436 continue; 2437 2438 cgtime(&now); 2439 sprintf(buf, " Elapsed[%.0f]", tdiff(&now, &(info->elapsed[i]))); 2440 strcat(statbuf[i], buf); 2441 } 2442 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2443 uint8_t show = 0; 2444 2445 if (info->mod_type[i] == AVA4_TYPE_NULL) 2446 continue; 2447 2448 if (info->mod_type[i] == AVA4_TYPE_MM60) 2449 show = 1; 2450 2451 if (info->mod_type[i] == AVA4_TYPE_MM50) 2452 show = 1; 2453 2454 if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i)) 2455 show = 1; 2456 2457 if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) { 2458 if (!mm_cmp_d17f4a(info, i)) 2459 show = 1; 2460 } 2461 2462 strcat(statbuf[i], " MW["); 2463 for (j = 0; j < info->miner_count[i]; j++) { 2464 if (show) 2465 sprintf(buf, "%"PRIu64" ", info->local_works_i[i][j]); 2466 else 2467 sprintf(buf, "%d ", info->matching_work[i][j]); 2468 2469 strcat(statbuf[i], buf); 2470 } 2471 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2472 } 2473 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2474 if (info->mod_type[i] == AVA4_TYPE_NULL) 2475 continue; 2476 2477 sprintf(buf, " LW[%"PRIu64"]", info->local_works[i]); 2478 strcat(statbuf[i], buf); 2479 } 2480 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2481 uint8_t show = 0; 2482 2483 if (info->mod_type[i] == AVA4_TYPE_NULL) 2484 continue; 2485 2486 if (info->mod_type[i] == AVA4_TYPE_MM60) 2487 show = 1; 2488 2489 if (info->mod_type[i] == AVA4_TYPE_MM50) 2490 show = 1; 2491 2492 if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i)) 2493 show = 1; 2494 2495 if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) { 2496 if (!mm_cmp_d17f4a(info, i)) 2497 show = 1; 2498 } 2499 2500 if (show) { 2501 strcat(statbuf[i], " MH["); 2502 for (j = 0; j < info->miner_count[i]; j++) { 2503 sprintf(buf, "%"PRIu64" ", info->hw_works_i[i][j]); 2504 strcat(statbuf[i], buf); 2505 } 2506 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2507 } 2508 } 2509 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2510 if (info->mod_type[i] == AVA4_TYPE_NULL) 2511 continue; 2512 2513 sprintf(buf, " HW[%"PRIu64"]", info->hw_works[i]); 2514 strcat(statbuf[i], buf); 2515 } 2516 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2517 if (info->mod_type[i] == AVA4_TYPE_NULL) 2518 continue; 2519 2520 a = info->hw_works[i]; 2521 b = info->local_works[i]; 2522 hwp = b ? ((double)a / (double)b) * 100: 0; 2523 2524 sprintf(buf, " DH[%.3f%%]", hwp); 2525 strcat(statbuf[i], buf); 2526 } 2527 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2528 uint8_t show = 0; 2529 2530 if (info->mod_type[i] == AVA4_TYPE_NULL) 2531 continue; 2532 2533 a = 0; 2534 b = 0; 2535 memset(lw5_i, 0, info->miner_count[i] * sizeof(uint32_t)); 2536 memset(hw5_i, 0, info->miner_count[i] * sizeof(uint32_t)); 2537 2538 for (j = 0; j < AVA4_DEFAULT_ADJ_TIMES; j++) { 2539 a += info->lw5[i][j]; 2540 b += info->hw5[i][j]; 2541 2542 for (k = 0; k < info->miner_count[i]; k++) { 2543 lw5_i[k] += info->lw5_i[i][k][j]; 2544 hw5_i[k] += info->hw5_i[i][k][j]; 2545 } 2546 } 2547 2548 cgtime(¤t); 2549 diff = tdiff(¤t, &(info->last_5s)) + 25.0; 2550 2551 hwp = a ? (double)b / (double)a * 100 : 0; 2552 2553 if (info->mod_type[i] == AVA4_TYPE_MM50) 2554 show = 1; 2555 2556 if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i)) 2557 show = 1; 2558 2559 if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) { 2560 if (!mm_cmp_d17f4a(info, i)) 2561 show = 1; 2562 } 2563 2564 sprintf(buf, " GHS5m[%.2f] DH5m[%.3f%%]", ((double)a - (double)b) * 4.295 / diff, hwp); 2565 strcat(statbuf[i], buf); 2566 2567 if (opt_debug && show) { 2568 strcat(statbuf[i], " MDH5m["); 2569 for (k = 0; k < info->miner_count[i]; k++) { 2570 hwp = lw5_i[k] ? (double)hw5_i[k] / (double)lw5_i[k] * 100 : 0; 2571 sprintf(buf, "%.3f%% ", hwp); 2572 strcat(statbuf[i], buf); 2573 } 2574 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2575 } 2576 } 2577 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2578 if (info->mod_type[i] == AVA4_TYPE_NULL) 2579 continue; 2580 2581 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2582 sprintf(buf, " Temp[%d] Temp0[%d] Temp1[%d]", 2583 info->temp[i], 2584 (int)convert_temp(info->adc[i][0]), 2585 (int)convert_temp(info->adc[i][1])); 2586 } else 2587 sprintf(buf, " Temp[%d]", info->temp[i]); 2588 2589 strcat(statbuf[i], buf); 2590 } 2591 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2592 if (info->mod_type[i] == AVA4_TYPE_NULL) 2593 continue; 2594 2595 sprintf(buf, " Fan[%d]", info->fan[i]); 2596 strcat(statbuf[i], buf); 2597 } 2598 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2599 if (info->mod_type[i] == AVA4_TYPE_NULL) 2600 continue; 2601 if (info->mod_type[i] == AVA4_TYPE_MM60) 2602 sprintf(buf, " Vol[%.1f]", convert_voltage(info->adc[i][4], 1 / 11.0)); 2603 else 2604 sprintf(buf, " Vol[%.4f]", (float)info->get_voltage[i] / 10000); 2605 strcat(statbuf[i], buf); 2606 } 2607 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2608 uint8_t show = 0; 2609 int32_t vref = 0; 2610 2611 if (info->mod_type[i] == AVA4_TYPE_NULL) 2612 continue; 2613 2614 if (info->mod_type[i] == AVA4_TYPE_MM50) 2615 show = 1; 2616 2617 if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i)) 2618 show = 1; 2619 2620 if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) { 2621 if (!mm_cmp_d17f4a(info, i)) 2622 show = 1; 2623 } 2624 2625 if (opt_debug && show) { 2626 strcat(statbuf[i], " MVol["); 2627 for (j = 0; j < info->miner_count[i]; j++) { 2628 sprintf(buf, "%.4f ", (float)info->set_voltage_i[i][j] / 10000); 2629 vref += ((info->set_voltage_i[i][j] - opt_avalon4_voltage_min) / 125); 2630 strcat(statbuf[i], buf); 2631 } 2632 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2633 2634 strcat(statbuf[i], " VREF["); 2635 sprintf(buf, "%d ", vref); 2636 strcat(statbuf[i], buf); 2637 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2638 } 2639 } 2640 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2641 if (info->mod_type[i] == AVA4_TYPE_NULL) 2642 continue; 2643 2644 if (info->mod_type[i] == AVA4_TYPE_MM60) 2645 sprintf(buf, " GHSmm[%.2f] Freq[%.2f]", (float)info->get_frequency[i] / 1000 * info->total_asics[i], (float)info->get_frequency[i] / 1000); 2646 else 2647 sprintf(buf, " Freq[%.2f]", (float)info->get_frequency[i] / 1000); 2648 strcat(statbuf[i], buf); 2649 } 2650 if (opt_debug) { 2651 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2652 if (info->mod_type[i] == AVA4_TYPE_NULL) 2653 continue; 2654 2655 if (info->mod_type[i] == AVA4_TYPE_MM50) { 2656 for (j = 0; j < info->miner_count[i]; j++) { 2657 sprintf(buf, " MFreq%d[", j); 2658 strcat(statbuf[i], buf); 2659 for (k = 0; k < info->asic_count[i]; k++) { 2660 sprintf(buf, "%d %d %d ", 2661 info->set_frequency_i[i][j][k][0], 2662 info->set_frequency_i[i][j][k][1], 2663 info->set_frequency_i[i][j][k][2]); 2664 strcat(statbuf[i], buf); 2665 } 2666 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2667 } 2668 } 2669 } 2670 } 2671 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2672 if (info->mod_type[i] == AVA4_TYPE_NULL) 2673 continue; 2674 2675 sprintf(buf, " PG[%d]", info->power_good[i]); 2676 strcat(statbuf[i], buf); 2677 } 2678 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2679 if (info->mod_type[i] == AVA4_TYPE_NULL) 2680 continue; 2681 2682 sprintf(buf, " Led[%d]", info->led_red[i]); 2683 strcat(statbuf[i], buf); 2684 } 2685 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2686 if (info->mod_type[i] == AVA4_TYPE_NULL) 2687 continue; 2688 2689 if (info->mod_type[i] == AVA4_TYPE_MM50 || info->mod_type[i] == AVA4_TYPE_MM60) { 2690 for (j = 0; j < info->miner_count[i]; j++) { 2691 sprintf(buf, " MW%d[", j); 2692 strcat(statbuf[i], buf); 2693 for (k = 0; k < info->asic_count[i]; k++) { 2694 sprintf(buf, "%d ", info->chipmatching_work[i][j][k]); 2695 strcat(statbuf[i], buf); 2696 } 2697 2698 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2699 } 2700 } 2701 } 2702 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2703 if (info->mod_type[i] == AVA4_TYPE_NULL) 2704 continue; 2705 2706 if (info->mod_type[i] == AVA4_TYPE_MM50) { 2707 for (j = 0; j < info->miner_count[i]; j++) { 2708 sprintf(buf, " MA%d[", j); 2709 strcat(statbuf[i], buf); 2710 for (k = 0; k < info->asic_count[i]; k++) { 2711 sprintf(buf, "%d ", info->ma_sum[i][j][k]); 2712 strcat(statbuf[i], buf); 2713 } 2714 2715 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2716 } 2717 } 2718 } 2719 if (opt_debug) { 2720 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2721 if (info->mod_type[i] == AVA4_TYPE_NULL) 2722 continue; 2723 2724 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2725 sprintf(buf, " PLL["); 2726 strcat(statbuf[i], buf); 2727 for (j = 0; j < AVA4_DEFAULT_PLL_MAX; j++) { 2728 sprintf(buf, "%d ", info->pll_sel[i][j]); 2729 strcat(statbuf[i], buf); 2730 } 2731 statbuf[i][strlen(statbuf[i]) - 1] = ']'; 2732 } 2733 } 2734 } 2735 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2736 if (info->mod_type[i] == AVA4_TYPE_NULL) 2737 continue; 2738 2739 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2740 sprintf(buf, " TA[%d]", info->total_asics[i]); 2741 strcat(statbuf[i], buf); 2742 } 2743 } 2744 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2745 if (info->mod_type[i] == AVA4_TYPE_NULL) 2746 continue; 2747 2748 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2749 sprintf(buf, " EC[%d]", info->error_code[i]); 2750 strcat(statbuf[i], buf); 2751 } 2752 } 2753 if (opt_debug) { 2754 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2755 if (info->mod_type[i] == AVA4_TYPE_NULL) 2756 continue; 2757 2758 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2759 sprintf(buf, " SF[%d %d %d]", 2760 info->set_smart_frequency[i][0], 2761 info->set_smart_frequency[i][1], 2762 info->set_smart_frequency[i][2]); 2763 strcat(statbuf[i], buf); 2764 } 2765 } 2766 2767 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2768 if (info->mod_type[i] == AVA4_TYPE_NULL) 2769 continue; 2770 2771 if (info->mod_type[i] == AVA4_TYPE_MM60) { 2772 sprintf(buf, " FM[%d]", info->freq_mode[i]); 2773 strcat(statbuf[i], buf); 2774 } 2775 } 2776 } 2777 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2778 if (info->mod_type[i] == AVA4_TYPE_NULL) 2779 continue; 2780 2781 sprintf(buf, "MM ID%d", i); 2782 root = api_add_string(root, buf, statbuf[i], true); 2783 } 2784 2785 root = api_add_int(root, "MM Count", &(info->mm_count), true); 2786 if (!has_a6) 2787 root = api_add_bool(root, "Automatic Voltage", &opt_avalon4_autov, true); 2788 root = api_add_int(root, "Smart Speed", &opt_avalon4_smart_speed, true); 2789 root = api_add_bool(root, "Nonce check", &opt_avalon4_noncecheck, true); 2790 if (info->connecter == AVA4_CONNECTER_IIC) 2791 root = api_add_string(root, "Connecter", "IIC", true); 2792 2793 if (info->connecter == AVA4_CONNECTER_AUC) { 2794 root = api_add_string(root, "Connecter", "AUC", true); 2795 root = api_add_string(root, "AUC VER", info->auc_version, false); 2796 root = api_add_int(root, "AUC I2C Speed", &(info->auc_speed), true); 2797 root = api_add_int(root, "AUC I2C XDelay", &(info->auc_xdelay), true); 2798 root = api_add_int(root, "AUC ADC", &(info->auc_temp), true); 2799 } 2800 2801 return root; 2802 } 2803 2804 /* format: freq[-addr[-miner[-chip]]] add4[0, 63], miner[1, miner_count], chip[1, asic_count] */ 2805 char *set_avalon4_device_freq(struct cgpu_info *avalon4, char *arg) 2806 { 2807 struct avalon4_info *info = avalon4->device_data; 2808 char *colon1, *colon2, *param = arg; 2809 unsigned int val[3], addr = 0, i; 2810 uint32_t miner_id = 0, chip_id = 0; 2811 2812 if (!(*arg)) 2813 return NULL; 2814 2815 colon1 = strchr(arg, ':'); 2816 if (colon1) { 2817 *(colon1++) = '\0'; 2818 param = colon1; 2819 } 2820 2821 if (*arg) { 2822 val[0] = atoi(arg); 2823 if (val[0] < AVA4_DEFAULT_FREQUENCY_MIN || val[0] > AVA4_DEFAULT_FREQUENCY_MAX) 2824 return "Invalid value1 passed to set_avalon4_device_freq"; 2825 } 2826 2827 if (colon1 && *colon1) { 2828 colon2 = strchr(colon1, ':'); 2829 if (colon2) { 2830 *(colon2++) = '\0'; 2831 param = colon2; 2832 } 2833 2834 if (*colon1) { 2835 val[1] = atoi(colon1); 2836 if (val[1] < AVA4_DEFAULT_FREQUENCY_MIN || val[1] > AVA4_DEFAULT_FREQUENCY_MAX) 2837 return "Invalid value2 passed to set_avalon4_device_freq"; 2838 } 2839 2840 if (colon2 && *colon2) { 2841 val[2] = atoi(colon2); 2842 if (val[2] < AVA4_DEFAULT_FREQUENCY_MIN || val[2] > AVA4_DEFAULT_FREQUENCY_MAX) 2843 return "Invalid value3 passed to set_avalon4_device_freq"; 2844 } 2845 } 2846 2847 if (!val[0]) 2848 val[2] = val[1] = val[0] = AVA4_DEFAULT_FREQUENCY; 2849 2850 if (!val[1]) 2851 val[2] = val[1] = val[0]; 2852 2853 if (!val[2]) 2854 val[2] = val[1]; 2855 2856 colon1 = strchr(param, '-'); 2857 if (colon1) { 2858 sscanf(colon1, "-%d-%d-%d", &addr, &miner_id, &chip_id); 2859 if (miner_id >= AVA4_DEFAULT_MODULARS) { 2860 applog(LOG_ERR, "invalid dev index: %d, valid range 0-%d", addr, (AVA4_DEFAULT_MODULARS - 1)); 2861 return "Invalid dev index to set_avalon4_device_freq"; 2862 } 2863 if (!info->enable[addr]) { 2864 applog(LOG_ERR, "Disabled dev:%d", addr); 2865 return "Disabled dev to set_avalon4_device_freq"; 2866 } 2867 if (miner_id > info->miner_count[addr]) { 2868 applog(LOG_ERR, "invalid miner index: %d, valid range 0-%d", chip_id, info->miner_count[addr]); 2869 return "Invalid miner index to set_avalon4_device_freq"; 2870 } 2871 if (chip_id > info->asic_count[addr]) { 2872 applog(LOG_ERR, "invalid asic index: %d, valid range 0-%d", chip_id, info->asic_count[addr]); 2873 return "Invalid asic index to set_avalon4_device_freq"; 2874 } 2875 } 2876 2877 if (!miner_id || !chip_id) { 2878 memcpy(opt_avalon4_freq, val, sizeof(int) * 3); 2879 if (!addr) { 2880 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 2881 if (!info->enable[i]) 2882 continue; 2883 2884 avalon4_set_freq(avalon4, i, 0, 0, val); 2885 } 2886 } else 2887 avalon4_set_freq(avalon4, addr, 0, 0, val); 2888 } else 2889 avalon4_set_freq(avalon4, addr, miner_id, chip_id, val); 2890 2891 return NULL; 2892 } 2893 2894 static char *avalon4_set_device(struct cgpu_info *avalon4, char *option, char *setting, char *replybuf) 2895 { 2896 int val, i, j; 2897 struct avalon4_info *info = avalon4->device_data; 2898 2899 if (strcasecmp(option, "help") == 0) { 2900 sprintf(replybuf, "led|fan|voltage|frequency|pdelay|freezesafe"); 2901 return replybuf; 2902 } 2903 2904 if (strcasecmp(option, "freezesafe") == 0) { 2905 if (!setting || !*setting) { 2906 sprintf(replybuf, "missing freezesafe mode setting"); 2907 return replybuf; 2908 } 2909 2910 val = atoi(setting); 2911 2912 opt_avalon4_freezesafe = val ? 1 : 0; 2913 2914 applog(LOG_NOTICE, "%s-%d: update freezesafe mode: %d", 2915 avalon4->drv->name, avalon4->device_id, opt_avalon4_freezesafe); 2916 2917 return NULL; 2918 } 2919 2920 if (strcasecmp(option, "pdelay") == 0) { 2921 if (!setting || !*setting) { 2922 sprintf(replybuf, "missing polling delay setting"); 2923 return replybuf; 2924 } 2925 2926 val = atoi(setting); 2927 if (val < 1 || val > 65535) { 2928 sprintf(replybuf, "invalid polling delay: %d, valid range 1-65535", val); 2929 return replybuf; 2930 } 2931 2932 opt_avalon4_polling_delay = val; 2933 2934 applog(LOG_NOTICE, "%s-%d: Update polling delay to: %d", 2935 avalon4->drv->name, avalon4->device_id, val); 2936 2937 return NULL; 2938 } 2939 2940 if (strcasecmp(option, "fan") == 0) { 2941 if (!setting || !*setting) { 2942 sprintf(replybuf, "missing fan value"); 2943 return replybuf; 2944 } 2945 2946 if (set_avalon4_fan(setting)) { 2947 sprintf(replybuf, "invalid fan value, valid range 0-100"); 2948 return replybuf; 2949 } 2950 2951 applog(LOG_NOTICE, "%s-%d: Update fan to %d-%d", 2952 avalon4->drv->name, avalon4->device_id, 2953 opt_avalon4_fan_min, opt_avalon4_fan_max); 2954 2955 return NULL; 2956 } 2957 2958 if (strcasecmp(option, "frequency") == 0) { 2959 if (!setting || !*setting) { 2960 sprintf(replybuf, "missing frequency value"); 2961 return replybuf; 2962 } 2963 2964 if (set_avalon4_device_freq(avalon4, setting)) { 2965 sprintf(replybuf, "invalid frequency value, valid range %d-%d", 2966 AVA4_DEFAULT_FREQUENCY_MIN, AVA4_DEFAULT_FREQUENCY_MAX); 2967 return replybuf; 2968 } 2969 2970 applog(LOG_NOTICE, "%s-%d: Update frequency to %d", 2971 avalon4->drv->name, avalon4->device_id, 2972 (opt_avalon4_freq[0] * 4 + opt_avalon4_freq[1] * 4 + opt_avalon4_freq[2]) / 9); 2973 2974 return NULL; 2975 } 2976 2977 if (strcasecmp(option, "led") == 0) { 2978 int val_led = -1; 2979 2980 if (!setting || !*setting) { 2981 sprintf(replybuf, "missing module_id setting"); 2982 return replybuf; 2983 } 2984 2985 sscanf(setting, "%d-%d", &val, &val_led); 2986 if (val < 1 || val >= AVA4_DEFAULT_MODULARS) { 2987 sprintf(replybuf, "invalid module_id: %d, valid range 1-%d", val, AVA4_DEFAULT_MODULARS); 2988 return replybuf; 2989 } 2990 2991 if (!info->enable[val]) { 2992 sprintf(replybuf, "the current module was disabled %d", val); 2993 return replybuf; 2994 } 2995 2996 if (val_led == -1) 2997 info->led_red[val] = !info->led_red[val]; 2998 else { 2999 if (val_led < 0 || val_led > 1) { 3000 sprintf(replybuf, "invalid LED status: %d, valid value 0|1", val_led); 3001 return replybuf; 3002 } 3003 3004 if (val_led != info->led_red[val]) 3005 info->led_red[val] = val_led; 3006 } 3007 3008 applog(LOG_NOTICE, "%s-%d: Module:%d, LED: %s", 3009 avalon4->drv->name, avalon4->device_id, 3010 val, info->led_red[val] ? "on" : "off"); 3011 3012 return NULL; 3013 } 3014 3015 if (strcasecmp(option, "voltage") == 0) { 3016 int val_mod, val_volt, val_ch = -1, val_offset = -1; 3017 3018 if (!setting || !*setting) { 3019 sprintf(replybuf, "missing voltage value"); 3020 return replybuf; 3021 } 3022 3023 sscanf(setting, "%d-%d-%d-%d", &val_mod, &val_volt, &val_ch, &val_offset); 3024 if (val_mod < 0 || val_mod >= AVA4_DEFAULT_MODULARS || 3025 val_volt < AVA4_DEFAULT_VOLTAGE_MIN || val_volt > AVA4_DEFAULT_VOLTAGE_MAX) { 3026 sprintf(replybuf, "invalid module_id or voltage value, valid module_id range %d-%d, valid voltage range %d-%d", 3027 0, AVA4_DEFAULT_MODULARS, 3028 AVA4_DEFAULT_VOLTAGE_MIN, AVA4_DEFAULT_VOLTAGE_MAX); 3029 return replybuf; 3030 } 3031 3032 if ((val_ch != -1) && (val_ch < -1 || val_ch >= AVA4_DEFAULT_MINER_MAX)) { 3033 sprintf(replybuf, "invalid miner_id, valid miner_id range %d-%d", 3034 0, AVA4_DEFAULT_MINER_MAX - 1); 3035 return replybuf; 3036 } 3037 3038 if ((val_offset != -1) && ((val_volt + val_offset) < AVA4_DEFAULT_VOLTAGE_MIN || 3039 ((val_volt + val_offset) > AVA4_DEFAULT_VOLTAGE_MAX))) { 3040 sprintf(replybuf, "invalid val_offset, valid val_offset range %d-%d", 3041 AVA4_DEFAULT_VOLTAGE_MIN - val_volt, 3042 AVA4_DEFAULT_VOLTAGE_MAX - val_volt); 3043 return replybuf; 3044 } 3045 3046 if (!info->enable[val_mod]) { 3047 sprintf(replybuf, "the current module was disabled %d", val_mod); 3048 return replybuf; 3049 } 3050 3051 info->set_voltage[val_mod] = val_volt; 3052 if (val_ch == -1) { 3053 for (i = 0; i < info->miner_count[val_mod]; i++) { 3054 info->set_voltage_i[val_mod][i] = val_volt; 3055 info->set_voltage_offset[val_mod][i] = 0; 3056 } 3057 } else { 3058 info->set_voltage_i[val_mod][val_ch] = val_volt; 3059 if (val_offset == -1) 3060 info->set_voltage_offset[val_mod][val_ch] = 0; 3061 else 3062 info->set_voltage_offset[val_mod][val_ch] = val_offset; 3063 } 3064 3065 if (val_mod == AVA4_MODULE_BROADCAST) { 3066 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 3067 info->set_voltage[i] = val_volt; 3068 if (val_ch == -1) { 3069 for (j = 0; j < info->miner_count[i]; j++) { 3070 info->set_voltage_i[i][j] = val_volt; 3071 info->set_voltage_offset[i][j] = 0; 3072 } 3073 } else { 3074 info->set_voltage_i[i][val_ch] = val_volt; 3075 if (val_offset == -1) 3076 info->set_voltage_offset[i][val_ch] = 0; 3077 else 3078 info->set_voltage_offset[i][val_ch] = val_offset; 3079 } 3080 } 3081 } 3082 3083 applog(LOG_NOTICE, "%s-%d: Update module[%d] voltage to %d, val_ch:%d, val_offset:%d", 3084 avalon4->drv->name, avalon4->device_id, val_mod, val_volt, val_ch, val_offset); 3085 3086 return NULL; 3087 } 3088 3089 sprintf(replybuf, "Unknown option: %s", option); 3090 return replybuf; 3091 } 3092 3093 static void avalon4_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon4) 3094 { 3095 struct avalon4_info *info = avalon4->device_data; 3096 int temp = get_current_temp_max(info); 3097 int voltsmin = AVA4_DEFAULT_VOLTAGE_MAX, voltsmax = AVA4_DEFAULT_VOLTAGE_MIN; 3098 int fanmin = AVA4_DEFAULT_FAN_MAX, fanmax = AVA4_DEFAULT_FAN_MIN; 3099 int i, j, tempadcmin = AVA4_ADC_MAX, vcc12adcmin = AVA4_ADC_MAX; 3100 int has_a6 = 0; 3101 uint32_t frequency = 0; 3102 float ghs_sum = 0.0; 3103 3104 for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) { 3105 if (!info->enable[i]) 3106 continue; 3107 3108 if (info->mod_type[i] == AVA4_TYPE_MM60) 3109 has_a6 = 1; 3110 3111 if (fanmax <= info->fan_pct[i]) 3112 fanmax = info->fan_pct[i]; 3113 if (fanmin >= info->fan_pct[i]) 3114 fanmin = info->fan_pct[i]; 3115 3116 if (voltsmax <= info->get_voltage[i]) 3117 voltsmax = info->get_voltage[i]; 3118 if (voltsmin >= info->get_voltage[i]) 3119 voltsmin = info->get_voltage[i]; 3120 3121 for (j = 0; j < AVA4_DEFAULT_ADC_MAX - 2; j++) { 3122 if (info->adc[i][j] < tempadcmin) 3123 tempadcmin = info->adc[i][j]; 3124 } 3125 if (info->adc[i][4] < vcc12adcmin) 3126 vcc12adcmin = info->adc[i][4]; 3127 frequency += info->get_frequency[i]; 3128 ghs_sum += ((float)info->get_frequency[i] / 1000 * info->total_asics[i]); 3129 } 3130 3131 if (has_a6) { 3132 if (info->mm_count) 3133 frequency /= info->mm_count; 3134 tailsprintf(buf, bufsiz, "%4dMhz %.2fGHS %2dC-%2dC %3d%% %.1fV", frequency / 96, 3135 ghs_sum, temp, (int)convert_temp(tempadcmin), fanmin, 3136 (vcc12adcmin == AVA4_ADC_MAX) ? 0 : convert_voltage(vcc12adcmin, 1 / 11.0)); 3137 } else { 3138 frequency = (opt_avalon4_freq[0] * 4 + opt_avalon4_freq[1] * 4 + opt_avalon4_freq[2]) / 9; 3139 tailsprintf(buf, bufsiz, "%4dMhz %2dC %3d%% %.3fV", frequency, 3140 temp, fanmin, (float)voltsmax / 10000); 3141 } 3142 } 3143 3144 struct device_drv avalon4_drv = { 3145 .drv_id = DRIVER_avalon4, 3146 .dname = "avalon4", 3147 .name = "AV4", 3148 .set_device = avalon4_set_device, 3149 .get_api_stats = avalon4_api_stats, 3150 .get_statline_before = avalon4_statline_before, 3151 .drv_detect = avalon4_detect, 3152 .thread_prepare = avalon4_prepare, 3153 .hash_work = hash_driver_work, 3154 .flush_work = avalon4_update, 3155 .update_work = avalon4_update, 3156 .scanwork = avalon4_scanhash, 3157 .max_diff = AVA4_DRV_DIFFMAX, 3158 };