/ driver-btm-soc.h
driver-btm-soc.h
1 /* 2 * Copyright 2016-2017 Fazio Bai <yang.bai@bitmain.com> 3 * Copyright 2016-2017 Clement Duan <kai.duan@bitmain.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the Free 7 * Software Foundation; either version 3 of the License, or (at your option) 8 * any later version. See COPYING for more details. 9 */ 10 11 #ifndef __DRIVER_BTM_SOC_H__ 12 #define __DRIVER_BTM_SOC_H__ 13 14 #include "config.h" 15 //FPGA rgister Address Map 16 #define HARDWARE_VERSION (0x00000000/sizeof(int)) 17 #define FAN_SPEED (0x00000004/sizeof(int)) 18 #define HASH_ON_PLUG (0x00000008/sizeof(int)) 19 #define BUFFER_SPACE (0x0000000c/sizeof(int)) 20 #define RETURN_NONCE (0x00000010/sizeof(int)) 21 #define NONCE_NUMBER_IN_FIFO (0x00000018/sizeof(int)) 22 #define NONCE_FIFO_INTERRUPT (0x0000001c/sizeof(int)) 23 #define TEMPERATURE_0_3 (0x00000020/sizeof(int)) 24 #define TEMPERATURE_4_7 (0x00000024/sizeof(int)) 25 #define TEMPERATURE_8_11 (0x00000028/sizeof(int)) 26 #define TEMPERATURE_12_15 (0x0000002c/sizeof(int)) 27 #define IIC_COMMAND (0x00000030/sizeof(int)) 28 #define RESET_HASHBOARD_COMMAND (0x00000034/sizeof(int)) 29 #define BMC_CMD_COUNTER (0x00000038/sizeof(int)) 30 #define TW_WRITE_COMMAND (0x00000040/sizeof(int)) 31 #define QN_WRITE_DATA_COMMAND (0x00000080/sizeof(int)) 32 #define FAN_CONTROL (0x00000084/sizeof(int)) 33 #define TIME_OUT_CONTROL (0x00000088/sizeof(int)) 34 #define TICKET_MASK_FPGA (0x0000008c/sizeof(int)) 35 #define HASH_COUNTING_NUMBER_FPGA (0x00000090/sizeof(int)) 36 #define SNO (0x00000094/sizeof(int)) 37 #define BC_WRITE_COMMAND (0x000000c0/sizeof(int)) 38 #define BC_COMMAND_BUFFER (0x000000c4/sizeof(int)) 39 #define FPGA_CHIP_ID_ADDR (0x000000f0/sizeof(int)) 40 #define CRC_ERROR_CNT_ADDR (0x000000f8/sizeof(int)) 41 #define DHASH_ACC_CONTROL (0x00000100/sizeof(int)) 42 #define COINBASE_AND_NONCE2_LENGTH (0x00000104/sizeof(int)) 43 #define WORK_NONCE_2 (0x00000108/sizeof(int)) 44 #define NONCE2_AND_JOBID_STORE_ADDRESS (0x00000110/sizeof(int)) 45 #define MERKLE_BIN_NUMBER (0x00000114/sizeof(int)) 46 #define JOB_START_ADDRESS (0x00000118/sizeof(int)) 47 #define JOB_LENGTH (0x0000011c/sizeof(int)) 48 #define JOB_DATA_READY (0x00000120/sizeof(int)) 49 #define JOB_ID (0x00000124/sizeof(int)) 50 #define BLOCK_HEADER_VERSION (0x00000130/sizeof(int)) 51 #define TIME_STAMP (0x00000134/sizeof(int)) 52 #define TARGET_BITS (0x00000138/sizeof(int)) 53 #define PRE_HEADER_HASH (0x00000140/sizeof(int)) 54 55 //FPGA registers bit map 56 //QN_WRITE_DATA_COMMAND 57 #define RESET_HASH_BOARD (1 << 31) 58 #define RESET_ALL (1 << 23) 59 #define CHAIN_ID(id) (id << 16) 60 #define RESET_FPGA (1 << 15) 61 #define RESET_TIME(time) (time << 0) 62 #define TIME_OUT_VALID (1 << 31) 63 //RETURN_NONCE 64 #define WORK_ID_OR_CRC (1 << 31) 65 #define WORK_ID_OR_CRC_VALUE(value) ((value >> 16) & 0x7fff) 66 #define NONCE_INDICATOR (1 << 7) 67 #define CHAIN_NUMBER(value) (value & 0xf) 68 #define REGISTER_DATA_CRC(value) ((value >> 24) & 0x7f) 69 //BC_WRITE_COMMAND 70 #define BC_COMMAND_BUFFER_READY (1 << 31) 71 #define BC_COMMAND_EN_CHAIN_ID (1 << 23) 72 #define BC_COMMAND_EN_NULL_WORK (1 << 22) 73 //NONCE2_AND_JOBID_STORE_ADDRESS 74 #define JOB_ID_OFFSET (0x0/sizeof(int)) 75 #define HEADER_VERSION_OFFSET (0x4/sizeof(int)) 76 #define NONCE2_L_OFFSET (0x8/sizeof(int)) 77 #define NONCE2_H_OFFSET (0xc/sizeof(int)) 78 #define MIDSTATE_OFFSET 0x20 79 //DHASH_ACC_CONTROL 80 #define VIL_MODE (1 << 15) 81 #define VIL_MIDSTATE_NUMBER(value) ((value & 0x0f) << 8) 82 #define NEW_BLOCK (1 << 7) 83 #define RUN_BIT (1 << 6) 84 #define OPERATION_MODE (1 << 5) 85 //NONCE_FIFO_INTERRUPT 86 #define FLUSH_NONCE3_FIFO (1 << 16) 87 88 89 //ASIC macro define 90 //ASIC register address 91 #define SOC_VERSION 1 92 #define CHIP_ADDRESS 0x0 93 #define GOLDEN_NONCE_COUNTER 0x8 94 #define PLL_PARAMETER 0xc 95 #define START_NONCE_OFFSET 0x10 96 #define HASH_COUNTING_NUMBER 0x14 97 #define TICKET_MASK 0x18 98 #define MISC_CONTROL 0x1c 99 #define GENERAL_I2C_COMMAND 0X20 100 101 //ASIC command 102 #define SET_ADDRESS 0x1 103 #define SET_PLL_DIVIDER2 0x2 104 #define PATTERN_CONTROL 0x3 105 #define GET_STATUS 0x4 106 #define CHAIN_INACTIVE 0x5 107 #define SET_BAUD_OPS 0x6 108 #define SET_PLL_DIVIDER1 0x7 109 #define SET_CONFIG 0x8 110 #define COMMAND_FOR_ALL 0x80 111 //other ASIC macro define 112 #define MAX_BAUD_DIVIDER 26 113 #define DEFAULT_BAUD_DIVIDER 26 114 #define VIL_COMMAND_TYPE (0x02 << 5) 115 #define VIL_ALL (0x01 << 4) 116 #define PAT (0x01 << 7) 117 #define GRAY (0x01 << 6) 118 #define INV_CLKO (0x01 << 5) 119 #define LPD (0x01 << 4) 120 #define GATEBCLK (0x01 << 7) 121 #define RFS (0x01 << 6) 122 #define MMEN (0x01 << 7) 123 #define TFS(x) ((x & 0x03) << 5) 124 125 126 // Pic 127 #define PIC_FLASH_POINTER_START_ADDRESS_H 0x03 128 #define PIC_FLASH_POINTER_START_ADDRESS_L 0x00 129 #define PIC_FLASH_POINTER_END_ADDRESS_H 0x0f 130 #define PIC_FLASH_POINTER_END_ADDRESS_L 0x7f 131 #define PIC_FLASH_LENGTH (((unsigned int)PIC_FLASH_POINTER_END_ADDRESS_H<<8 + PIC_FLASH_POINTER_END_ADDRESS_L) - ((unsigned int)PIC_FLASH_POINTER_START_ADDRESS_H<<8 + PIC_FLASH_POINTER_START_ADDRESS_L) + 1) 132 #define PIC_FLASH_SECTOR_LENGTH 32 133 #define PIC_SOFTWARE_VERSION_LENGTH 1 134 #define PIC_VOLTAGE_TIME_LENGTH 6 135 #define PIC_COMMAND_1 0x55 136 #define PIC_COMMAND_2 0xaa 137 #define SET_PIC_FLASH_POINTER 0x01 138 #define SEND_DATA_TO_IIC 0x02 // just send data into pic's cache 139 #define READ_DATA_FROM_IIC 0x03 140 #define ERASE_IIC_FLASH 0x04 // erase 32 bytes one time 141 #define WRITE_DATA_INTO_PIC 0x05 // tell pic write data into flash from cache 142 #define JUMP_FROM_LOADER_TO_APP 0x06 143 #define RESET_PIC 0x07 144 #define GET_PIC_FLASH_POINTER 0x08 145 #define ERASE_PIC_APP_PROGRAM 0x09 146 #define SET_VOLTAGE 0x10 147 #define SET_VOLTAGE_TIME 0x11 148 #define SET_HASH_BOARD_ID 0x12 149 #define GET_HASH_BOARD_ID 0x13 150 #define SET_HOST_MAC_ADDRESS 0x14 151 #define ENABLE_VOLTAGE 0x15 152 #define SEND_HEART_BEAT 0x16 153 #define GET_PIC_SOFTWARE_VERSION 0x17 154 #define GET_VOLTAGE 0x18 155 #define GET_DATE 0x19 156 #define GET_WHICH_MAC 0x20 157 #define GET_MAC 0x21 158 #define WR_TEMP_OFFSET_VALUE 0x22 159 #define RD_TEMP_OFFSET_VALUE 0x23 160 161 //diff freq 162 #define PIC_FLASH_POINTER_FREQ_START_ADDRESS_H 0x0F 163 #define PIC_FLASH_POINTER_FREQ_START_ADDRESS_L 0xA0 164 #define PIC_FLASH_POINTER_FREQ_END_ADDRESS_H 0x0f 165 #define PIC_FLASH_POINTER_FREQ_END_ADDRESS_L 0xDF 166 #define FREQ_MAGIC 0x7D 167 168 // BAD CORE NUM 169 #define PIC_FLASH_POINTER_BADCORE_START_ADDRESS_H 0x0F 170 #define PIC_FLASH_POINTER_BADCORE_START_ADDRESS_L 0x80 171 #define PIC_FLASH_POINTER_BADCORE_END_ADDRESS_H 0x0f 172 #define PIC_FLASH_POINTER_BADCORE_END_ADDRESS_L 0x9F 173 #define BADCORE_MAGIC 0x23 // magic number for bad core num 174 175 #define HEART_BEAT_TIME_GAP 10 // 10s 176 #define IIC_READ (1 << 25) 177 #define IIC_WRITE (~IIC_READ) 178 #define IIC_REG_ADDR_VALID (1 << 24) 179 //#define IIC_ADDR_HIGH_4_BIT (0x0A << 20) 180 #define IIC_CHAIN_NUMBER(x) ((x & 0x0f) << 16) 181 #define IIC_REG_ADDR(x) ((x & 0xff) << 8) 182 183 // AT24C02 184 #define AT24C02_ADDRESS 0x50 185 #define EEPROM_LENGTH 256 186 #define HASH_ID_ADDR 0x80 187 #define VOLTAGE_ADDR 0x90 188 #define SENSOR_OFFSET_ADDR 0x98 189 #define VOLTAGE_SET_TIME 0xA0 190 #define VOLTAGE_SET_TIME 0xA0 191 #define FREQ_BADCORE_ADDR 0x00 // 128 bytes 0 - 0x7F 192 193 //other FPGA macro define 194 #define TOTAL_LEN 0x160 195 #define FPGA_MEM_TOTAL_LEN (16*1024*1024) // 16M bytes 196 #define HARDWARE_VERSION_VALUE 0xC501 197 #define NONCE2_AND_JOBID_STORE_SPACE (2*1024*1024) // 2M bytes 198 #define NONCE2_AND_JOBID_STORE_SPACE_ORDER 9 // for 2M bytes space 199 #define JOB_STORE_SPACE (1 << 16) // for 64K bytes space 200 #define JOB_START_SPACE (1024*8) // 8K bytes 201 #define JOB_START_ADDRESS_ALIGN 32 // JOB_START_ADDRESS need 32 bytes aligned 202 #define NONCE2_AND_JOBID_ALIGN 64 // NONCE2_AND_JOBID_STORE_SPACE need 64 bytes aligned 203 #define MAX_TIMEOUT_VALUE 0x1ffff // defined in TIME_OUT_CONTROL 204 #define MAX_NONCE_NUMBER_IN_FIFO 0x1ff // 511 nonce 205 #define NONCE_DATA_LENGTH 4 // 4 bytes 206 #define REGISTER_DATA_LENGTH 4 // 4 bytes 207 #define TW_WRITE_COMMAND_LEN 52 208 #define TW_WRITE_COMMAND_LEN_VIL 52 209 #define NEW_BLOCK_MARKER 0x11 210 #define NORMAL_BLOCK_MARKER 0x01 211 212 // ATTENTION: if MEM size is changed, must change this micro definition too!!! use MAX size (BYTE) - 16 MB as FPGA start memory address 213 #define PHY_MEM_NONCE2_JOBID_ADDRESS_XILINX_1GB ((1024-16)*1024*1024) 214 #define PHY_MEM_NONCE2_JOBID_ADDRESS_XILINX_512MB ((512-16)*1024*1024) // XILINX use 512MB memory 215 #define PHY_MEM_NONCE2_JOBID_ADDRESS_XILINX_256MB ((256-16)*1024*1024) // XILINX use 256MB memory 216 217 #define PHY_MEM_NONCE2_JOBID_ADDRESS_C5 ((1024-16)*1024*1024) 218 extern unsigned int PHY_MEM_NONCE2_JOBID_ADDRESS; 219 220 #define PHY_MEM_JOB_START_ADDRESS_1 (PHY_MEM_NONCE2_JOBID_ADDRESS + NONCE2_AND_JOBID_STORE_SPACE) 221 #define PHY_MEM_JOB_START_ADDRESS_2 (PHY_MEM_JOB_START_ADDRESS_1 + JOB_STORE_SPACE) 222 223 //#include "miner_type.h" // use setminertype to define miner type in this file instead of belows!!! 224 //#define R4 // if defined , for R4 63 chips 225 //#define S9_PLUS // if defined , for T9 57 chips 226 //#define S9_63 // if defined , for S9 63 chips 227 //#define T9_18 // if defined , for T9+ 18 chips 228 229 #define RESET_KEEP_TIME 3 // keep reset signal for 1 secnods 230 #undef USE_OPENCORE_ONEBYONE // if defined, we will use open core one by one, do 114 times on open core for each chain! but NOT WORKS!?? 231 #undef ENABLE_REGISTER_CRC_CHECK //if defined, will drop the register buffer with crc error! 232 #define REBOOT_TEST_ONCE_1HOUR //if defined, will check hashrate after 1 hour, and reboot only once 233 #define ENABLE_FINAL_TEST_WITHOUT_REBOOT // when REBOOT_TEST_ONCE_1HOUR enabeld and this defined, the miner will not reboot after test for 1 hours, then we can save time. test system will treat these miners as good with green color. 234 #define DISABLE_FINAL_TEST //if defined, it will set rebootTestNum=0 and restartNum=2 to indicate the the miner fw is in normal user mode , not test mode 235 #define DISABLE_SHOWX_ENABLE_XTIMES // if defined, will disable x show on web UI, but will enable x times counter in 1 mins 236 #define FASTER_TESTPATTEN // will use 9% timeout to test patten 237 #undef USE_OPENCORE_TWICE 238 #define ENABLE_REINIT_WHEN_TESTFAILED //if defined, when test failed on patten, we set a flag in file, and will use highest voltage according to the limit rules of power and hashrate. 239 #define RESET_HASHBOARD_TIME 15 240 #define ENABLE_CHECK_PIC_FLASH_ADDR // if enabled, will check PIC FLASH ADDR value , set and read back to compare from PIC 241 #define ENABLE_RESTORE_PIC_APP // if enabled, will restore PIC APP when the version is not correct!!! 242 243 #ifdef R4 244 #define USE_N_OFFSET_FIX_TEMP // if defined, we will use n and offset to fix temp value 245 #define EXTEND_TEMP_MODE // if defined, we set temp value area from -64 to 191 as extended temp 246 #define ENABLE_HIGH_VOLTAGE_OPENCORE 247 248 #define PIC_VERSION 0x03 249 250 #define CHAIN_ASIC_NUM 63 251 252 #define R4_MAX_VOLTAGE_C5 890 253 #define R4_MAX_VOLTAGE_XILINX 910 254 255 #define FIX_BAUD_VALUE 1 256 #define UPRATE_PERCENT 1 // means we need reserved more 1% rate 257 258 #define HIGHEST_VOLTAGE_LIMITED_HW 940 //measn the largest voltage, hw can support 259 #define USE_NEW_RESET_FPGA 260 #undef USE_PREINIT_OPENCORE // if defined, we will open core at first ,then get asicnum and do other init process 261 #endif 262 263 #ifdef S9_PLUS 264 #define ENABLE_HIGH_VOLTAGE_OPENCORE 265 266 #define S9_PLUS_VOLTAGE2 //if defined, then it support S9+ new board with new voltage controller 267 268 #define PIC_VERSION 0x03 269 270 #define CHAIN_ASIC_NUM 57 271 #define USE_N_OFFSET_FIX_TEMP // if defined, we will use n and offset to fix temp value 272 #define EXTEND_TEMP_MODE // if defined, we set temp value area from -64 to 191 as extended temp 273 #define HIGHEST_VOLTAGE_LIMITED_HW 970 //measn the largest voltage, hw can support 274 #define FIX_BAUD_VALUE 1 275 #define UPRATE_PERCENT 2 // means we need reserved more 2% rate 276 #define USE_NEW_RESET_FPGA 277 #undef USE_PREINIT_OPENCORE // if defined, we will open core at first ,then get asicnum and do other init process 278 #endif 279 280 #ifdef S9_63 281 #define ENABLE_HIGH_VOLTAGE_OPENCORE 282 283 #define PIC_VERSION 0x03 284 285 #define CHAIN_ASIC_NUM 63 286 #define USE_N_OFFSET_FIX_TEMP // if defined, we will use n and offset to fix temp value 287 #define EXTEND_TEMP_MODE // if defined, we set temp value area from -64 to 191 as extended temp 288 289 #define FIX_BAUD_VALUE 1 290 #define UPRATE_PERCENT 1 // means we need reserved more 1% rate 291 #define HIGHEST_VOLTAGE_LIMITED_HW 940 //measn the largest voltage, hw can support 292 #define USE_NEW_RESET_FPGA 293 #undef USE_PREINIT_OPENCORE // if defined, we will open core at first ,then get asicnum and do other init process 294 #endif 295 296 #ifdef T9_18 297 #define ENABLE_HIGH_VOLTAGE_OPENCORE // T9+ use this , will cause error on chips, because the voltage changing need a long time to balance 298 299 #define PIC_VERSION 0x03 300 301 #define CHAIN_ASIC_NUM 18 302 #define USE_N_OFFSET_FIX_TEMP // if defined, we will use n and offset to fix temp value 303 #define EXTEND_TEMP_MODE // if defined, we set temp value area from -64 to 191 as extended temp 304 305 #define FIX_BAUD_VALUE 1 306 #define UPRATE_PERCENT 2 // means we need reserved more 2% rate 307 #define HIGHEST_VOLTAGE_LIMITED_HW 930 //measn the largest voltage, hw can support 308 #define USE_NEW_RESET_FPGA 309 #undef USE_PREINIT_OPENCORE // if defined, we will open core at first ,then get asicnum and do other init process 310 #endif 311 312 #ifdef USE_PREINIT_OPENCORE 313 #define ENABLE_SET_TICKETMASK_BEFORE_TESTPATTEN // a bug, do not know reason: asic ticket mask > 0 even after reset asic!!! 314 #else 315 #undef ENABLE_SET_TICKETMASK_BEFORE_TESTPATTEN // a bug, do not know reason: asic ticket mask > 0 even after reset asic!!! 316 #endif 317 318 #define ASIC_TYPE 1387 // 1385 or 1387 319 #define CHIP_ADDR_INTERVAL 4 // fix chip address interval = 4 320 #define DEFAULT_BAUD_VALUE 26 321 #define ASIC_CORE_NUM 114 322 323 #define BM1387_CORE_NUM ASIC_CORE_NUM 324 325 // macro define about miner 326 #define BITMAIN_MAX_CHAIN_NUM 16 327 #define BITMAIN_MAX_FAN_NUM 8 // FPGA just can supports 8 fan 328 #define BITMAIN_DEFAULT_ASIC_NUM 64 // max support 64 ASIC on 1 HASH board 329 #define MIDSTATE_LEN 32 330 #define DATA2_LEN 12 331 #define MAX_RETURNED_NONCE_NUM 10 332 #define PREV_HASH_LEN 32 333 #define MERKLE_BIN_LEN 32 334 #define INIT_CONFIG_TYPE 0x51 335 #define STATUS_DATA_TYPE 0xa1 336 #define SEND_JOB_TYPE 0x52 337 #define READ_JOB_TYPE 0xa2 338 #define CHECK_SYSTEM_TIME_GAP 10000 // 10s 339 //fan 340 341 // BELOW IS ALL FOR DEBUG !!! normally all must be undefined!!! 342 #undef DEBUG_FORCE_REINIT //defined to force to reinit with higher voltage 343 #undef DEBUG_KEEP_USE_PIC_VOLTAGE_WITHOUT_CHECKING_VOLTAGE_OF_SEARCHFREQ // if defined, will read pic voltage at first , and use this voltage in mining as working voltage, ignore the backup voltage of search freq 344 #undef DEBUG_ENABLE_I2C_TIMEOUT_PROCESS // if defined, sw will process I2C timeout, but normally FPGA will process timeout, SW do not need this 345 #undef DEBUG_PRINT_T9_PLUS_PIC_HEART_INFO // if defined, used to debug T9+ bug: pic heart cmd failed! 346 #undef DEBUG_PIC_UPGRADE // if defined, we will force to write PIC program data once! 347 #undef DEBUG_KEEP_REBOOT_EVERY_ONE_HOUR // if defined, keep reboot every one hour!!! this is for R4 348 #undef DEBUG_NOT_CHECK_FAN_NUM // if defined, we will ignore fan number checking, will keep run even without any fan!!! 349 #undef DEBUG_WITHOUT_FREQ_VOLTAGE_LIMIT // if defined, we will not limit freq according to voltage! 350 351 #undef DEBUG_DOWN_VOLTAGE_TEST 352 #ifdef DEBUG_DOWN_VOLTAGE_TEST 353 #define DEBUG_DOWN_VOLTAGE_VALUE 10 // means down 0.1 V 354 #endif 355 356 #undef DEBUG_XILINX_NONCE_NOTENOUGH // will disable mutex lock on read temp and send work, but will disable one chain's read temp 357 #ifdef DEBUG_XILINX_NONCE_NOTENOUGH 358 #define DISABLE_REG_CHAIN_INDEX 5 //disable which chain's read register 359 #endif 360 361 #undef DEBUG_OPENCORE_TWICE 362 #undef ENABLE_REINIT_MINING // if defined, will enable hashrate check in mining, and re-init if low hashrate. 363 #undef DEBUG_REINIT // reinit per 2mins and will not do pre heat patten test 364 #undef DEBUG_REBOOT // reboot every 30mins, for test 365 #undef DEBUG_218_FAN_FULLSPEED //for debug on 218, full speed on fan 366 #undef DISABLE_TEMP_PROTECT 367 #undef TWO_CHIP_TEMP_S9 368 #undef SHOW_BOTTOM_TEMP 369 #undef KEEP_TEMPFAN_LOG // if defined, will not clear old temp fan log info 370 #undef HIGH_TEMP_TEST_S9 //if defined, will use 120 degree as the high temp 371 #undef CAPTURE_PATTEN 372 373 #define CHECK_RT_IDEAL_RATE_PERCENT 85 // RT rate / ideal rate >= 85% will be OK, or need re init 374 375 typedef enum 376 { 377 TEMP_POS_LOCAL=0, 378 TEMP_POS_MIDDLE, 379 TEMP_POS_BOTTOM, 380 TEMP_POS_NUM=4, // always the last one, to identify the number of temp , must 4 bytes alignment 381 } TEMP_POSITION; 382 383 #ifdef R4 384 #define PWM_T 0 // 0 local temp, 1 middle temp, 2 bottom, as above!!! 385 386 #define MIN_FAN_NUM 1 387 #define MAX_FAN_SPEED 3000 388 #define TEMP_INTERVAL 2 389 390 // below are used for R4 on using one app to support C5 and XILINX board 391 extern int MIN_PWM_PERCENT; 392 extern int MID_PWM_PERCENT; 393 extern int MAX_PWM_PERCENT; 394 extern int MAX_TEMP; 395 extern int MAX_FAN_TEMP; 396 extern int MID_FAN_TEMP; 397 extern int MIN_FAN_TEMP; 398 extern int MAX_PCB_TEMP; 399 extern int MAX_FAN_PCB_TEMP; 400 401 #if PWM_T == 1 402 #define MIN_PWM_PERCENT_C5 20 403 #define MID_PWM_PERCENT_C5 60 404 #define MAX_PWM_PERCENT_C5 100 405 #define MAX_TEMP_C5 125 406 #define MAX_FAN_TEMP_C5 110 407 #define MID_FAN_TEMP_C5 90 408 #define MIN_FAN_TEMP_C5 60 409 #define MAX_PCB_TEMP_C5 100 // use middle to control fan, but use pcb temp to check to stop or not! 410 #define MAX_FAN_PCB_TEMP_C5 85 //90 use middle to control fan, but use pcb temp to check to stop or not! 411 412 #define MIN_PWM_PERCENT_XILINX 20 413 #define MID_PWM_PERCENT_XILINX 60 414 #define MAX_PWM_PERCENT_XILINX 100 415 #define MAX_TEMP_XILINX 125 416 #define MAX_FAN_TEMP_XILINX 110 417 #define MID_FAN_TEMP_XILINX 90 418 #define MIN_FAN_TEMP_XILINX 60 419 #define MAX_PCB_TEMP_XILINX 100 // use middle to control fan, but use pcb temp to check to stop or not! 420 #define MAX_FAN_PCB_TEMP_XILINX 85 //90 use middle to control fan, but use pcb temp to check to stop or not! 421 #else 422 #define MIN_PWM_PERCENT_C5 50 423 #define MID_PWM_PERCENT_C5 90 424 #define MAX_PWM_PERCENT_C5 100 425 #define MAX_TEMP_C5 90 426 #define MAX_FAN_TEMP_C5 75 427 #define MID_FAN_TEMP_C5 65 428 #define MIN_FAN_TEMP_C5 25 429 #define MAX_PCB_TEMP_C5 90 // use middle to control fan, but use pcb temp to check to stop or not! 430 #define MAX_FAN_PCB_TEMP_C5 85 //90 use middle to control fan, but use pcb temp to check to stop or not! 431 432 #define MIN_PWM_PERCENT_XILINX 30 433 #define MID_PWM_PERCENT_XILINX 70 434 #define MAX_PWM_PERCENT_XILINX 100 435 #define MAX_TEMP_XILINX 90 436 #define MAX_FAN_TEMP_XILINX 75 437 #define MID_FAN_TEMP_XILINX 65 438 #define MIN_FAN_TEMP_XILINX 25 439 #define MAX_PCB_TEMP_XILINX 90 // use middle to control fan, but use pcb temp to check to stop or not! 440 #define MAX_FAN_PCB_TEMP_XILINX 85 //90 use middle to control fan, but use pcb temp to check to stop or not! 441 #endif 442 443 #define TEMP_INTERVAL 2 444 445 #define MID_PWM_ADJUST_FACTOR ((MAX_PWM_PERCENT-MID_PWM_PERCENT)/(MAX_FAN_TEMP-MID_FAN_TEMP)) 446 #define PWM_ADJUST_FACTOR ((MID_PWM_PERCENT-MIN_PWM_PERCENT)/(MID_FAN_TEMP-MIN_FAN_TEMP)) 447 #else 448 // below is for S9 449 #define PWM_T 1 // 0 local temp, 1 middle temp, 2 bottom, as above!!! 450 451 #define MIN_FAN_NUM 2 452 #define MAX_FAN_SPEED 6000 453 #if PWM_T == 1 454 #define MIN_PWM_PERCENT 0 455 #define MAX_PWM_PERCENT 100 456 457 #ifdef HIGH_TEMP_TEST_S9 458 #define MAX_TEMP 135 //125 135 145 release:135 459 #define MAX_FAN_TEMP 120 // 115 125 135 release:120 460 #define MIN_FAN_TEMP 70 //65 75 85 release:70 461 #define MAX_PCB_TEMP 105 //100 105 110 release:105 462 #define MAX_FAN_PCB_TEMP 95 //95 100 105 release:95 463 #define MIN_FAN_PCB_TEMP 45 // Attention: MAX_FAN_PCB_TEMP - MIN_FAN_PCB_TEMP = MAX_FAN_TEMP - MIN_FAN_TEMP 464 #else 465 #ifdef TWO_CHIP_TEMP_S9 466 #define MAX_TEMP 135 //125 135 145 release:135 467 #define MAX_FAN_TEMP 120 // 115 125 135 release:120 468 #define MIN_FAN_TEMP 70 //65 75 85 release:70 469 #define MAX_PCB_TEMP 105 //100 105 110 release:105 470 #define MAX_FAN_PCB_TEMP 95 //95 100 105 release:95 471 #define MIN_FAN_PCB_TEMP 45 // Attention: MAX_FAN_PCB_TEMP - MIN_FAN_PCB_TEMP = MAX_FAN_TEMP - MIN_FAN_TEMP 472 #else 473 #define MAX_TEMP 125 //125 135 145 release:125 474 #define MAX_FAN_TEMP 90 // 115 125 135 release:115 475 #define MIN_FAN_TEMP 40 //65 75 85 release:65 476 #define MAX_PCB_TEMP 90 //100 105 110 release:95 477 #define MAX_FAN_PCB_TEMP 75 //95 100 105 release:85 478 #define MIN_FAN_PCB_TEMP 25 // Attention: MAX_FAN_PCB_TEMP - MIN_FAN_PCB_TEMP = MAX_FAN_TEMP - MIN_FAN_TEMP 479 #endif 480 #endif 481 #else 482 #define MIN_PWM_PERCENT 20 483 #define MAX_PWM_PERCENT 100 484 #define MAX_TEMP 90 485 #define MAX_FAN_TEMP 75 486 #define MIN_FAN_TEMP 35 487 #define MAX_PCB_TEMP 90 // use middle to control fan, but use pcb temp to check to stop or not! 488 #endif 489 #define TEMP_INTERVAL 2 490 #define PWM_ADJUST_FACTOR ((MAX_PWM_PERCENT-MIN_PWM_PERCENT)/(MAX_FAN_TEMP-MIN_FAN_TEMP)) 491 #endif 492 493 #ifdef HIGH_TEMP_TEST_S9 494 #define MIN_TEMP_CONTINUE_DOWN_FAN 110 // release: 90 495 #define MAX_TEMP_NEED_UP_FANSTEP 120 // release: 100 if temp is higher than 100, then we need make fan much faster 496 #else 497 #define MIN_TEMP_CONTINUE_DOWN_FAN 80 // release: 90 498 #define MAX_TEMP_NEED_UP_FANSTEP 85 // release: 100 if temp is higher than 100, then we need make fan much faster 499 #endif 500 501 #define PWM_SCALE 50 //50: 1M=1us, 20KHz?? 502 //25: 40KHz 503 504 #define PWM_ADJ_SCALE 9/10 505 //use for hash test 506 #define TEST_DHASH 0 507 #define DEVICE_DIFF 8 508 //use for status check 509 510 #define MAX_TEMPCHIP_NUM 8 // support 8 chip has temp 511 512 #define MIN_FREQ 4 // 8:300M 6:250M 4:200M 513 #define MAX_FREQ 100 //850M 514 #define MAX_SW_TEMP_OFFSET -15 515 #define BMMINER_VERSION 3 // 3 for auto freq, 1 or 2 for normal ( the old version is 0) 516 517 // for c5, bmminer will detect board type and use it. 518 #define RED_LED_DEV_C5 "/sys/class/leds/hps_led2/brightness" 519 #define GREEN_LED_DEV_C5 "/sys/class/leds/hps_led0/brightness" 520 521 // for xilinx, bmminer will detect board type and use it. 522 #define RED_LED_DEV_XILINX "/sys/class/gpio/gpio943/value" 523 #define GREEN_LED_DEV_XILINX "/sys/class/gpio/gpio944/value" 524 525 // S9 , T9, R4 PIC PROGRAM 526 #define PIC_PROGRAM "/etc/config/hash_s8_app.txt" 527 528 // T9+ PIC PROGRAM 529 #define DSPIC33EP16GS202_PIC_PROGRAM "/etc/config/dsPIC33EP16GS202_app.txt" 530 531 532 #define TIMESLICE 60 533 534 #ifdef T9_18 535 #define IIC_ADDR_HIGH_4_BIT (0x04 << 20) 536 #define EEPROM_ADDR_HIGH_4_BIT (0x0A << 20) 537 #define IIC_SELECT(x) ((x & 0x03) << 26) 538 539 unsigned int get_iic(); 540 unsigned char set_iic(unsigned int data); 541 unsigned char T9_plus_write_pic_iic(bool read, bool reg_addr_valid, unsigned char reg_addr, unsigned char which_iic, unsigned char data); 542 int dsPIC33EP16GS202_jump_to_app_from_loader(unsigned char which_iic); 543 #else 544 #define IIC_ADDR_HIGH_4_BIT (0x0A << 20) 545 #endif 546 547 548 struct init_config 549 { 550 uint8_t token_type; 551 uint8_t version; 552 uint16_t length; 553 uint8_t reset :1; 554 uint8_t fan_eft :1; 555 uint8_t timeout_eft :1; 556 uint8_t frequency_eft :1; 557 uint8_t voltage_eft :1; 558 uint8_t chain_check_time_eft :1; 559 uint8_t chip_config_eft :1; 560 uint8_t hw_error_eft :1; 561 uint8_t beeper_ctrl :1; 562 uint8_t temp_ctrl :1; 563 uint8_t chain_freq_eft :1; 564 uint8_t reserved1 :5; 565 uint8_t reserved2[2]; 566 uint8_t chain_num; 567 uint8_t asic_num; 568 uint8_t fan_pwm_percent; 569 uint8_t temperature; 570 uint16_t frequency; 571 uint8_t voltage[2]; 572 uint8_t chain_check_time_integer; 573 uint8_t chain_check_time_fractions; 574 uint8_t timeout_data_integer; 575 uint8_t timeout_data_fractions; 576 uint32_t reg_data; 577 uint8_t chip_address; 578 uint8_t reg_address; 579 uint16_t chain_min_freq; 580 uint16_t chain_max_freq; 581 uint16_t crc; 582 } __attribute__((packed, aligned(4))); 583 584 585 586 struct bitmain_soc_info 587 { 588 cglock_t update_lock; 589 590 uint8_t data_type; 591 uint8_t version; 592 uint16_t length; 593 uint8_t chip_value_eft :1; 594 uint8_t reserved1 :7; 595 uint8_t chain_num; 596 uint16_t reserved2; 597 uint8_t fan_num; 598 uint8_t temp_num; 599 uint8_t reserved3[2]; 600 uint32_t fan_exist; 601 uint32_t temp_exist; 602 uint16_t diff; 603 uint16_t reserved4; 604 uint32_t reg_value; 605 uint32_t chain_asic_exist[BITMAIN_MAX_CHAIN_NUM][BITMAIN_DEFAULT_ASIC_NUM/32]; 606 uint32_t chain_asic_status[BITMAIN_MAX_CHAIN_NUM][BITMAIN_DEFAULT_ASIC_NUM/32]; 607 uint8_t chain_asic_num[BITMAIN_MAX_CHAIN_NUM]; 608 uint8_t temp[BITMAIN_MAX_CHAIN_NUM]; 609 uint8_t fan_speed_value[BITMAIN_MAX_FAN_NUM]; 610 uint16_t freq[BITMAIN_MAX_CHAIN_NUM]; 611 struct thr_info *thr; 612 pthread_t read_nonce_thr; 613 pthread_mutex_t lock; 614 615 struct init_config soc_config; 616 int pool_no; 617 struct pool pool0; 618 struct pool pool1; 619 struct pool pool2; 620 uint32_t pool0_given_id; 621 uint32_t pool1_given_id; 622 uint32_t pool2_given_id; 623 624 uint16_t crc; 625 } __attribute__((packed, aligned(4))); 626 627 struct part_of_job 628 { 629 uint8_t token_type; // buf[0] 630 uint8_t version; 631 uint16_t reserved; 632 uint32_t length; // buf[1] 633 uint8_t pool_nu; // buf[2] 634 uint8_t new_block :1; 635 uint8_t asic_diff_valid :1; 636 uint8_t reserved1 :6; 637 uint8_t asic_diff; 638 uint8_t reserved2[1]; 639 uint32_t job_id; // buf[3] 640 uint32_t bbversion; // buf[4] 641 uint8_t prev_hash[32]; // buf[5] - buf[12] 642 uint32_t ntime; // buf[13] 643 uint32_t nbit; // buf[14] 644 uint16_t coinbase_len; // buf[15] 645 uint16_t nonce2_offset; 646 uint16_t nonce2_bytes_num; // 4 or 8 bytes // buf[16] 647 uint16_t merkles_num; 648 uint64_t nonce2_start_value; //nonce2 start calculate value. // buf[17] - buf[18] 649 }; 650 //uint8_t coinbase //this is variable 651 //uint8_t merkle_bin[32] * merkles_num 652 //uint16_t crc 653 654 struct nonce_content 655 { 656 uint32_t job_id; 657 uint32_t work_id; 658 uint32_t header_version; 659 uint64_t nonce2; 660 uint32_t nonce3; 661 uint32_t chain_num; 662 uint8_t midstate[MIDSTATE_LEN]; 663 } __attribute__((packed, aligned(4))); 664 665 struct nonce 666 { 667 uint8_t token_type; 668 uint8_t version; 669 uint16_t length; 670 uint16_t valid_nonce_num; 671 struct nonce_content nonce_cont[MAX_RETURNED_NONCE_NUM]; 672 uint16_t crc; 673 } __attribute__((packed, aligned(4))); 674 675 struct all_parameters 676 { 677 678 unsigned int *current_job_start_address; 679 unsigned int pwm_value; 680 unsigned int chain_exist[BITMAIN_MAX_CHAIN_NUM]; 681 unsigned int timeout; 682 unsigned int fan_exist_map; 683 unsigned int temp_sensor_map; 684 unsigned int nonce_error; 685 unsigned int chain_asic_exist[BITMAIN_MAX_CHAIN_NUM][8]; 686 unsigned int chain_asic_status[BITMAIN_MAX_CHAIN_NUM][8]; 687 signed char chain_asic_temp_num[BITMAIN_MAX_CHAIN_NUM]; // the real number of temp chip 688 unsigned char TempChipType[BITMAIN_MAX_CHAIN_NUM][MAX_TEMPCHIP_NUM]; 689 unsigned char TempChipAddr[BITMAIN_MAX_CHAIN_NUM][MAX_TEMPCHIP_NUM]; // each temp chip's address: chip index*4, index start from 0 690 int16_t chain_asic_temp[BITMAIN_MAX_CHAIN_NUM][MAX_TEMPCHIP_NUM][TEMP_POS_NUM]; // 4 kinds of temp 691 int16_t chain_asic_maxtemp[BITMAIN_MAX_CHAIN_NUM][TEMP_POS_NUM]; // 4 kinds of temp 692 int16_t chain_asic_mintemp[BITMAIN_MAX_CHAIN_NUM][TEMP_POS_NUM]; // 4 kinds of temp 693 int8_t chain_asic_iic[CHAIN_ASIC_NUM]; 694 uint32_t chain_hw[BITMAIN_MAX_CHAIN_NUM]; 695 uint64_t chain_asic_nonce[BITMAIN_MAX_CHAIN_NUM][BITMAIN_DEFAULT_ASIC_NUM]; 696 char chain_asic_status_string[BITMAIN_MAX_CHAIN_NUM][BITMAIN_DEFAULT_ASIC_NUM+8]; 697 698 unsigned long long int total_nonce_num; 699 700 unsigned char fan_exist[BITMAIN_MAX_FAN_NUM]; 701 unsigned int fan_speed_value[BITMAIN_MAX_FAN_NUM]; 702 int temp[BITMAIN_MAX_CHAIN_NUM]; 703 uint8_t chain_asic_num[BITMAIN_MAX_CHAIN_NUM]; 704 unsigned char check_bit; 705 unsigned char pwm_percent; 706 unsigned char chain_num; 707 unsigned char fan_num; 708 unsigned char temp_num; 709 unsigned int fan_speed_top1; 710 int temp_top1[TEMP_POS_NUM]; 711 int temp_low1[TEMP_POS_NUM]; 712 int temp_top1_last; 713 unsigned char corenum; 714 unsigned char addrInterval; 715 unsigned char max_asic_num_in_one_chain; 716 unsigned char baud; 717 unsigned char diff; 718 uint8_t fan_eft; 719 uint8_t fan_pwm; 720 721 unsigned short int frequency; 722 char frequency_t[10]; 723 unsigned short int freq[BITMAIN_MAX_CHAIN_NUM]; 724 } __attribute__((packed, aligned(4))); 725 726 727 728 struct nonce_buf 729 { 730 unsigned int p_wr; 731 unsigned int p_rd; 732 unsigned int nonce_num; 733 struct nonce_content nonce_buffer[MAX_NONCE_NUMBER_IN_FIFO]; 734 } __attribute__((packed, aligned(4))); 735 736 struct reg_content 737 { 738 unsigned int reg_value; 739 unsigned char crc; 740 unsigned char chain_number; 741 } __attribute__((packed, aligned(4))); 742 743 struct reg_buf 744 { 745 unsigned int p_wr; 746 unsigned int p_rd; 747 unsigned int reg_value_num; 748 struct reg_content reg_buffer[MAX_NONCE_NUMBER_IN_FIFO]; 749 } __attribute__((packed, aligned(4))); 750 751 struct freq_pll 752 { 753 const char *freq; 754 unsigned int fildiv1; 755 unsigned int fildiv2; 756 unsigned int vilpll; 757 }; 758 759 #define Swap32(l) (((l) >> 24) | (((l) & 0x00ff0000) >> 8) | (((l) & 0x0000ff00) << 8) | ((l) << 24)) 760 761 762 struct vil_work 763 { 764 uint8_t type; // Bit[7:5]: Type,fixed 0x01. Bit[4:0]:Reserved 765 uint8_t length; // data length, from Byte0 to the end. 766 uint8_t wc_base; // Bit[7]: Reserved. Bit[6:0]: Work count base, muti-Midstate, each Midstate corresponding work count increase one by one. 767 uint8_t mid_num; // Bit[7:3]: Reserved Bit[2:0]: MSN, midstate num,now support 1,2,4. 768 //uint32_t sno; // SPAT mode??Start Nonce Number Normal mode??Reserved. 769 uint8_t midstate[32]; 770 uint8_t data2[12]; 771 }; 772 773 struct vil_work_1387 774 { 775 uint8_t work_type; 776 uint8_t chain_id; 777 uint8_t reserved1[2]; 778 uint32_t work_count; 779 uint8_t data[12]; 780 uint8_t midstate[32]; 781 }; 782 783 784 static struct freq_pll freq_pll_1385[] = 785 { 786 {"100",0x020040, 0x0420, 0x200241}, 787 {"125",0x028040, 0x0420, 0x280241}, 788 {"150",0x030040, 0x0420, 0x300241}, 789 {"175",0x038040, 0x0420, 0x380241}, 790 {"200",0x040040, 0x0420, 0x400241}, 791 {"225",0x048040, 0x0420, 0x480241}, 792 {"250",0x050040, 0x0420, 0x500241}, 793 {"275",0x058040, 0x0420, 0x580241}, 794 {"300",0x060040, 0x0420, 0x600241}, 795 {"325",0x068040, 0x0420, 0x680241}, 796 {"350",0x070040, 0x0420, 0x700241}, 797 {"375",0x078040, 0x0420, 0x780241}, 798 {"400",0x080040, 0x0420, 0x800241}, 799 {"404",0x061040, 0x0320, 0x610231}, 800 {"406",0x041040, 0x0220, 0x410221}, 801 {"408",0x062040, 0x0320, 0x620231}, 802 {"412",0x042040, 0x0220, 0x420221}, 803 {"416",0x064040, 0x0320, 0x640231}, 804 {"418",0x043040, 0x0220, 0x430221}, 805 {"420",0x065040, 0x0320, 0x650231}, 806 {"425",0x044040, 0x0220, 0x440221}, 807 {"429",0x067040, 0x0320, 0x670231}, 808 {"431",0x045040, 0x0220, 0x450221}, 809 {"433",0x068040, 0x0320, 0x680231}, 810 {"437",0x046040, 0x0220, 0x460221}, 811 {"441",0x06a040, 0x0320, 0x6a0231}, 812 {"443",0x047040, 0x0220, 0x470221}, 813 {"445",0x06b040, 0x0320, 0x6b0231}, 814 {"450",0x048040, 0x0220, 0x480221}, 815 {"454",0x06d040, 0x0320, 0x6d0231}, 816 {"456",0x049040, 0x0220, 0x490221}, 817 {"458",0x06e040, 0x0320, 0x6e0231}, 818 {"462",0x04a040, 0x0220, 0x4a0221}, 819 {"466",0x070040, 0x0320, 0x700231}, 820 {"468",0x04b040, 0x0220, 0x4b0221}, 821 {"470",0x071040, 0x0320, 0x710231}, 822 {"475",0x04c040, 0x0220, 0x4c0221}, 823 {"479",0x073040, 0x0320, 0x730231}, 824 {"481",0x04d040, 0x0220, 0x4d0221}, 825 {"483",0x074040, 0x0320, 0x740231}, 826 {"487",0x04e040, 0x0220, 0x4e0221}, 827 {"491",0x076040, 0x0320, 0x760231}, 828 {"493",0x04f040, 0x0220, 0x4f0221}, 829 {"495",0x077040, 0x0320, 0x770231}, 830 {"500",0x050040, 0x0220, 0x500221}, 831 {"504",0x079040, 0x0320, 0x790231}, 832 {"506",0x051040, 0x0220, 0x510221}, 833 {"508",0x07a040, 0x0320, 0x7a0231}, 834 {"512",0x052040, 0x0220, 0x520221}, 835 {"516",0x07c040, 0x0320, 0x7c0231}, 836 {"518",0x053040, 0x0220, 0x530221}, 837 {"520",0x07d040, 0x0320, 0x7d0231}, 838 {"525",0x054040, 0x0220, 0x540221}, 839 {"529",0x07f040, 0x0320, 0x7f0231}, 840 {"531",0x055040, 0x0220, 0x550221}, 841 {"533",0x080040, 0x0320, 0x800231}, 842 {"537",0x056040, 0x0220, 0x560221}, 843 {"543",0x057040, 0x0220, 0x570221}, 844 {"550",0x058040, 0x0220, 0x580221}, 845 {"556",0x059040, 0x0220, 0x590221}, 846 {"562",0x05a040, 0x0220, 0x5a0221}, 847 {"568",0x05b040, 0x0220, 0x5b0221}, 848 {"575",0x05c040, 0x0220, 0x5c0221}, 849 {"581",0x05d040, 0x0220, 0x5d0221}, 850 {"587",0x05e040, 0x0220, 0x5e0221}, 851 {"593",0x05f040, 0x0220, 0x5f0221}, 852 {"600",0x060040, 0x0220, 0x600221}, 853 {"606",0x061040, 0x0220, 0x610221}, 854 {"612",0x062040, 0x0220, 0x620221}, 855 {"618",0x063040, 0x0220, 0x630221}, 856 {"625",0x064040, 0x0220, 0x640221}, 857 {"631",0x065040, 0x0220, 0x650221}, 858 {"637",0x066040, 0x0220, 0x660221}, 859 {"643",0x067040, 0x0220, 0x670221}, 860 {"650",0x068040, 0x0220, 0x680221}, 861 {"656",0x069040, 0x0220, 0x690221}, 862 {"662",0x06a040, 0x0220, 0x6a0221}, 863 {"668",0x06b040, 0x0220, 0x6b0221}, 864 {"675",0x06c040, 0x0220, 0x6c0221}, 865 {"681",0x06d040, 0x0220, 0x6d0221}, 866 {"687",0x06e040, 0x0220, 0x6e0221}, 867 {"693",0x06f040, 0x0220, 0x6f0221}, 868 {"700",0x070040, 0x0220, 0x700221}, 869 {"706",0x071040, 0x0220, 0x710221}, 870 {"712",0x072040, 0x0220, 0x720221}, 871 {"718",0x073040, 0x0220, 0x730221}, 872 {"725",0x074040, 0x0220, 0x740221}, 873 {"731",0x075040, 0x0220, 0x750221}, 874 {"737",0x076040, 0x0220, 0x760221}, 875 {"743",0x077040, 0x0220, 0x770221}, 876 {"750",0x078040, 0x0220, 0x780221}, 877 {"756",0x079040, 0x0220, 0x790221}, 878 {"762",0x07a040, 0x0220, 0x7a0221}, 879 {"768",0x07b040, 0x0220, 0x7b0221}, 880 {"775",0x07c040, 0x0220, 0x7c0221}, 881 {"781",0x07d040, 0x0220, 0x7d0221}, 882 {"787",0x07e040, 0x0220, 0x7e0221}, 883 {"793",0x07f040, 0x0220, 0x7f0221}, 884 {"800",0x080040, 0x0220, 0x800221}, 885 {"825",0x042040, 0x0120, 0x420211}, 886 {"850",0x044040, 0x0120, 0x440211}, 887 {"875",0x046040, 0x0120, 0x460211}, 888 {"900",0x048040, 0x0120, 0x480211}, 889 {"925",0x04a040, 0x0120, 0x4a0211}, 890 {"950",0x04c040, 0x0120, 0x4c0211}, 891 {"975",0x04e040, 0x0120, 0x4e0211}, 892 {"1000",0x050040, 0x0120, 0x500211}, 893 {"1025",0x052040, 0x0120, 0x520211}, 894 {"1050",0x054040, 0x0120, 0x540211}, 895 {"1075",0x056040, 0x0120, 0x560211}, 896 {"1100",0x058040, 0x0120, 0x580211}, 897 {"1125",0x05a040, 0x0120, 0x5a0211}, 898 {"1150",0x05c040, 0x0120, 0x5c0211}, 899 {"1175",0x05e040, 0x0120, 0x5e0211}, 900 }; 901 902 extern bool opt_bitmain_fan_ctrl; 903 extern bool opt_bitmain_new_cmd_type_vil; 904 extern bool opt_fixed_freq; 905 extern bool opt_pre_heat; 906 extern int opt_bitmain_fan_pwm; 907 extern int opt_bitmain_soc_freq; 908 extern int opt_bitmain_soc_voltage; 909 extern int ADD_FREQ; 910 extern int ADD_FREQ1; 911 extern int fpga_version; 912 extern int opt_multi_version; 913 914 int getChainExistFlag(int chainIndex); 915 unsigned char get_pic_voltage(unsigned char chain); 916 int getVolValueFromPICvoltage(unsigned char vol_pic); 917 unsigned char getPICvoltageFromValue(int vol_value); 918 void set_pic_voltage(unsigned char chain, unsigned char voltage); 919 int getChainAsicNum(int chainIndex); 920 int readRebootTestNum(); 921 int send_job(unsigned char *buf); 922 923 924 #endif 925