instructions.h
1 /* 2 * Copyright (c) 2019 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28 #ifndef _INSTRUCTIONS_H_ 29 #define _INSTRUCTIONS_H_ 30 31 #define ARM64_INSTR_CAS_MASK (0x3fa07c00) 32 #define ARM64_INSTR_CAS_BITS (0x08a07c00) 33 #define ARM64_INSTR_IS_CAS(x) (((x) & ARM64_INSTR_CAS_MASK) == ARM64_INSTR_CAS_BITS) 34 35 #define ARM64_INSTR_CAS_SZ_MASK 0x3 36 #define ARM64_INSTR_CAS_SZ_SHIFT 30 37 #define ARM64_INSTR_CAS_SZ_GET(x) (((x) >> ARM64_INSTR_CAS_SZ_SHIFT) & ARM64_INSTR_CAS_SZ_MASK) 38 39 #define ARM64_INSTR_CAS_A_MASK 0x1 40 #define ARM64_INSTR_CAS_A_SHIFT 22 41 #define ARM64_INSTR_CAS_A_GET(x) (((x) >> ARM64_INSTR_CAS_A_SHIFT) & ARM64_INSTR_CAS_A_MASK) 42 43 #define ARM64_INSTR_CAS_RS_MASK 0x1f 44 #define ARM64_INSTR_CAS_RS_SHIFT 16 45 #define ARM64_INSTR_CAS_RS_GET(x) (((x) >> ARM64_INSTR_CAS_RS_SHIFT) & ARM64_INSTR_CAS_RS_MASK) 46 47 #define ARM64_INSTR_CAS_R_MASK 0x1 48 #define ARM64_INSTR_CAS_R_SHIFT 15 49 #define ARM64_INSTR_CAS_R_GET(x) (((x) >> ARM64_INSTR_CAS_R_SHIFT) & ARM64_INSTR_CAS_R_MASK) 50 51 #define ARM64_INSTR_CAS_RN_MASK 0x1f 52 #define ARM64_INSTR_CAS_RN_SHIFT 5 53 #define ARM64_INSTR_CAS_RN_GET(x) (((x) >> ARM64_INSTR_CAS_RN_SHIFT) & ARM64_INSTR_CAS_RN_MASK) 54 55 #define ARM64_INSTR_CAS_RT_MASK 0x1f 56 #define ARM64_INSTR_CAS_RT_SHIFT 0 57 #define ARM64_INSTR_CAS_RT_GET(x) (((x) >> ARM64_INSTR_CAS_RT_SHIFT) & ARM64_INSTR_CAS_RT_MASK) 58 59 60 61 #define ARM64_INSTR_CASP_MASK (0xbfa07c00) 62 #define ARM64_INSTR_CASP_BITS (0x08207c00) 63 #define ARM64_INSTR_IS_CASP(x) (((x) & ARM64_INSTR_CASP_MASK) == ARM64_INSTR_CASP_BITS) 64 65 #define ARM64_INSTR_CASP_SZ_MASK 0x1 66 #define ARM64_INSTR_CASP_SZ_SHIFT 30 67 #define ARM64_INSTR_CASP_SZ_GET(x) (((x) >> ARM64_INSTR_CASP_SZ_SHIFT) & ARM64_INSTR_CASP_SZ_MASK) 68 69 #define ARM64_INSTR_CASP_A_MASK 0x1 70 #define ARM64_INSTR_CASP_A_SHIFT 22 71 #define ARM64_INSTR_CASP_A_GET(x) (((x) >> ARM64_INSTR_CASP_A_SHIFT) & ARM64_INSTR_CASP_A_MASK) 72 73 #define ARM64_INSTR_CASP_RS_MASK 0x1f 74 #define ARM64_INSTR_CASP_RS_SHIFT 16 75 #define ARM64_INSTR_CASP_RS_GET(x) (((x) >> ARM64_INSTR_CASP_RS_SHIFT) & ARM64_INSTR_CASP_RS_MASK) 76 77 #define ARM64_INSTR_CASP_R_MASK 0x1 78 #define ARM64_INSTR_CASP_R_SHIFT 15 79 #define ARM64_INSTR_CASP_R_GET(x) (((x) >> ARM64_INSTR_CASP_R_SHIFT) & ARM64_INSTR_CASP_R_MASK) 80 81 #define ARM64_INSTR_CASP_RN_MASK 0x1f 82 #define ARM64_INSTR_CASP_RN_SHIFT 5 83 #define ARM64_INSTR_CASP_RN_GET(x) (((x) >> ARM64_INSTR_CASP_RN_SHIFT) & ARM64_INSTR_CASP_RN_MASK) 84 85 #define ARM64_INSTR_CASP_RT_MASK 0x1f 86 #define ARM64_INSTR_CASP_RT_SHIFT 0 87 #define ARM64_INSTR_CASP_RT_GET(x) (((x) >> ARM64_INSTR_CASP_RT_SHIFT) & ARM64_INSTR_CASP_RT_MASK) 88 89 90 91 #define ARM64_INSTR_ATOMIC_LDST_MASK (0x3f208c00) 92 #define ARM64_INSTR_ATOMIC_LDST_BITS (0x38200000) 93 #define ARM64_INSTR_IS_ATOMIC_LDST(x) (((x) & ARM64_INSTR_ATOMIC_LDST_MASK) == ARM64_INSTR_ATOMIC_LDST_BITS) 94 95 #define ARM64_INSTR_ATOMIC_LDST_SZ_MASK 0x3 96 #define ARM64_INSTR_ATOMIC_LDST_SZ_SHIFT 30 97 #define ARM64_INSTR_ATOMIC_LDST_SZ_GET(x) (((x) >> ARM64_INSTR_ATOMIC_LDST_SZ_SHIFT) & ARM64_INSTR_ATOMIC_LDST_SZ_MASK) 98 99 #define ARM64_INSTR_ATOMIC_LDST_A_MASK 0x1 100 #define ARM64_INSTR_ATOMIC_LDST_A_SHIFT 23 101 #define ARM64_INSTR_ATOMIC_LDST_A_GET(x) (((x) >> ARM64_INSTR_ATOMIC_LDST_A_SHIFT) & ARM64_INSTR_ATOMIC_LDST_A_MASK) 102 103 #define ARM64_INSTR_ATOMIC_LDST_R_MASK 0x1 104 #define ARM64_INSTR_ATOMIC_LDST_R_SHIFT 22 105 #define ARM64_INSTR_ATOMIC_LDST_R_GET(x) (((x) >> ARM64_INSTR_ATOMIC_LDST_R_SHIFT) & ARM64_INSTR_ATOMIC_LDST_R_MASK) 106 107 #define ARM64_INSTR_ATOMIC_LDST_RS_MASK 0x1f 108 #define ARM64_INSTR_ATOMIC_LDST_RS_SHIFT 16 109 #define ARM64_INSTR_ATOMIC_LDST_RS_GET(x) (((x) >> ARM64_INSTR_ATOMIC_LDST_RS_SHIFT) & ARM64_INSTR_ATOMIC_LDST_RS_MASK) 110 111 #define ARM64_INSTR_ATOMIC_LDST_OPC_ADD 0 112 #define ARM64_INSTR_ATOMIC_LDST_OPC_BIC 1 113 #define ARM64_INSTR_ATOMIC_LDST_OPC_EOR 2 114 #define ARM64_INSTR_ATOMIC_LDST_OPC_ORR 3 115 #define ARM64_INSTR_ATOMIC_LDST_OPC_SMAX 4 116 #define ARM64_INSTR_ATOMIC_LDST_OPC_SMIN 5 117 #define ARM64_INSTR_ATOMIC_LDST_OPC_UMAX 6 118 #define ARM64_INSTR_ATOMIC_LDST_OPC_UMIN 7 119 120 #define ARM64_INSTR_ATOMIC_LDST_OPC_MASK 0x7 121 #define ARM64_INSTR_ATOMIC_LDST_OPC_SHIFT 12 122 #define ARM64_INSTR_ATOMIC_LDST_OPC_GET(x) (((x) >> ARM64_INSTR_ATOMIC_LDST_OPC_SHIFT) & ARM64_INSTR_ATOMIC_LDST_OPC_MASK) 123 124 #define ARM64_INSTR_ATOMIC_LDST_RN_MASK 0x1f 125 #define ARM64_INSTR_ATOMIC_LDST_RN_SHIFT 5 126 #define ARM64_INSTR_ATOMIC_LDST_RN_GET(x) (((x) >> ARM64_INSTR_ATOMIC_LDST_RN_SHIFT) & ARM64_INSTR_ATOMIC_LDST_RN_MASK) 127 128 #define ARM64_INSTR_ATOMIC_LDST_RT_MASK 0x1f 129 #define ARM64_INSTR_ATOMIC_LDST_RT_SHIFT 0 130 #define ARM64_INSTR_ATOMIC_LDST_RT_GET(x) (((x) >> ARM64_INSTR_ATOMIC_LDST_RT_SHIFT) & ARM64_INSTR_ATOMIC_LDST_RT_MASK) 131 132 133 134 #define ARM64_INSTR_SWP_MASK (0x3f208c00) 135 #define ARM64_INSTR_SWP_BITS (0x38208000) 136 #define ARM64_INSTR_IS_SWP(x) (((x) & ARM64_INSTR_SWP_MASK) == ARM64_INSTR_SWP_BITS) 137 138 #define ARM64_INSTR_SWP_SZ_MASK 0x3 139 #define ARM64_INSTR_SWP_SZ_SHIFT 30 140 #define ARM64_INSTR_SWP_SZ_GET(x) (((x) >> ARM64_INSTR_SWP_SZ_SHIFT) & ARM64_INSTR_SWP_SZ_MASK) 141 142 #define ARM64_INSTR_SWP_A_MASK 0x1 143 #define ARM64_INSTR_SWP_A_SHIFT 23 144 #define ARM64_INSTR_SWP_A_GET(x) (((x) >> ARM64_INSTR_SWP_A_SHIFT) & ARM64_INSTR_SWP_A_MASK) 145 146 #define ARM64_INSTR_SWP_R_MASK 0x1 147 #define ARM64_INSTR_SWP_R_SHIFT 22 148 #define ARM64_INSTR_SWP_R_GET(x) (((x) >> ARM64_INSTR_SWP_R_SHIFT) & ARM64_INSTR_SWP_R_MASK) 149 150 #define ARM64_INSTR_SWP_RS_MASK 0x1f 151 #define ARM64_INSTR_SWP_RS_SHIFT 16 152 #define ARM64_INSTR_SWP_RS_GET(x) (((x) >> ARM64_INSTR_SWP_RS_SHIFT) & ARM64_INSTR_SWP_RS_MASK) 153 154 #define ARM64_INSTR_SWP_OPC_MASK 0x7 155 #define ARM64_INSTR_SWP_OPC_SHIFT 12 156 #define ARM64_INSTR_SWP_OPC_GET(x) (((x) >> ARM64_INSTR_SWP_OPC_SHIFT) & ARM64_INSTR_SWP_OPC_MASK) 157 158 #define ARM64_INSTR_SWP_RN_MASK 0x1f 159 #define ARM64_INSTR_SWP_RN_SHIFT 5 160 #define ARM64_INSTR_SWP_RN_GET(x) (((x) >> ARM64_INSTR_SWP_RN_SHIFT) & ARM64_INSTR_SWP_RN_MASK) 161 162 #define ARM64_INSTR_SWP_RT_MASK 0x1f 163 #define ARM64_INSTR_SWP_RT_SHIFT 0 164 #define ARM64_INSTR_SWP_RT_GET(x) (((x) >> ARM64_INSTR_SWP_RT_SHIFT) & ARM64_INSTR_SWP_RT_MASK) 165 166 #endif /* _INSTRUCTIONS_H_ */