1  #pragma once
 2  
 3  #include <cstdint>
 4  
 5  // Source file for anything specific to the RISC-V vector extension.
 6  
 7  namespace biscuit {
 8  
 9  /// Describes whether or not an instruction should make use of the mask vector.
10  enum class VecMask : uint32_t {
11      Yes = 0,
12      No = 1,
13  };
14  
15  /// Describes the selected element width.
16  enum class SEW : uint32_t {
17      E8    = 0b000, // 8-bit vector elements
18      E16   = 0b001, // 16-bit vector elements
19      E32   = 0b010, // 32-bit vector elements
20      E64   = 0b011, // 64-bit vector elements
21      E128  = 0b100, // 128-bit vector elements
22      E256  = 0b101, // 256-bit vector elements
23      E512  = 0b110, // 512-bit vector elements
24      E1024 = 0b111, // 1024-bit vector elements
25  };
26  
27  /// Describes the selected register group multiplier.
28  enum class LMUL : uint32_t {
29      M1  = 0b000, // Group of one vector
30      M2  = 0b001, // Groups of two vectors
31      M4  = 0b010, // Groups of four vectors
32      M8  = 0b011, // Groups of eight vectors
33      MF8 = 0b101, // Fractional vector group (1/8)
34      MF4 = 0b110, // Fractional vector group (1/4)
35      MF2 = 0b111, // Fractional vector group (1/2)
36  };
37  
38  /**
39   * Describes whether or not vector masks are agnostic.
40   *
41   * From the RVV spec:
42   *
43   * When a set is marked undisturbed, the corresponding set of
44   * destination elements in a vector register group retain the
45   * value they previously held. 
46   *
47   * When a set is marked agnostic, the corresponding set of destination
48   * elements in any vector destination operand can either retain the value
49   * they previously held, or are overwritten with 1s.
50   *
51   * Within a single vector instruction, each destination element can be either
52   * left undisturbed or overwritten with 1s, in any combination, and the pattern
53   * of undisturbed or overwritten with 1s is not required to be deterministic when
54   * the instruction is executed with the same inputs. In addition, except for
55   * mask load instructions, any element in the tail of a mask result can also be
56   * written with the value the mask-producing operation would have calculated with vl=VLMAX
57   */
58  enum class VMA : uint32_t {
59      No,  // Undisturbed
60      Yes, // Agnostic
61  };
62  
63  /**
64   * Describes whether or not vector tail elements are agnostic.
65   * 
66   * From the RVV spec:
67   *
68   * When a set is marked undisturbed, the corresponding set of
69   * destination elements in a vector register group retain the
70   * value they previously held. 
71   *
72   * When a set is marked agnostic, the corresponding set of destination
73   * elements in any vector destination operand can either retain the value
74   * they previously held, or are overwritten with 1s.
75   *
76   * Within a single vector instruction, each destination element can be either
77   * left undisturbed or overwritten with 1s, in any combination, and the pattern
78   * of undisturbed or overwritten with 1s is not required to be deterministic when
79   * the instruction is executed with the same inputs. In addition, except for
80   * mask load instructions, any element in the tail of a mask result can also be
81   * written with the value the mask-producing operation would have calculated with vl=VLMAX
82   */
83  enum class VTA : uint32_t {
84      No,  // Undisturbed
85      Yes, // Agnostic
86  };
87  
88  } // namespace biscuit