/ hardware / mini_board / picodvi.kicad_pro
picodvi.kicad_pro
  1  {
  2    "board": {
  3      "design_settings": {
  4        "defaults": {
  5          "board_outline_line_width": 0.15,
  6          "copper_line_width": 0.19999999999999998,
  7          "copper_text_italic": false,
  8          "copper_text_size_h": 1.5,
  9          "copper_text_size_v": 1.5,
 10          "copper_text_thickness": 0.3,
 11          "copper_text_upright": false,
 12          "courtyard_line_width": 0.049999999999999996,
 13          "dimension_precision": 4,
 14          "dimension_units": 3,
 15          "dimensions": {
 16            "arrow_length": 1270000,
 17            "extension_offset": 500000,
 18            "keep_text_aligned": true,
 19            "suppress_zeroes": false,
 20            "text_position": 0,
 21            "units_format": 1
 22          },
 23          "fab_line_width": 0.09999999999999999,
 24          "fab_text_italic": false,
 25          "fab_text_size_h": 1.0,
 26          "fab_text_size_v": 1.0,
 27          "fab_text_thickness": 0.15,
 28          "fab_text_upright": false,
 29          "other_line_width": 0.09999999999999999,
 30          "other_text_italic": false,
 31          "other_text_size_h": 1.0,
 32          "other_text_size_v": 1.0,
 33          "other_text_thickness": 0.15,
 34          "other_text_upright": false,
 35          "pads": {
 36            "drill": 0.0,
 37            "height": 4.0,
 38            "width": 3.4
 39          },
 40          "silk_line_width": 0.15,
 41          "silk_text_italic": false,
 42          "silk_text_size_h": 0.0,
 43          "silk_text_size_v": 0.0,
 44          "silk_text_thickness": 0.0,
 45          "silk_text_upright": false,
 46          "zones": {
 47            "45_degree_only": true,
 48            "min_clearance": 0.15
 49          }
 50        },
 51        "diff_pair_dimensions": [
 52          {
 53            "gap": 0.0,
 54            "via_gap": 0.0,
 55            "width": 0.0
 56          }
 57        ],
 58        "drc_exclusions": [],
 59        "meta": {
 60          "filename": "board_design_settings.json",
 61          "version": 2
 62        },
 63        "rule_severities": {
 64          "annular_width": "error",
 65          "clearance": "error",
 66          "copper_edge_clearance": "error",
 67          "courtyards_overlap": "error",
 68          "diff_pair_gap_out_of_range": "error",
 69          "diff_pair_uncoupled_length_too_long": "error",
 70          "drill_out_of_range": "error",
 71          "duplicate_footprints": "warning",
 72          "extra_footprint": "warning",
 73          "hole_clearance": "error",
 74          "hole_near_hole": "error",
 75          "invalid_outline": "error",
 76          "item_on_disabled_layer": "error",
 77          "items_not_allowed": "error",
 78          "length_out_of_range": "error",
 79          "malformed_courtyard": "error",
 80          "microvia_drill_out_of_range": "error",
 81          "missing_courtyard": "ignore",
 82          "missing_footprint": "warning",
 83          "net_conflict": "warning",
 84          "npth_inside_courtyard": "ignore",
 85          "padstack": "error",
 86          "pth_inside_courtyard": "ignore",
 87          "shorting_items": "error",
 88          "silk_over_copper": "error",
 89          "silk_overlap": "error",
 90          "skew_out_of_range": "error",
 91          "too_many_vias": "error",
 92          "track_dangling": "warning",
 93          "track_width": "error",
 94          "tracks_crossing": "error",
 95          "unconnected_items": "error",
 96          "unresolved_variable": "error",
 97          "via_dangling": "warning",
 98          "zone_has_empty_net": "error",
 99          "zones_intersect": "error"
100        },
101        "rules": {
102          "allow_blind_buried_vias": false,
103          "allow_microvias": false,
104          "max_error": 0.005,
105          "min_clearance": 0.0,
106          "min_copper_edge_clearance": 0.075,
107          "min_hole_clearance": 0.0,
108          "min_hole_to_hole": 0.25,
109          "min_microvia_diameter": 0.19999999999999998,
110          "min_microvia_drill": 0.09999999999999999,
111          "min_silk_clearance": 0.0,
112          "min_through_hole_diameter": 0.19999999999999998,
113          "min_track_width": 0.13,
114          "min_via_annular_width": 0.049999999999999996,
115          "min_via_diameter": 0.44999999999999996
116        },
117        "track_widths": [
118          0.0,
119          0.15,
120          0.2,
121          0.3,
122          0.5,
123          1.0
124        ],
125        "via_dimensions": [
126          {
127            "diameter": 0.0,
128            "drill": 0.0
129          },
130          {
131            "diameter": 0.6,
132            "drill": 0.3
133          }
134        ],
135        "zones_allow_external_fillets": false,
136        "zones_use_no_outline": true
137      },
138      "layer_presets": []
139    },
140    "boards": [],
141    "cvpcb": {
142      "equivalence_files": []
143    },
144    "erc": {
145      "erc_exclusions": [],
146      "meta": {
147        "version": 0
148      },
149      "pin_map": [
150        [
151          0,
152          0,
153          0,
154          0,
155          0,
156          0,
157          1,
158          0,
159          0,
160          0,
161          0,
162          2
163        ],
164        [
165          0,
166          2,
167          0,
168          1,
169          0,
170          0,
171          1,
172          0,
173          2,
174          2,
175          2,
176          2
177        ],
178        [
179          0,
180          0,
181          0,
182          0,
183          0,
184          0,
185          1,
186          0,
187          1,
188          0,
189          1,
190          2
191        ],
192        [
193          0,
194          1,
195          0,
196          0,
197          0,
198          0,
199          1,
200          1,
201          2,
202          1,
203          1,
204          2
205        ],
206        [
207          0,
208          0,
209          0,
210          0,
211          0,
212          0,
213          1,
214          0,
215          0,
216          0,
217          0,
218          2
219        ],
220        [
221          0,
222          0,
223          0,
224          0,
225          0,
226          0,
227          0,
228          0,
229          0,
230          0,
231          0,
232          2
233        ],
234        [
235          1,
236          1,
237          1,
238          1,
239          1,
240          0,
241          1,
242          1,
243          1,
244          1,
245          1,
246          2
247        ],
248        [
249          0,
250          0,
251          0,
252          1,
253          0,
254          0,
255          1,
256          0,
257          0,
258          0,
259          0,
260          2
261        ],
262        [
263          0,
264          2,
265          1,
266          2,
267          0,
268          0,
269          1,
270          0,
271          2,
272          2,
273          2,
274          2
275        ],
276        [
277          0,
278          2,
279          0,
280          1,
281          0,
282          0,
283          1,
284          0,
285          2,
286          0,
287          0,
288          2
289        ],
290        [
291          0,
292          2,
293          1,
294          1,
295          0,
296          0,
297          1,
298          0,
299          2,
300          0,
301          0,
302          2
303        ],
304        [
305          2,
306          2,
307          2,
308          2,
309          2,
310          2,
311          2,
312          2,
313          2,
314          2,
315          2,
316          2
317        ]
318      ],
319      "rule_severities": {
320        "bus_definition_conflict": "error",
321        "bus_label_syntax": "error",
322        "bus_to_bus_conflict": "error",
323        "bus_to_net_conflict": "error",
324        "different_unit_footprint": "error",
325        "different_unit_net": "error",
326        "duplicate_reference": "error",
327        "duplicate_sheet_names": "error",
328        "extra_units": "error",
329        "global_label_dangling": "warning",
330        "hier_label_mismatch": "error",
331        "label_dangling": "error",
332        "lib_symbol_issues": "warning",
333        "multiple_net_names": "warning",
334        "net_not_bus_member": "warning",
335        "no_connect_connected": "warning",
336        "no_connect_dangling": "warning",
337        "pin_not_connected": "error",
338        "pin_not_driven": "error",
339        "pin_to_pin": "warning",
340        "power_pin_not_driven": "error",
341        "similar_labels": "warning",
342        "unannotated": "error",
343        "unit_value_mismatch": "error",
344        "unresolved_variable": "error",
345        "wire_dangling": "error"
346      }
347    },
348    "libraries": {
349      "pinned_footprint_libs": [],
350      "pinned_symbol_libs": []
351    },
352    "meta": {
353      "filename": "picodvi.kicad_pro",
354      "version": 1
355    },
356    "net_settings": {
357      "classes": [
358        {
359          "bus_width": 12.0,
360          "clearance": 0.15,
361          "diff_pair_gap": 0.15,
362          "diff_pair_via_gap": 0.25,
363          "diff_pair_width": 0.15,
364          "line_style": 0,
365          "microvia_diameter": 0.3,
366          "microvia_drill": 0.1,
367          "name": "Default",
368          "pcb_color": "rgba(0, 0, 0, 0.000)",
369          "schematic_color": "rgba(0, 0, 0, 0.000)",
370          "track_width": 0.15,
371          "via_diameter": 0.45,
372          "via_drill": 0.2,
373          "wire_width": 6.0
374        },
375        {
376          "bus_width": 12.0,
377          "clearance": 0.13,
378          "diff_pair_gap": 0.15,
379          "diff_pair_via_gap": 0.25,
380          "diff_pair_width": 0.15,
381          "line_style": 0,
382          "microvia_diameter": 0.3,
383          "microvia_drill": 0.1,
384          "name": "Tight",
385          "nets": [
386            "/DVI_CK+",
387            "/DVI_CK-",
388            "/DVI_D0+",
389            "/DVI_D0-",
390            "/DVI_D1+",
391            "/DVI_D1-",
392            "/DVI_D2+",
393            "/DVI_D2-"
394          ],
395          "pcb_color": "rgba(0, 0, 0, 0.000)",
396          "schematic_color": "rgba(0, 0, 0, 0.000)",
397          "track_width": 0.13,
398          "via_diameter": 0.45,
399          "via_drill": 0.2,
400          "wire_width": 6.0
401        },
402        {
403          "bus_width": 12.0,
404          "clearance": 0.13,
405          "diff_pair_gap": 0.13,
406          "diff_pair_via_gap": 0.25,
407          "diff_pair_width": 0.36,
408          "line_style": 0,
409          "microvia_diameter": 0.3,
410          "microvia_drill": 0.1,
411          "name": "USB",
412          "nets": [
413            "/USB_D+",
414            "/USB_D-"
415          ],
416          "pcb_color": "rgba(0, 0, 0, 0.000)",
417          "schematic_color": "rgba(0, 0, 0, 0.000)",
418          "track_width": 0.15,
419          "via_diameter": 0.45,
420          "via_drill": 0.2,
421          "wire_width": 6.0
422        }
423      ],
424      "meta": {
425        "version": 0
426      },
427      "net_colors": null
428    },
429    "pcbnew": {
430      "last_paths": {
431        "gencad": "",
432        "idf": "",
433        "netlist": "",
434        "specctra_dsn": "",
435        "step": "",
436        "vrml": ""
437      },
438      "page_layout_descr_file": ""
439    },
440    "schematic": {
441      "drawing": {
442        "default_bus_thickness": 12.0,
443        "default_junction_size": 36.0,
444        "default_line_thickness": 6.0,
445        "default_text_size": 50.0,
446        "default_wire_thickness": 6.0,
447        "field_names": [],
448        "intersheets_ref_own_page": false,
449        "intersheets_ref_prefix": "",
450        "intersheets_ref_short": false,
451        "intersheets_ref_show": false,
452        "intersheets_ref_suffix": "",
453        "junction_size_choice": 3,
454        "pin_symbol_size": 25.0,
455        "text_offset_ratio": 0.3
456      },
457      "legacy_lib_dir": "",
458      "legacy_lib_list": [],
459      "meta": {
460        "version": 0
461      },
462      "net_format_name": "",
463      "ngspice": {
464        "meta": {
465          "version": 0
466        },
467        "model_mode": 0
468      },
469      "page_layout_descr_file": "",
470      "plot_directory": "",
471      "spice_adjust_passive_values": false,
472      "spice_external_command": "spice \"%I\"",
473      "subpart_first_id": 65,
474      "subpart_id_separator": 0
475    },
476    "sheets": [
477      [
478        "98b19243-63a6-4a2f-a7a3-82f58ab9b34c",
479        ""
480      ]
481    ],
482    "text_variables": {}
483  }