/ libbitfury.c
libbitfury.c
1 /* 2 * Copyright 2014-2015 Con Kolivas 3 * Copyright 2013 Andrew Smith 4 * Copyright 2013 bitfury 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 3 of the License, or (at your option) 9 * any later version. See COPYING for more details. 10 */ 11 12 #include "miner.h" 13 #include "driver-bitfury.h" 14 #include "libbitfury.h" 15 #include "sha2.h" 16 17 void ms3steps(uint32_t *p) 18 { 19 uint32_t a, b, c, d, e, f, g, h, new_e, new_a; 20 int i; 21 22 a = p[0]; 23 b = p[1]; 24 c = p[2]; 25 d = p[3]; 26 e = p[4]; 27 f = p[5]; 28 g = p[6]; 29 h = p[7]; 30 for (i = 0; i < 3; i++) { 31 new_e = p[i+16] + sha256_k[i] + h + CH(e,f,g) + SHA256_F2(e) + d; 32 new_a = p[i+16] + sha256_k[i] + h + CH(e,f,g) + SHA256_F2(e) + 33 SHA256_F1(a) + MAJ(a,b,c); 34 d = c; 35 c = b; 36 b = a; 37 a = new_a; 38 h = g; 39 g = f; 40 f = e; 41 e = new_e; 42 } 43 p[15] = a; 44 p[14] = b; 45 p[13] = c; 46 p[12] = d; 47 p[11] = e; 48 p[10] = f; 49 p[9] = g; 50 p[8] = h; 51 } 52 53 uint32_t decnonce(uint32_t in) 54 { 55 uint32_t out; 56 57 /* First part load */ 58 out = (in & 0xFF) << 24; 59 in >>= 8; 60 61 /* Byte reversal */ 62 in = (((in & 0xaaaaaaaa) >> 1) | ((in & 0x55555555) << 1)); 63 in = (((in & 0xcccccccc) >> 2) | ((in & 0x33333333) << 2)); 64 in = (((in & 0xf0f0f0f0) >> 4) | ((in & 0x0f0f0f0f) << 4)); 65 66 out |= (in >> 2) & 0x3FFFFF; 67 68 /* Extraction */ 69 if (in & 1) 70 out |= (1 << 23); 71 if (in & 2) 72 out |= (1 << 22); 73 74 out -= 0x800004; 75 return out; 76 } 77 78 /* Test vectors to calculate (using address-translated loads) */ 79 static unsigned int atrvec[] = { 80 0xb0e72d8e, 0x1dc5b862, 0xe9e7c4a6, 0x3050f1f5, 0x8a1a6b7e, 0x7ec384e8, 0x42c1c3fc, 0x8ed158a1, /* MIDSTATE */ 81 0,0,0,0,0,0,0,0, 82 0x8a0bb7b7, 0x33af304f, 0x0b290c1a, 0xf0c4e61f, /* WDATA: hashMerleRoot[7], nTime, nBits, nNonce */ 83 }; 84 static bool atrvec_set; 85 86 void bitfury_work_to_payload(struct bitfury_payload *p, struct work *work) 87 { 88 cg_memcpy(p->midstate, work->midstate, 32); 89 p->m7 = *(unsigned int *)(work->data + 64); 90 p->ntime = *(unsigned int *)(work->data + 68); 91 p->nbits = *(unsigned int *)(work->data + 72); 92 applog(LOG_INFO, "INFO nonc: %08x bitfury_scanHash MS0: %08x, ", p->nnonce, 93 ((unsigned int *)work->midstate)[0]); 94 applog(LOG_INFO, "INFO merkle[7]: %08x, ntime: %08x, nbits: %08x", p->m7, 95 p->ntime, p->nbits); 96 } 97 98 /* Configuration registers - control oscillators and such stuff. PROGRAMMED when 99 * magic number matches, UNPROGRAMMED (default) otherwise */ 100 void spi_config_reg(struct bitfury_info *info, int cfgreg, int ena) 101 { 102 static const uint8_t enaconf[4] = { 0xc1, 0x6a, 0x59, 0xe3 }; 103 static const uint8_t disconf[4] = { 0, 0, 0, 0 }; 104 105 if (ena) 106 spi_add_data(info, 0x7000 + cfgreg * 32, enaconf, 4); 107 else 108 spi_add_data(info, 0x7000 + cfgreg * 32, disconf, 4); 109 } 110 111 void spi_set_freq(struct bitfury_info *info) 112 { 113 uint64_t freq; 114 const uint8_t *osc6 = (unsigned char *)&freq; 115 116 freq = (1ULL << info->osc6_bits) - 1ULL; 117 spi_add_data(info, 0x6000, osc6, 8); /* Program internal on-die slow oscillator frequency */ 118 } 119 120 #define FIRST_BASE 61 121 #define SECOND_BASE 4 122 123 void spi_send_conf(struct bitfury_info *info) 124 { 125 const int8_t nfu_counters[16] = { 64, 64, SECOND_BASE, SECOND_BASE+4, SECOND_BASE+2, 126 SECOND_BASE+2+16, SECOND_BASE, SECOND_BASE+1, (FIRST_BASE)%65, (FIRST_BASE+1)%65, 127 (FIRST_BASE+3)%65, (FIRST_BASE+3+16)%65, (FIRST_BASE+4)%65, (FIRST_BASE+4+4)%65, 128 (FIRST_BASE+3+3)%65, (FIRST_BASE+3+1+3)%65 }; 129 int i; 130 131 for (i = 7; i <= 11; i++) 132 spi_config_reg(info, i, 0); 133 spi_config_reg(info, 6, 1); /* disable OUTSLK */ 134 spi_config_reg(info, 4, 1); /* Enable slow oscillator */ 135 for (i = 1; i <= 3; ++i) 136 spi_config_reg(info, i, 0); 137 /* Program counters correctly for rounds processing, here it should 138 * start consuming power */ 139 spi_add_data(info, 0x0100, nfu_counters, 16); 140 } 141 142 void spi_send_init(struct bitfury_info *info) 143 { 144 /* Prepare internal buffers */ 145 /* PREPARE BUFFERS (INITIAL PROGRAMMING) */ 146 unsigned int w[16]; 147 148 if (!atrvec_set) { 149 atrvec_set = true; 150 ms3steps(atrvec); 151 } 152 memset(w, 0, sizeof(w)); 153 w[3] = 0xffffffff; 154 w[4] = 0x80000000; 155 w[15] = 0x00000280; 156 spi_add_data(info, 0x1000, w, 16 * 4); 157 spi_add_data(info, 0x1400, w, 8 * 4); 158 memset(w, 0, sizeof(w)); 159 w[0] = 0x80000000; 160 w[7] = 0x100; 161 spi_add_data(info, 0x1900, w, 8 * 4); /* Prepare MS and W buffers! */ 162 spi_add_data(info, 0x3000, atrvec, 19 * 4); 163 } 164 void spi_clear_buf(struct bitfury_info *info) 165 { 166 info->spibufsz = 0; 167 } 168 169 void spi_add_buf(struct bitfury_info *info, const void *buf, const int sz) 170 { 171 if (unlikely(info->spibufsz + sz > SPIBUF_SIZE)) { 172 applog(LOG_WARNING, "SPI bufsize overflow!"); 173 return; 174 } 175 cg_memcpy(&info->spibuf[info->spibufsz], buf, sz); 176 info->spibufsz += sz; 177 } 178 179 void spi_add_break(struct bitfury_info *info) 180 { 181 spi_add_buf(info, "\x4", 1); 182 } 183 184 void spi_add_fasync(struct bitfury_info *info, int n) 185 { 186 int i; 187 188 for (i = 0; i < n; i++) 189 spi_add_buf(info, "\x5", 1); 190 } 191 192 static void spi_add_buf_reverse(struct bitfury_info *info, const char *buf, const int sz) 193 { 194 int i; 195 196 for (i = 0; i < sz; i++) { // Reverse bit order in each byte! 197 unsigned char p = buf[i]; 198 199 p = ((p & 0xaa) >> 1) | ((p & 0x55) << 1); 200 p = ((p & 0xcc) >> 2) | ((p & 0x33) << 2); 201 p = ((p & 0xf0) >> 4) | ((p & 0x0f) << 4); 202 info->spibuf[info->spibufsz + i] = p; 203 } 204 info->spibufsz += sz; 205 } 206 207 void spi_add_data(struct bitfury_info *info, uint16_t addr, const void *buf, int len) 208 { 209 unsigned char otmp[3]; 210 211 if (len < 4 || len > 128) { 212 applog(LOG_WARNING, "Can't add SPI data size %d", len); 213 return; 214 } 215 len /= 4; /* Strip */ 216 otmp[0] = (len - 1) | 0xE0; 217 otmp[1] = (addr >> 8) & 0xFF; 218 otmp[2] = addr & 0xFF; 219 spi_add_buf(info, otmp, 3); 220 len *= 4; 221 spi_add_buf_reverse(info, buf, len); 222 } 223 224 // Bit-banging reset... Each 3 reset cycles reset first chip in chain 225 bool spi_reset(struct cgpu_info *bitfury, struct bitfury_info *info) 226 { 227 struct mcp_settings *mcp = &info->mcp; 228 int r; 229 230 // SCK_OVRRIDE 231 mcp->value.pin[NFU_PIN_SCK_OVR] = MCP2210_GPIO_PIN_HIGH; 232 mcp->direction.pin[NFU_PIN_SCK_OVR] = MCP2210_GPIO_OUTPUT; 233 mcp->designation.pin[NFU_PIN_SCK_OVR] = MCP2210_PIN_GPIO; 234 if (!mcp2210_set_gpio_settings(bitfury, mcp)) 235 return false; 236 237 for (r = 0; r < 16; ++r) { 238 char buf[1] = {0x81}; // will send this waveform: - _ _ _ _ _ _ - 239 unsigned int length = 1; 240 241 if (!mcp2210_spi_transfer(bitfury, &info->mcp, buf, &length)) 242 return false; 243 } 244 245 // Deactivate override 246 mcp->direction.pin[NFU_PIN_SCK_OVR] = MCP2210_GPIO_INPUT; 247 if (!mcp2210_set_gpio_settings(bitfury, mcp)) 248 return false; 249 250 return true; 251 } 252 253 bool mcp_spi_txrx(struct cgpu_info *bitfury, struct bitfury_info *info) 254 { 255 unsigned int length, sendrcv; 256 int offset = 0; 257 258 length = info->spibufsz; 259 applog(LOG_DEBUG, "%s %d: SPI sending %u bytes total", bitfury->drv->name, 260 bitfury->device_id, length); 261 while (length > MCP2210_TRANSFER_MAX) { 262 sendrcv = MCP2210_TRANSFER_MAX; 263 if (!mcp2210_spi_transfer(bitfury, &info->mcp, info->spibuf + offset, &sendrcv)) 264 return false; 265 if (sendrcv != MCP2210_TRANSFER_MAX) { 266 applog(LOG_DEBUG, "%s %d: Send/Receive size mismatch sent %d received %d", 267 bitfury->drv->name, bitfury->device_id, MCP2210_TRANSFER_MAX, sendrcv); 268 } 269 length -= MCP2210_TRANSFER_MAX; 270 offset += MCP2210_TRANSFER_MAX; 271 } 272 sendrcv = length; 273 if (!mcp2210_spi_transfer(bitfury, &info->mcp, info->spibuf + offset, &sendrcv)) 274 return false; 275 if (sendrcv != length) { 276 applog(LOG_WARNING, "%s %d: Send/Receive size mismatch sent %d received %d", 277 bitfury->drv->name, bitfury->device_id, length, sendrcv); 278 return false; 279 } 280 return true; 281 } 282 283 #define READ_WRITE_BYTES_SPI0 0x31 284 285 bool ftdi_spi_txrx(struct cgpu_info *bitfury, struct bitfury_info *info) 286 { 287 int err, amount, len; 288 uint16_t length; 289 char buf[1024]; 290 291 len = info->spibufsz; 292 length = info->spibufsz - 1; //FTDI length is shifted by one 0x0000 = one byte 293 buf[0] = READ_WRITE_BYTES_SPI0; 294 buf[1] = length & 0x00FF; 295 buf[2] = (length & 0xFF00) >> 8; 296 cg_memcpy(&buf[3], info->spibuf, info->spibufsz); 297 info->spibufsz += 3; 298 err = usb_write(bitfury, buf, info->spibufsz, &amount, C_BXM_SPITX); 299 if (err || amount != (int)info->spibufsz) { 300 applog(LOG_ERR, "%s %d: SPI TX error %d, sent %d of %d", bitfury->drv->name, 301 bitfury->device_id, err, amount, info->spibufsz); 302 return false; 303 } 304 info->spibufsz = len; 305 /* We shouldn't even get a timeout error on reads in spi mode */ 306 err = usb_read(bitfury, info->spibuf, len, &amount, C_BXM_SPIRX); 307 if (err || amount != len) { 308 applog(LOG_ERR, "%s %d: SPI RX error %d, read %d of %d", bitfury->drv->name, 309 bitfury->device_id, err, amount, info->spibufsz); 310 return false; 311 } 312 amount = usb_buffer_size(bitfury); 313 if (amount) { 314 applog(LOG_ERR, "%s %d: SPI RX Extra read buffer size %d", bitfury->drv->name, 315 bitfury->device_id, amount); 316 usb_buffer_clear(bitfury); 317 return false; 318 } 319 return true; 320 } 321 322 #define BT_OFFSETS 3 323 324 bool bitfury_checkresults(struct thr_info *thr, struct work *work, uint32_t nonce) 325 { 326 const uint32_t bf_offsets[] = {-0x800000, 0, -0x400000}; 327 int i; 328 329 for (i = 0; i < BT_OFFSETS; i++) { 330 uint32_t noffset = nonce + bf_offsets[i]; 331 332 if (test_nonce(work, noffset)) { 333 submit_tested_work(thr, work); 334 return true; 335 } 336 } 337 return false; 338 } 339 340 /* Currently really only supports 2 chips, so chip_n can only be 0 or 1 */ 341 bool libbitfury_sendHashData(struct thr_info *thr, struct cgpu_info *bitfury, 342 struct bitfury_info *info, int chip_n) 343 { 344 unsigned newbuf[17]; 345 unsigned *oldbuf = &info->oldbuf[17 * chip_n]; 346 struct bitfury_payload *p = &info->payload[chip_n]; 347 unsigned int localvec[20]; 348 349 /* Programming next value */ 350 cg_memcpy(localvec, p, 20 * 4); 351 ms3steps(localvec); 352 353 spi_clear_buf(info); 354 spi_add_break(info); 355 spi_add_fasync(info, chip_n); 356 spi_add_data(info, 0x3000, (void*)localvec, 19 * 4); 357 if (!info->spi_txrx(bitfury, info)) 358 return false; 359 360 cg_memcpy(newbuf, info->spibuf + 4 + chip_n, 17 * 4); 361 362 info->job_switched[chip_n] = newbuf[16] != oldbuf[16]; 363 364 if (likely(info->second_run[chip_n])) { 365 if (info->job_switched[chip_n]) { 366 int i; 367 368 for (i = 0; i < 16; i++) { 369 if (oldbuf[i] != newbuf[i] && info->owork[chip_n]) { 370 uint32_t nonce; //possible nonce 371 372 nonce = decnonce(newbuf[i]); 373 if (bitfury_checkresults(thr, info->owork[chip_n], nonce)) { 374 info->submits[chip_n]++; 375 info->nonces++; 376 } 377 } 378 } 379 cg_memcpy(oldbuf, newbuf, 17 * 4); 380 } 381 } else 382 info->second_run[chip_n] = true; 383 384 cgsleep_ms(BITFURY_REFRESH_DELAY); 385 386 return true; 387 }