USI_TWI_Master.h
1 /***************************************************************************** 2 * 3 * 4 * File USI_TWI_Master.h compiled with gcc 5 * Date Friday, 10/31/08 Boo! 6 * Updated by jkl 7 * 8 * 9 * Supported devices : All device with USI module can be used. 10 * The example is written for the ATtiny2313 11 * 12 * AppNote : AVR310 - Using the USI module as a TWI Master 13 * 14 * This is modified to just do I2C communication on ATtiny2313 running at 15 * 1MHz. Fast mode is probably possible, but would need a faster clock 16 * and has not been tested. 17 * 18 * 12/15/08 Added declaration of USI_TWI_Start_Memory_Read -jkl 19 ****************************************************************************/ 20 21 //********** Defines **********// 22 23 // Defines controlling timing limits - SCL <= 100KHz. 24 25 // For use with _delay_us() 26 #define T2_TWI 5 // >4,7us 27 #define T4_TWI 4 // >4,0us 28 29 // Defines error code generating 30 //#define PARAM_VERIFICATION 31 //#define NOISE_TESTING 32 #define SIGNAL_VERIFY // This should probably be on always. 33 34 /**************************************************************************** 35 Bit and byte definitions 36 ****************************************************************************/ 37 #define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte". 38 #define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte. 39 #define TWI_NACK_BIT 0 // Bit position for (N)ACK bit. 40 41 // Note these have been renumbered from the Atmel Apps Note. Most likely errors are now 42 // lowest numbers so they're easily recognized as LED flashes. 43 #define USI_TWI_NO_DATA 0x08 // Transmission buffer is empty 44 #define USI_TWI_DATA_OUT_OF_BOUND 0x09 // Transmission buffer is outside SRAM space 45 #define USI_TWI_UE_START_CON 0x07 // Unexpected Start Condition 46 #define USI_TWI_UE_STOP_CON 0x06 // Unexpected Stop Condition 47 #define USI_TWI_UE_DATA_COL 0x05 // Unexpected Data Collision (arbitration) 48 #define USI_TWI_NO_ACK_ON_DATA 0x02 // The slave did not acknowledge all data 49 #define USI_TWI_NO_ACK_ON_ADDRESS 0x01 // The slave did not acknowledge the address 50 #define USI_TWI_MISSING_START_CON 0x03 // Generated Start Condition not detected on bus 51 #define USI_TWI_MISSING_STOP_CON 0x04 // Generated Stop Condition not detected on bus 52 #define USI_TWI_BAD_MEM_READ 0x0A // Error during external memory read 53 54 // Device dependant defines ADDED BACK IN FROM ORIGINAL ATMEL .H 55 56 #if defined(__AVR_AT90Mega169__) | defined(__AVR_ATmega169__) | \ 57 defined(__AVR_AT90Mega165__) | defined(__AVR_ATmega165__) | \ 58 defined(__AVR_ATmega325__) | defined(__AVR_ATmega3250__) | \ 59 defined(__AVR_ATmega645__) | defined(__AVR_ATmega6450__) | \ 60 defined(__AVR_ATmega329__) | defined(__AVR_ATmega3290__) | \ 61 defined(__AVR_ATmega649__) | defined(__AVR_ATmega6490__) 62 #define DDR_USI DDRE 63 #define PORT_USI PORTE 64 #define PIN_USI PINE 65 #define PORT_USI_SDA PORTE5 66 #define PORT_USI_SCL PORTE4 67 #define PIN_USI_SDA PINE5 68 #define PIN_USI_SCL PINE4 69 #endif 70 71 #if defined(__AVR_ATtiny25__) | defined(__AVR_ATtiny45__) | defined(__AVR_ATtiny85__) | \ 72 defined(__AVR_AT90Tiny26__) | defined(__AVR_ATtiny26__) 73 #define DDR_USI DDRB 74 #define PORT_USI PORTB 75 #define PIN_USI PINB 76 #define PORT_USI_SDA PORTB0 77 #define PORT_USI_SCL PORTB2 78 #define PIN_USI_SDA PINB0 79 #define PIN_USI_SCL PINB2 80 #endif 81 82 #if defined(__AVR_ATtiny84__) | defined(__AVR_ATtiny44__) 83 # define DDR_USI DDRA 84 # define PORT_USI PORTA 85 # define PIN_USI PINA 86 # define PORT_USI_SDA PORTA6 87 # define PORT_USI_SCL PORTA4 88 # define PIN_USI_SDA PINA6 89 # define PIN_USI_SCL PINA4 90 #endif 91 92 #if defined(__AVR_AT90Tiny2313__) | defined(__AVR_ATtiny2313__) 93 #define DDR_USI DDRB 94 #define PORT_USI PORTB 95 #define PIN_USI PINB 96 #define PORT_USI_SDA PORTB5 97 #define PORT_USI_SCL PORTB7 98 #define PIN_USI_SDA PINB5 99 #define PIN_USI_SCL PINB7 100 #endif 101 102 /* From the original .h 103 // Device dependant defines - These for ATtiny2313. // CHANGED FOR ATtiny85 104 105 #define DDR_USI DDRB 106 #define PORT_USI PORTB 107 #define PIN_USI PINB 108 #define PORT_USI_SDA PORTB0 // was PORTB5 - N/U 109 #define PORT_USI_SCL PORTB2 // was PORTB7 - N/U 110 #define PIN_USI_SDA PINB0 // was PINB5 111 #define PIN_USI_SCL PINB2 // was PINB7 112 */ 113 114 // General defines 115 #define TRUE 1 116 #define FALSE 0 117 118 //********** Prototypes **********// 119 120 void TinyM_USI_TWI_Master_Initialise( void ); 121 unsigned char TinyM_USI_TWI_Start_Random_Read( unsigned char * , unsigned char ); 122 unsigned char TinyM_USI_TWI_Start_Read_Write( unsigned char * , unsigned char ); 123 unsigned char TinyM_USI_TWI_Master_Stop( void ); 124 unsigned char TinyM_USI_TWI_Get_State_Info( void );