coreboot_tables.h
1 /* 2 * 3 * Copyright (C) 2008 Advanced Micro Devices, Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _COREBOOT_TABLES_H 30 #define _COREBOOT_TABLES_H 31 32 #include <arch/types.h> 33 #include <commonlib/bsd/ipchksum.h> 34 #include <stdint.h> 35 36 enum { 37 CB_TAG_UNUSED = 0x0000, 38 CB_TAG_MEMORY = 0x0001, 39 CB_TAG_HWRPB = 0x0002, 40 CB_TAG_MAINBOARD = 0x0003, 41 CB_TAG_VERSION = 0x0004, 42 CB_TAG_EXTRA_VERSION = 0x0005, 43 CB_TAG_BUILD = 0x0006, 44 CB_TAG_COMPILE_TIME = 0x0007, 45 CB_TAG_COMPILE_BY = 0x0008, 46 CB_TAG_COMPILE_HOST = 0x0009, 47 CB_TAG_COMPILE_DOMAIN = 0x000a, 48 CB_TAG_COMPILER = 0x000b, 49 CB_TAG_LINKER = 0x000c, 50 CB_TAG_ASSEMBLER = 0x000d, 51 CB_TAG_SERIAL = 0x000f, 52 CB_TAG_CONSOLE = 0x0010, 53 CB_TAG_FORWARD = 0x0011, 54 CB_TAG_FRAMEBUFFER = 0x0012, 55 CB_TAG_GPIO = 0x0013, 56 CB_TAG_TIMESTAMPS = 0x0016, 57 CB_TAG_CBMEM_CONSOLE = 0x0017, 58 CB_TAG_MRC_CACHE = 0x0018, 59 CB_TAG_VBNV = 0x0019, 60 CB_TAG_VBOOT_HANDOFF = 0x0020, /* deprecated */ 61 CB_TAG_X86_ROM_MTRR = 0x0021, 62 CB_TAG_DMA = 0x0022, 63 CB_TAG_RAM_OOPS = 0x0023, 64 CB_TAG_ACPI_GNVS = 0x0024, 65 CB_TAG_BOARD_ID = 0x0025, 66 CB_TAG_VERSION_TIMESTAMP = 0x0026, 67 CB_TAG_WIFI_CALIBRATION = 0x0027, 68 CB_TAG_RAM_CODE = 0x0028, 69 CB_TAG_SPI_FLASH = 0x0029, 70 CB_TAG_SERIALNO = 0x002a, 71 CB_TAG_MTC = 0x002b, 72 CB_TAG_VPD = 0x002c, 73 CB_TAG_SKU_ID = 0x002d, 74 CB_TAG_BOOT_MEDIA_PARAMS = 0x0030, 75 CB_TAG_CBMEM_ENTRY = 0x0031, 76 CB_TAG_TSC_INFO = 0x0032, 77 CB_TAG_MAC_ADDRS = 0x0033, 78 CB_TAG_VBOOT_WORKBUF = 0x0034, 79 CB_TAG_MMC_INFO = 0x0035, 80 CB_TAG_TCPA_LOG = 0x0036, 81 CB_TAG_FMAP = 0x0037, 82 CB_TAG_SMMSTOREV2 = 0x0039, 83 CB_TAG_BOARD_CONFIG = 0x0040, 84 CB_TAG_ACPI_CNVS = 0x0041, 85 CB_TAG_TYPE_C_INFO = 0x0042, 86 CB_TAG_ACPI_RSDP = 0x0043, 87 CB_TAG_PCIE = 0x0044, 88 CB_TAG_CMOS_OPTION_TABLE = 0x00c8, 89 CB_TAG_OPTION = 0x00c9, 90 CB_TAG_OPTION_ENUM = 0x00ca, 91 CB_TAG_OPTION_DEFAULTS = 0x00cb, 92 CB_TAG_OPTION_CHECKSUM = 0x00cc, 93 }; 94 95 typedef __aligned(4) uint64_t cb_uint64_t; 96 97 struct cb_header { 98 u8 signature[4]; 99 u32 header_bytes; 100 u32 header_checksum; 101 u32 table_bytes; 102 u32 table_checksum; 103 u32 table_entries; 104 }; 105 106 struct cb_record { 107 u32 tag; 108 u32 size; 109 }; 110 111 struct cb_memory_range { 112 cb_uint64_t start; 113 cb_uint64_t size; 114 u32 type; 115 }; 116 117 #define CB_MEM_RAM 1 118 #define CB_MEM_RESERVED 2 119 #define CB_MEM_ACPI 3 120 #define CB_MEM_NVS 4 121 #define CB_MEM_UNUSABLE 5 122 #define CB_MEM_VENDOR_RSVD 6 123 #define CB_MEM_TABLE 16 124 125 struct cb_memory { 126 u32 tag; 127 u32 size; 128 struct cb_memory_range map[]; 129 }; 130 131 struct cb_hwrpb { 132 u32 tag; 133 u32 size; 134 u64 hwrpb; 135 }; 136 137 struct cb_mainboard { 138 u32 tag; 139 u32 size; 140 u8 vendor_idx; 141 u8 part_number_idx; 142 u8 strings[]; 143 }; 144 145 enum type_c_orientation { 146 TYPEC_ORIENTATION_NONE, 147 TYPEC_ORIENTATION_NORMAL, 148 TYPEC_ORIENTATION_REVERSE, 149 }; 150 151 struct type_c_port_info { 152 /* 153 * usb2_port_number and usb3_port_number are expected to be 154 * the port numbers as seen by the USB controller in the SoC. 155 */ 156 uint8_t usb2_port_number; 157 uint8_t usb3_port_number; 158 159 /* 160 * Valid sbu_orientation and data_orientation values will be of 161 * type enum type_c_orienation. 162 */ 163 uint8_t sbu_orientation; 164 uint8_t data_orientation; 165 }; 166 167 struct type_c_info { 168 u32 port_count; 169 struct type_c_port_info port_info[]; 170 }; 171 172 struct cb_string { 173 u32 tag; 174 u32 size; 175 u8 string[]; 176 }; 177 178 struct cb_serial { 179 u32 tag; 180 u32 size; 181 #define CB_SERIAL_TYPE_IO_MAPPED 1 182 #define CB_SERIAL_TYPE_MEMORY_MAPPED 2 183 u32 type; 184 u32 baseaddr; 185 u32 baud; 186 u32 regwidth; 187 188 /* Crystal or input frequency to the chip containing the UART. 189 * Provide the board specific details to allow the payload to 190 * initialize the chip containing the UART and make independent 191 * decisions as to which dividers to select and their values 192 * to eventually arrive at the desired console baud-rate. */ 193 u32 input_hertz; 194 }; 195 196 struct cb_console { 197 u32 tag; 198 u32 size; 199 u16 type; 200 }; 201 202 #define CB_TAG_CONSOLE_SERIAL8250 0 203 #define CB_TAG_CONSOLE_VGA 1 // OBSOLETE 204 #define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE 205 #define CB_TAG_CONSOLE_LOGBUF 3 // OBSOLETE 206 #define CB_TAG_CONSOLE_SROM 4 // OBSOLETE 207 #define CB_TAG_CONSOLE_EHCI 5 208 209 struct cb_forward { 210 u32 tag; 211 u32 size; 212 u64 forward; 213 }; 214 215 /* Panel orientation, matches drm_connector.h in the Linux kernel. */ 216 enum cb_fb_orientation { 217 CB_FB_ORIENTATION_NORMAL = 0, 218 CB_FB_ORIENTATION_BOTTOM_UP = 1, 219 CB_FB_ORIENTATION_LEFT_UP = 2, 220 CB_FB_ORIENTATION_RIGHT_UP = 3, 221 }; 222 223 struct cb_framebuffer_flags { 224 u8 has_external_display : 1; 225 u8 reserved : 7; 226 }; 227 228 struct cb_framebuffer { 229 u32 tag; 230 u32 size; 231 232 u64 physical_address; 233 u32 x_resolution; 234 u32 y_resolution; 235 u32 bytes_per_line; 236 u8 bits_per_pixel; 237 u8 red_mask_pos; 238 u8 red_mask_size; 239 u8 green_mask_pos; 240 u8 green_mask_size; 241 u8 blue_mask_pos; 242 u8 blue_mask_size; 243 u8 reserved_mask_pos; 244 u8 reserved_mask_size; 245 u8 orientation; 246 struct cb_framebuffer_flags flags; 247 u8 pad; 248 }; 249 250 #define CB_GPIO_ACTIVE_LOW 0 251 #define CB_GPIO_ACTIVE_HIGH 1 252 #define CB_GPIO_MAX_NAME_LENGTH 16 253 struct cb_gpio { 254 u32 port; 255 u32 polarity; 256 u32 value; 257 u8 name[CB_GPIO_MAX_NAME_LENGTH]; 258 }; 259 260 struct cb_gpios { 261 u32 tag; 262 u32 size; 263 264 u32 count; 265 struct cb_gpio gpios[]; 266 }; 267 268 struct cb_pcie { 269 uint32_t tag; 270 uint32_t size; 271 cb_uint64_t ctrl_base; /* Base address of PCIe controller */ 272 }; 273 274 struct lb_range { 275 uint32_t tag; 276 uint32_t size; 277 cb_uint64_t range_start; 278 uint32_t range_size; 279 }; 280 281 struct cb_cbmem_tab { 282 uint32_t tag; 283 uint32_t size; 284 cb_uint64_t cbmem_tab; 285 }; 286 287 struct cb_x86_rom_mtrr { 288 uint32_t tag; 289 uint32_t size; 290 /* The variable range MTRR index covering the ROM. If one wants to 291 * enable caching the ROM, the variable MTRR needs to be set to 292 * write-protect. To disable the caching after enabling set the 293 * type to uncacheable. */ 294 uint32_t index; 295 }; 296 297 /* Memory map windows to translate addresses between SPI flash space and host address space. */ 298 struct flash_mmap_window { 299 uint32_t flash_base; 300 uint32_t host_base; 301 uint32_t size; 302 }; 303 304 struct cb_spi_flash { 305 uint32_t tag; 306 uint32_t size; 307 uint32_t flash_size; 308 uint32_t sector_size; 309 uint32_t erase_cmd; 310 /* 311 * Number of mmap windows used by the platform to decode addresses between SPI flash 312 * space and host address space. This determines the number of entries in mmap_table. 313 */ 314 uint32_t mmap_count; 315 struct flash_mmap_window mmap_table[]; 316 }; 317 318 struct cb_boot_media_params { 319 uint32_t tag; 320 uint32_t size; 321 /* offsets are relative to start of boot media */ 322 cb_uint64_t fmap_offset; 323 cb_uint64_t cbfs_offset; 324 cb_uint64_t cbfs_size; 325 cb_uint64_t boot_media_size; 326 }; 327 328 329 struct cb_cbmem_entry { 330 uint32_t tag; 331 uint32_t size; 332 333 cb_uint64_t address; 334 uint32_t entry_size; 335 uint32_t id; 336 }; 337 338 struct cb_tsc_info { 339 uint32_t tag; 340 uint32_t size; 341 342 uint32_t freq_khz; 343 }; 344 345 struct mac_address { 346 uint8_t mac_addr[6]; 347 uint8_t pad[2]; /* Pad it to 8 bytes to keep it simple. */ 348 }; 349 350 struct cb_macs { 351 uint32_t tag; 352 uint32_t size; 353 uint32_t count; 354 struct mac_address mac_addrs[]; 355 }; 356 357 struct cb_mmc_info { 358 uint32_t tag; 359 uint32_t size; 360 /* 361 * Passes the early mmc status to payload to indicate if firmware 362 * successfully sent CMD0, CMD1 to the card or not. In case of 363 * success, the payload can skip the first step of the initialization 364 * sequence which is to send CMD0, and instead start by sending CMD1 365 * as described in Jedec Standard JESD83-B1 section 6.4.3. 366 * passes 1 on success 367 */ 368 int32_t early_cmd1_status; 369 }; 370 371 struct cb_board_config { 372 uint32_t tag; 373 uint32_t size; 374 375 cb_uint64_t fw_config; 376 uint32_t board_id; 377 uint32_t ram_code; 378 uint32_t sku_id; 379 }; 380 381 #define CB_MAX_SERIALNO_LENGTH 32 382 383 struct cb_cmos_option_table { 384 u32 tag; 385 u32 size; 386 u32 header_length; 387 }; 388 389 #define CB_CMOS_MAX_NAME_LENGTH 32 390 struct cb_cmos_entries { 391 u32 tag; 392 u32 size; 393 u32 bit; 394 u32 length; 395 u32 config; 396 u32 config_id; 397 u8 name[CB_CMOS_MAX_NAME_LENGTH]; 398 }; 399 400 #define CB_CMOS_MAX_TEXT_LENGTH 32 401 struct cb_cmos_enums { 402 u32 tag; 403 u32 size; 404 u32 config_id; 405 u32 value; 406 u8 text[CB_CMOS_MAX_TEXT_LENGTH]; 407 }; 408 409 #define CB_CMOS_IMAGE_BUFFER_SIZE 128 410 struct cb_cmos_defaults { 411 u32 tag; 412 u32 size; 413 u32 name_length; 414 u8 name[CB_CMOS_MAX_NAME_LENGTH]; 415 u8 default_set[CB_CMOS_IMAGE_BUFFER_SIZE]; 416 }; 417 418 #define CB_CHECKSUM_NONE 0 419 #define CB_CHECKSUM_PCBIOS 1 420 struct cb_cmos_checksum { 421 u32 tag; 422 u32 size; 423 u32 range_start; 424 u32 range_end; 425 u32 location; 426 u32 type; 427 }; 428 429 /* 430 * Handoff the ACPI RSDP 431 */ 432 struct cb_acpi_rsdp { 433 uint32_t tag; 434 uint32_t size; 435 cb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */ 436 }; 437 438 439 /* Helpful inlines */ 440 441 static inline u16 cb_checksum(const void *ptr, unsigned len) 442 { 443 return ipchksum(ptr, len); 444 } 445 446 static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm) 447 { 448 return (char *)(cbm->strings + cbm->vendor_idx); 449 } 450 451 static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) 452 { 453 return (char *)(cbm->strings + cbm->part_number_idx); 454 } 455 456 /* Helpful macros */ 457 458 #define MEM_RANGE_COUNT(_rec) \ 459 (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0])) 460 461 #define MEM_RANGE_PTR(_rec, _idx) \ 462 (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ 463 + (sizeof((_rec)->map[0]) * (_idx))) 464 465 #endif