1  /*
  2   *
  3   * Copyright (C) 2008 Advanced Micro Devices, Inc.
  4   * Copyright (C) 2008 coresystems GmbH
  5   *
  6   * Redistribution and use in source and binary forms, with or without
  7   * modification, are permitted provided that the following conditions
  8   * are met:
  9   * 1. Redistributions of source code must retain the above copyright
 10   *    notice, this list of conditions and the following disclaimer.
 11   * 2. Redistributions in binary form must reproduce the above copyright
 12   *    notice, this list of conditions and the following disclaimer in the
 13   *    documentation and/or other materials provided with the distribution.
 14   * 3. The name of the author may not be used to endorse or promote products
 15   *    derived from this software without specific prior written permission.
 16   *
 17   * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 18   * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 19   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 20   * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 21   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 22   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 23   * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 24   * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 25   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 26   * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 27   * SUCH DAMAGE.
 28   */
 29  
 30  #ifndef _PCI_H
 31  #define _PCI_H
 32  
 33  #include <arch/types.h>
 34  #include <stdint.h>
 35  
 36  typedef u32 pcidev_t;
 37  
 38  /* Device config space registers. */
 39  #define REG_VENDOR_ID           0x00
 40  #define REG_DEVICE_ID           0x02
 41  #define REG_COMMAND             0x04
 42  #define REG_STATUS              0x06
 43  #define REG_REVISION_ID         0x08
 44  #define REG_PROG_IF             0x09
 45  #define REG_SUBCLASS            0x0A
 46  #define REG_CLASS               0x0B
 47  #define REG_CACHE_LINE_SIZE     0x0C
 48  #define REG_LATENCY_TIMER       0x0D
 49  #define REG_HEADER_TYPE         0x0E
 50  #define REG_BIST                0x0F
 51  #define REG_BAR0                0x10
 52  #define REG_BAR1                0x14
 53  #define REG_BAR2                0x18
 54  #define REG_BAR3                0x1C
 55  #define REG_BAR4                0x20
 56  #define REG_BAR5                0x24
 57  #define REG_CARDBUS_CIS_POINTER 0x28
 58  #define REG_SUBSYS_VENDOR_ID    0x2C
 59  #define REG_SUBSYS_ID           0x2E
 60  #define REG_DEV_OPROM_BASE      0x30
 61  #define REG_CAP_POINTER         0x34
 62  #define REG_INTERRUPT_LINE      0x3C
 63  #define REG_INTERRUPT_PIN       0x3D
 64  #define REG_MIN_GRANT           0x3E
 65  #define REG_MAX_LATENCY         0x3F
 66  
 67  /* Bridge config space registers. */
 68  #define REG_PRIMARY_BUS         0x18
 69  #define REG_SECONDARY_BUS       0x19
 70  #define REG_SUBORDINATE_BUS     0x1A
 71  #define REG_SECONDARY_LATENCY   0x1B
 72  #define REG_IO_BASE             0x1C
 73  #define REG_IO_LIMIT            0x1D
 74  #define REG_SECONDARY_STATUS    0x1E
 75  #define REG_MEMORY_BASE         0x20
 76  #define REG_MEMORY_LIMIT        0x22
 77  #define REG_PREFETCH_MEM_BASE   0x24
 78  #define REG_PREFETCH_MEM_LIMIT  0x26
 79  #define REG_PREFETCH_BASE_UPPER 0x28
 80  #define REG_PREFETCH_LIMIT_UPPER 0x2C
 81  #define REG_IO_BASE_UPPER       0x30
 82  #define REG_IO_LIMIT_UPPER      0x32
 83  #define REG_BRIDGE_OPROM_BASE   0x38
 84  #define REG_BRIDGE_CONTROL      0x3C
 85  
 86  #define REG_COMMAND_IO  (1 << 0)
 87  #define REG_COMMAND_MEM (1 << 1)
 88  #define REG_COMMAND_BM  (1 << 2)
 89  
 90  #define HEADER_TYPE_NORMAL        0
 91  #define HEADER_TYPE_BRIDGE        1
 92  #define HEADER_TYPE_CARDBUS       2
 93  #define HEADER_TYPE_MULTIFUNCTION 0x80
 94  
 95  #define PCI_DEV(_bus, _dev, _fn) (0x80000000 | \
 96  (uint32_t)(_bus << 16) | (uint32_t)(_dev << 11) | (uint32_t)(_fn << 8))
 97  
 98  #define PCI_ADDR(_bus, _dev, _fn, _reg) \
 99  (PCI_DEV(_bus, _dev, _fn) | (uint8_t)(_reg & ~3))
100  
101  #define PCI_BUS(_d)  ((_d >> 16) & 0xff)
102  #define PCI_SLOT(_d) ((_d >> 11) & 0x1f)
103  #define PCI_FUNC(_d) ((_d >> 8) & 0x7)
104  
105  uintptr_t pci_map_bus(pcidev_t dev);
106  
107  u8 pci_read_config8(pcidev_t dev, u16 reg);
108  u16 pci_read_config16(pcidev_t dev, u16 reg);
109  u32 pci_read_config32(pcidev_t dev, u16 reg);
110  
111  void pci_write_config8(pcidev_t dev, u16 reg, u8 val);
112  void pci_write_config16(pcidev_t dev, u16 reg, u16 val);
113  void pci_write_config32(pcidev_t dev, u16 reg, u32 val);
114  
115  int pci_find_device(u16 vid, u16 did, pcidev_t *dev);
116  u32 pci_read_resource(pcidev_t dev, int bar);
117  
118  void pci_set_bus_master(pcidev_t dev);
119  
120  #endif