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hri_supc_d51.h
   1  /**
   2   * \file
   3   *
   4   * \brief SAM SUPC
   5   *
   6   * Copyright (C) 2016 Atmel Corporation. All rights reserved.
   7   *
   8   * \asf_license_start
   9   *
  10   * \page License
  11   *
  12   * Redistribution and use in source and binary forms, with or without
  13   * modification, are permitted provided that the following conditions are met:
  14   *
  15   * 1. Redistributions of source code must retain the above copyright notice,
  16   *    this list of conditions and the following disclaimer.
  17   *
  18   * 2. Redistributions in binary form must reproduce the above copyright notice,
  19   *    this list of conditions and the following disclaimer in the documentation
  20   *    and/or other materials provided with the distribution.
  21   *
  22   * 3. The name of Atmel may not be used to endorse or promote products derived
  23   *    from this software without specific prior written permission.
  24   *
  25   * 4. This software may only be redistributed and used in connection with an
  26   *    Atmel microcontroller product.
  27   *
  28   * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
  29   * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  30   * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  31   * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
  32   * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34   * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35   * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36   * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37   * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38   * POSSIBILITY OF SUCH DAMAGE.
  39   *
  40   * \asf_license_stop
  41   */
  42  
  43  #ifdef _SAMD51_SUPC_COMPONENT_
  44  #ifndef _HRI_SUPC_D51_H_INCLUDED_
  45  #define _HRI_SUPC_D51_H_INCLUDED_
  46  
  47  #ifdef __cplusplus
  48  extern "C" {
  49  #endif
  50  
  51  #include <stdbool.h>
  52  #include <hal_atomic.h>
  53  
  54  #if defined(ENABLE_SUPC_CRITICAL_SECTIONS)
  55  #define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
  56  #define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
  57  #else
  58  #define SUPC_CRITICAL_SECTION_ENTER()
  59  #define SUPC_CRITICAL_SECTION_LEAVE()
  60  #endif
  61  
  62  typedef uint32_t hri_supc_bbps_reg_t;
  63  typedef uint32_t hri_supc_bkin_reg_t;
  64  typedef uint32_t hri_supc_bkout_reg_t;
  65  typedef uint32_t hri_supc_bod12_reg_t;
  66  typedef uint32_t hri_supc_bod33_reg_t;
  67  typedef uint32_t hri_supc_intenset_reg_t;
  68  typedef uint32_t hri_supc_intflag_reg_t;
  69  typedef uint32_t hri_supc_status_reg_t;
  70  typedef uint32_t hri_supc_vref_reg_t;
  71  typedef uint32_t hri_supc_vreg_reg_t;
  72  
  73  static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw)
  74  {
  75  	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
  76  }
  77  
  78  static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw)
  79  {
  80  	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos;
  81  }
  82  
  83  static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value)
  84  {
  85  	if (value == 0x0) {
  86  		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
  87  	} else {
  88  		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
  89  	}
  90  }
  91  
  92  static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw)
  93  {
  94  	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
  95  }
  96  
  97  static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw)
  98  {
  99  	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
 100  }
 101  
 102  static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw)
 103  {
 104  	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos;
 105  }
 106  
 107  static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value)
 108  {
 109  	if (value == 0x0) {
 110  		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
 111  	} else {
 112  		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
 113  	}
 114  }
 115  
 116  static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw)
 117  {
 118  	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
 119  }
 120  
 121  static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw)
 122  {
 123  	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
 124  }
 125  
 126  static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw)
 127  {
 128  	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos;
 129  }
 130  
 131  static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value)
 132  {
 133  	if (value == 0x0) {
 134  		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
 135  	} else {
 136  		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
 137  	}
 138  }
 139  
 140  static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw)
 141  {
 142  	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
 143  }
 144  
 145  static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw)
 146  {
 147  	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY;
 148  }
 149  
 150  static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw)
 151  {
 152  	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos;
 153  }
 154  
 155  static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value)
 156  {
 157  	if (value == 0x0) {
 158  		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY;
 159  	} else {
 160  		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY;
 161  	}
 162  }
 163  
 164  static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw)
 165  {
 166  	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY;
 167  }
 168  
 169  static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw)
 170  {
 171  	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET;
 172  }
 173  
 174  static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw)
 175  {
 176  	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos;
 177  }
 178  
 179  static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value)
 180  {
 181  	if (value == 0x0) {
 182  		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET;
 183  	} else {
 184  		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET;
 185  	}
 186  }
 187  
 188  static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw)
 189  {
 190  	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET;
 191  }
 192  
 193  static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw)
 194  {
 195  	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY;
 196  }
 197  
 198  static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw)
 199  {
 200  	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos;
 201  }
 202  
 203  static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value)
 204  {
 205  	if (value == 0x0) {
 206  		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY;
 207  	} else {
 208  		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY;
 209  	}
 210  }
 211  
 212  static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw)
 213  {
 214  	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY;
 215  }
 216  
 217  static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw)
 218  {
 219  	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
 220  }
 221  
 222  static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw)
 223  {
 224  	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos;
 225  }
 226  
 227  static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value)
 228  {
 229  	if (value == 0x0) {
 230  		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
 231  	} else {
 232  		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
 233  	}
 234  }
 235  
 236  static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw)
 237  {
 238  	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
 239  }
 240  
 241  static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw)
 242  {
 243  	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
 244  }
 245  
 246  static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw)
 247  {
 248  	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos;
 249  }
 250  
 251  static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value)
 252  {
 253  	if (value == 0x0) {
 254  		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
 255  	} else {
 256  		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
 257  	}
 258  }
 259  
 260  static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw)
 261  {
 262  	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
 263  }
 264  
 265  static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
 266  {
 267  	((Supc *)hw)->INTENSET.reg = mask;
 268  }
 269  
 270  static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
 271  {
 272  	uint32_t tmp;
 273  	tmp = ((Supc *)hw)->INTENSET.reg;
 274  	tmp &= mask;
 275  	return tmp;
 276  }
 277  
 278  static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw)
 279  {
 280  	return ((Supc *)hw)->INTENSET.reg;
 281  }
 282  
 283  static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data)
 284  {
 285  	((Supc *)hw)->INTENSET.reg = data;
 286  	((Supc *)hw)->INTENCLR.reg = ~data;
 287  }
 288  
 289  static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
 290  {
 291  	((Supc *)hw)->INTENCLR.reg = mask;
 292  }
 293  
 294  static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw)
 295  {
 296  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
 297  }
 298  
 299  static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw)
 300  {
 301  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
 302  }
 303  
 304  static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw)
 305  {
 306  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
 307  }
 308  
 309  static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw)
 310  {
 311  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
 312  }
 313  
 314  static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw)
 315  {
 316  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
 317  }
 318  
 319  static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw)
 320  {
 321  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
 322  }
 323  
 324  static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw)
 325  {
 326  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos;
 327  }
 328  
 329  static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw)
 330  {
 331  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY;
 332  }
 333  
 334  static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw)
 335  {
 336  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos;
 337  }
 338  
 339  static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw)
 340  {
 341  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
 342  }
 343  
 344  static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw)
 345  {
 346  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos;
 347  }
 348  
 349  static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw)
 350  {
 351  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY;
 352  }
 353  
 354  static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw)
 355  {
 356  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
 357  }
 358  
 359  static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw)
 360  {
 361  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
 362  }
 363  
 364  static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw)
 365  {
 366  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
 367  }
 368  
 369  static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw)
 370  {
 371  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
 372  }
 373  
 374  static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw)
 375  {
 376  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
 377  }
 378  
 379  static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw)
 380  {
 381  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
 382  }
 383  
 384  static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw)
 385  {
 386  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
 387  }
 388  
 389  static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw)
 390  {
 391  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
 392  }
 393  
 394  static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw)
 395  {
 396  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
 397  }
 398  
 399  static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw)
 400  {
 401  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
 402  }
 403  
 404  static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw)
 405  {
 406  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos;
 407  }
 408  
 409  static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw)
 410  {
 411  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY;
 412  }
 413  
 414  static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw)
 415  {
 416  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos;
 417  }
 418  
 419  static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw)
 420  {
 421  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
 422  }
 423  
 424  static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw)
 425  {
 426  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos;
 427  }
 428  
 429  static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw)
 430  {
 431  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY;
 432  }
 433  
 434  static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw)
 435  {
 436  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
 437  }
 438  
 439  static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw)
 440  {
 441  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
 442  }
 443  
 444  static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw)
 445  {
 446  	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
 447  }
 448  
 449  static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw)
 450  {
 451  	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
 452  }
 453  
 454  static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
 455  {
 456  	uint32_t tmp;
 457  	tmp = ((Supc *)hw)->INTFLAG.reg;
 458  	tmp &= mask;
 459  	return tmp;
 460  }
 461  
 462  static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw)
 463  {
 464  	return ((Supc *)hw)->INTFLAG.reg;
 465  }
 466  
 467  static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
 468  {
 469  	((Supc *)hw)->INTFLAG.reg = mask;
 470  }
 471  
 472  static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw)
 473  {
 474  	SUPC_CRITICAL_SECTION_ENTER();
 475  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE;
 476  	SUPC_CRITICAL_SECTION_LEAVE();
 477  }
 478  
 479  static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw)
 480  {
 481  	uint32_t tmp;
 482  	tmp = ((Supc *)hw)->BOD33.reg;
 483  	tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos;
 484  	return (bool)tmp;
 485  }
 486  
 487  static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value)
 488  {
 489  	uint32_t tmp;
 490  	SUPC_CRITICAL_SECTION_ENTER();
 491  	tmp = ((Supc *)hw)->BOD33.reg;
 492  	tmp &= ~SUPC_BOD33_ENABLE;
 493  	tmp |= value << SUPC_BOD33_ENABLE_Pos;
 494  	((Supc *)hw)->BOD33.reg = tmp;
 495  	SUPC_CRITICAL_SECTION_LEAVE();
 496  }
 497  
 498  static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw)
 499  {
 500  	SUPC_CRITICAL_SECTION_ENTER();
 501  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE;
 502  	SUPC_CRITICAL_SECTION_LEAVE();
 503  }
 504  
 505  static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw)
 506  {
 507  	SUPC_CRITICAL_SECTION_ENTER();
 508  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE;
 509  	SUPC_CRITICAL_SECTION_LEAVE();
 510  }
 511  
 512  static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw)
 513  {
 514  	SUPC_CRITICAL_SECTION_ENTER();
 515  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG;
 516  	SUPC_CRITICAL_SECTION_LEAVE();
 517  }
 518  
 519  static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw)
 520  {
 521  	uint32_t tmp;
 522  	tmp = ((Supc *)hw)->BOD33.reg;
 523  	tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos;
 524  	return (bool)tmp;
 525  }
 526  
 527  static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value)
 528  {
 529  	uint32_t tmp;
 530  	SUPC_CRITICAL_SECTION_ENTER();
 531  	tmp = ((Supc *)hw)->BOD33.reg;
 532  	tmp &= ~SUPC_BOD33_STDBYCFG;
 533  	tmp |= value << SUPC_BOD33_STDBYCFG_Pos;
 534  	((Supc *)hw)->BOD33.reg = tmp;
 535  	SUPC_CRITICAL_SECTION_LEAVE();
 536  }
 537  
 538  static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw)
 539  {
 540  	SUPC_CRITICAL_SECTION_ENTER();
 541  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG;
 542  	SUPC_CRITICAL_SECTION_LEAVE();
 543  }
 544  
 545  static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw)
 546  {
 547  	SUPC_CRITICAL_SECTION_ENTER();
 548  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG;
 549  	SUPC_CRITICAL_SECTION_LEAVE();
 550  }
 551  
 552  static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw)
 553  {
 554  	SUPC_CRITICAL_SECTION_ENTER();
 555  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY;
 556  	SUPC_CRITICAL_SECTION_LEAVE();
 557  }
 558  
 559  static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw)
 560  {
 561  	uint32_t tmp;
 562  	tmp = ((Supc *)hw)->BOD33.reg;
 563  	tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos;
 564  	return (bool)tmp;
 565  }
 566  
 567  static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value)
 568  {
 569  	uint32_t tmp;
 570  	SUPC_CRITICAL_SECTION_ENTER();
 571  	tmp = ((Supc *)hw)->BOD33.reg;
 572  	tmp &= ~SUPC_BOD33_RUNSTDBY;
 573  	tmp |= value << SUPC_BOD33_RUNSTDBY_Pos;
 574  	((Supc *)hw)->BOD33.reg = tmp;
 575  	SUPC_CRITICAL_SECTION_LEAVE();
 576  }
 577  
 578  static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw)
 579  {
 580  	SUPC_CRITICAL_SECTION_ENTER();
 581  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY;
 582  	SUPC_CRITICAL_SECTION_LEAVE();
 583  }
 584  
 585  static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw)
 586  {
 587  	SUPC_CRITICAL_SECTION_ENTER();
 588  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY;
 589  	SUPC_CRITICAL_SECTION_LEAVE();
 590  }
 591  
 592  static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw)
 593  {
 594  	SUPC_CRITICAL_SECTION_ENTER();
 595  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB;
 596  	SUPC_CRITICAL_SECTION_LEAVE();
 597  }
 598  
 599  static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw)
 600  {
 601  	uint32_t tmp;
 602  	tmp = ((Supc *)hw)->BOD33.reg;
 603  	tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos;
 604  	return (bool)tmp;
 605  }
 606  
 607  static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value)
 608  {
 609  	uint32_t tmp;
 610  	SUPC_CRITICAL_SECTION_ENTER();
 611  	tmp = ((Supc *)hw)->BOD33.reg;
 612  	tmp &= ~SUPC_BOD33_RUNHIB;
 613  	tmp |= value << SUPC_BOD33_RUNHIB_Pos;
 614  	((Supc *)hw)->BOD33.reg = tmp;
 615  	SUPC_CRITICAL_SECTION_LEAVE();
 616  }
 617  
 618  static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw)
 619  {
 620  	SUPC_CRITICAL_SECTION_ENTER();
 621  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB;
 622  	SUPC_CRITICAL_SECTION_LEAVE();
 623  }
 624  
 625  static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw)
 626  {
 627  	SUPC_CRITICAL_SECTION_ENTER();
 628  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB;
 629  	SUPC_CRITICAL_SECTION_LEAVE();
 630  }
 631  
 632  static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw)
 633  {
 634  	SUPC_CRITICAL_SECTION_ENTER();
 635  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP;
 636  	SUPC_CRITICAL_SECTION_LEAVE();
 637  }
 638  
 639  static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw)
 640  {
 641  	uint32_t tmp;
 642  	tmp = ((Supc *)hw)->BOD33.reg;
 643  	tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos;
 644  	return (bool)tmp;
 645  }
 646  
 647  static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value)
 648  {
 649  	uint32_t tmp;
 650  	SUPC_CRITICAL_SECTION_ENTER();
 651  	tmp = ((Supc *)hw)->BOD33.reg;
 652  	tmp &= ~SUPC_BOD33_RUNBKUP;
 653  	tmp |= value << SUPC_BOD33_RUNBKUP_Pos;
 654  	((Supc *)hw)->BOD33.reg = tmp;
 655  	SUPC_CRITICAL_SECTION_LEAVE();
 656  }
 657  
 658  static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw)
 659  {
 660  	SUPC_CRITICAL_SECTION_ENTER();
 661  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP;
 662  	SUPC_CRITICAL_SECTION_LEAVE();
 663  }
 664  
 665  static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw)
 666  {
 667  	SUPC_CRITICAL_SECTION_ENTER();
 668  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP;
 669  	SUPC_CRITICAL_SECTION_LEAVE();
 670  }
 671  
 672  static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 673  {
 674  	SUPC_CRITICAL_SECTION_ENTER();
 675  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask);
 676  	SUPC_CRITICAL_SECTION_LEAVE();
 677  }
 678  
 679  static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 680  {
 681  	uint32_t tmp;
 682  	tmp = ((Supc *)hw)->BOD33.reg;
 683  	tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos;
 684  	return tmp;
 685  }
 686  
 687  static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data)
 688  {
 689  	uint32_t tmp;
 690  	SUPC_CRITICAL_SECTION_ENTER();
 691  	tmp = ((Supc *)hw)->BOD33.reg;
 692  	tmp &= ~SUPC_BOD33_ACTION_Msk;
 693  	tmp |= SUPC_BOD33_ACTION(data);
 694  	((Supc *)hw)->BOD33.reg = tmp;
 695  	SUPC_CRITICAL_SECTION_LEAVE();
 696  }
 697  
 698  static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 699  {
 700  	SUPC_CRITICAL_SECTION_ENTER();
 701  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask);
 702  	SUPC_CRITICAL_SECTION_LEAVE();
 703  }
 704  
 705  static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 706  {
 707  	SUPC_CRITICAL_SECTION_ENTER();
 708  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask);
 709  	SUPC_CRITICAL_SECTION_LEAVE();
 710  }
 711  
 712  static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw)
 713  {
 714  	uint32_t tmp;
 715  	tmp = ((Supc *)hw)->BOD33.reg;
 716  	tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos;
 717  	return tmp;
 718  }
 719  
 720  static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 721  {
 722  	SUPC_CRITICAL_SECTION_ENTER();
 723  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask);
 724  	SUPC_CRITICAL_SECTION_LEAVE();
 725  }
 726  
 727  static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 728  {
 729  	uint32_t tmp;
 730  	tmp = ((Supc *)hw)->BOD33.reg;
 731  	tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos;
 732  	return tmp;
 733  }
 734  
 735  static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data)
 736  {
 737  	uint32_t tmp;
 738  	SUPC_CRITICAL_SECTION_ENTER();
 739  	tmp = ((Supc *)hw)->BOD33.reg;
 740  	tmp &= ~SUPC_BOD33_HYST_Msk;
 741  	tmp |= SUPC_BOD33_HYST(data);
 742  	((Supc *)hw)->BOD33.reg = tmp;
 743  	SUPC_CRITICAL_SECTION_LEAVE();
 744  }
 745  
 746  static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 747  {
 748  	SUPC_CRITICAL_SECTION_ENTER();
 749  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask);
 750  	SUPC_CRITICAL_SECTION_LEAVE();
 751  }
 752  
 753  static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 754  {
 755  	SUPC_CRITICAL_SECTION_ENTER();
 756  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask);
 757  	SUPC_CRITICAL_SECTION_LEAVE();
 758  }
 759  
 760  static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw)
 761  {
 762  	uint32_t tmp;
 763  	tmp = ((Supc *)hw)->BOD33.reg;
 764  	tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos;
 765  	return tmp;
 766  }
 767  
 768  static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 769  {
 770  	SUPC_CRITICAL_SECTION_ENTER();
 771  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask);
 772  	SUPC_CRITICAL_SECTION_LEAVE();
 773  }
 774  
 775  static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 776  {
 777  	uint32_t tmp;
 778  	tmp = ((Supc *)hw)->BOD33.reg;
 779  	tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos;
 780  	return tmp;
 781  }
 782  
 783  static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
 784  {
 785  	uint32_t tmp;
 786  	SUPC_CRITICAL_SECTION_ENTER();
 787  	tmp = ((Supc *)hw)->BOD33.reg;
 788  	tmp &= ~SUPC_BOD33_PSEL_Msk;
 789  	tmp |= SUPC_BOD33_PSEL(data);
 790  	((Supc *)hw)->BOD33.reg = tmp;
 791  	SUPC_CRITICAL_SECTION_LEAVE();
 792  }
 793  
 794  static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 795  {
 796  	SUPC_CRITICAL_SECTION_ENTER();
 797  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask);
 798  	SUPC_CRITICAL_SECTION_LEAVE();
 799  }
 800  
 801  static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 802  {
 803  	SUPC_CRITICAL_SECTION_ENTER();
 804  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask);
 805  	SUPC_CRITICAL_SECTION_LEAVE();
 806  }
 807  
 808  static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw)
 809  {
 810  	uint32_t tmp;
 811  	tmp = ((Supc *)hw)->BOD33.reg;
 812  	tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos;
 813  	return tmp;
 814  }
 815  
 816  static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 817  {
 818  	SUPC_CRITICAL_SECTION_ENTER();
 819  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask);
 820  	SUPC_CRITICAL_SECTION_LEAVE();
 821  }
 822  
 823  static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 824  {
 825  	uint32_t tmp;
 826  	tmp = ((Supc *)hw)->BOD33.reg;
 827  	tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos;
 828  	return tmp;
 829  }
 830  
 831  static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
 832  {
 833  	uint32_t tmp;
 834  	SUPC_CRITICAL_SECTION_ENTER();
 835  	tmp = ((Supc *)hw)->BOD33.reg;
 836  	tmp &= ~SUPC_BOD33_LEVEL_Msk;
 837  	tmp |= SUPC_BOD33_LEVEL(data);
 838  	((Supc *)hw)->BOD33.reg = tmp;
 839  	SUPC_CRITICAL_SECTION_LEAVE();
 840  }
 841  
 842  static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 843  {
 844  	SUPC_CRITICAL_SECTION_ENTER();
 845  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask);
 846  	SUPC_CRITICAL_SECTION_LEAVE();
 847  }
 848  
 849  static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 850  {
 851  	SUPC_CRITICAL_SECTION_ENTER();
 852  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask);
 853  	SUPC_CRITICAL_SECTION_LEAVE();
 854  }
 855  
 856  static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw)
 857  {
 858  	uint32_t tmp;
 859  	tmp = ((Supc *)hw)->BOD33.reg;
 860  	tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos;
 861  	return tmp;
 862  }
 863  
 864  static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 865  {
 866  	SUPC_CRITICAL_SECTION_ENTER();
 867  	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask);
 868  	SUPC_CRITICAL_SECTION_LEAVE();
 869  }
 870  
 871  static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 872  {
 873  	uint32_t tmp;
 874  	tmp = ((Supc *)hw)->BOD33.reg;
 875  	tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos;
 876  	return tmp;
 877  }
 878  
 879  static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
 880  {
 881  	uint32_t tmp;
 882  	SUPC_CRITICAL_SECTION_ENTER();
 883  	tmp = ((Supc *)hw)->BOD33.reg;
 884  	tmp &= ~SUPC_BOD33_VBATLEVEL_Msk;
 885  	tmp |= SUPC_BOD33_VBATLEVEL(data);
 886  	((Supc *)hw)->BOD33.reg = tmp;
 887  	SUPC_CRITICAL_SECTION_LEAVE();
 888  }
 889  
 890  static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 891  {
 892  	SUPC_CRITICAL_SECTION_ENTER();
 893  	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask);
 894  	SUPC_CRITICAL_SECTION_LEAVE();
 895  }
 896  
 897  static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
 898  {
 899  	SUPC_CRITICAL_SECTION_ENTER();
 900  	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask);
 901  	SUPC_CRITICAL_SECTION_LEAVE();
 902  }
 903  
 904  static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw)
 905  {
 906  	uint32_t tmp;
 907  	tmp = ((Supc *)hw)->BOD33.reg;
 908  	tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos;
 909  	return tmp;
 910  }
 911  
 912  static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
 913  {
 914  	SUPC_CRITICAL_SECTION_ENTER();
 915  	((Supc *)hw)->BOD33.reg |= mask;
 916  	SUPC_CRITICAL_SECTION_LEAVE();
 917  }
 918  
 919  static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
 920  {
 921  	uint32_t tmp;
 922  	tmp = ((Supc *)hw)->BOD33.reg;
 923  	tmp &= mask;
 924  	return tmp;
 925  }
 926  
 927  static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data)
 928  {
 929  	SUPC_CRITICAL_SECTION_ENTER();
 930  	((Supc *)hw)->BOD33.reg = data;
 931  	SUPC_CRITICAL_SECTION_LEAVE();
 932  }
 933  
 934  static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
 935  {
 936  	SUPC_CRITICAL_SECTION_ENTER();
 937  	((Supc *)hw)->BOD33.reg &= ~mask;
 938  	SUPC_CRITICAL_SECTION_LEAVE();
 939  }
 940  
 941  static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
 942  {
 943  	SUPC_CRITICAL_SECTION_ENTER();
 944  	((Supc *)hw)->BOD33.reg ^= mask;
 945  	SUPC_CRITICAL_SECTION_LEAVE();
 946  }
 947  
 948  static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw)
 949  {
 950  	return ((Supc *)hw)->BOD33.reg;
 951  }
 952  
 953  static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw)
 954  {
 955  	SUPC_CRITICAL_SECTION_ENTER();
 956  	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE;
 957  	SUPC_CRITICAL_SECTION_LEAVE();
 958  }
 959  
 960  static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw)
 961  {
 962  	uint32_t tmp;
 963  	tmp = ((Supc *)hw)->BOD12.reg;
 964  	tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos;
 965  	return (bool)tmp;
 966  }
 967  
 968  static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value)
 969  {
 970  	uint32_t tmp;
 971  	SUPC_CRITICAL_SECTION_ENTER();
 972  	tmp = ((Supc *)hw)->BOD12.reg;
 973  	tmp &= ~SUPC_BOD12_ENABLE;
 974  	tmp |= value << SUPC_BOD12_ENABLE_Pos;
 975  	((Supc *)hw)->BOD12.reg = tmp;
 976  	SUPC_CRITICAL_SECTION_LEAVE();
 977  }
 978  
 979  static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw)
 980  {
 981  	SUPC_CRITICAL_SECTION_ENTER();
 982  	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE;
 983  	SUPC_CRITICAL_SECTION_LEAVE();
 984  }
 985  
 986  static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw)
 987  {
 988  	SUPC_CRITICAL_SECTION_ENTER();
 989  	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE;
 990  	SUPC_CRITICAL_SECTION_LEAVE();
 991  }
 992  
 993  static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw)
 994  {
 995  	SUPC_CRITICAL_SECTION_ENTER();
 996  	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST;
 997  	SUPC_CRITICAL_SECTION_LEAVE();
 998  }
 999  
1000  static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw)
1001  {
1002  	uint32_t tmp;
1003  	tmp = ((Supc *)hw)->BOD12.reg;
1004  	tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos;
1005  	return (bool)tmp;
1006  }
1007  
1008  static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value)
1009  {
1010  	uint32_t tmp;
1011  	SUPC_CRITICAL_SECTION_ENTER();
1012  	tmp = ((Supc *)hw)->BOD12.reg;
1013  	tmp &= ~SUPC_BOD12_HYST;
1014  	tmp |= value << SUPC_BOD12_HYST_Pos;
1015  	((Supc *)hw)->BOD12.reg = tmp;
1016  	SUPC_CRITICAL_SECTION_LEAVE();
1017  }
1018  
1019  static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw)
1020  {
1021  	SUPC_CRITICAL_SECTION_ENTER();
1022  	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST;
1023  	SUPC_CRITICAL_SECTION_LEAVE();
1024  }
1025  
1026  static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw)
1027  {
1028  	SUPC_CRITICAL_SECTION_ENTER();
1029  	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST;
1030  	SUPC_CRITICAL_SECTION_LEAVE();
1031  }
1032  
1033  static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw)
1034  {
1035  	SUPC_CRITICAL_SECTION_ENTER();
1036  	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG;
1037  	SUPC_CRITICAL_SECTION_LEAVE();
1038  }
1039  
1040  static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw)
1041  {
1042  	uint32_t tmp;
1043  	tmp = ((Supc *)hw)->BOD12.reg;
1044  	tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos;
1045  	return (bool)tmp;
1046  }
1047  
1048  static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value)
1049  {
1050  	uint32_t tmp;
1051  	SUPC_CRITICAL_SECTION_ENTER();
1052  	tmp = ((Supc *)hw)->BOD12.reg;
1053  	tmp &= ~SUPC_BOD12_STDBYCFG;
1054  	tmp |= value << SUPC_BOD12_STDBYCFG_Pos;
1055  	((Supc *)hw)->BOD12.reg = tmp;
1056  	SUPC_CRITICAL_SECTION_LEAVE();
1057  }
1058  
1059  static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw)
1060  {
1061  	SUPC_CRITICAL_SECTION_ENTER();
1062  	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG;
1063  	SUPC_CRITICAL_SECTION_LEAVE();
1064  }
1065  
1066  static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw)
1067  {
1068  	SUPC_CRITICAL_SECTION_ENTER();
1069  	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG;
1070  	SUPC_CRITICAL_SECTION_LEAVE();
1071  }
1072  
1073  static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw)
1074  {
1075  	SUPC_CRITICAL_SECTION_ENTER();
1076  	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY;
1077  	SUPC_CRITICAL_SECTION_LEAVE();
1078  }
1079  
1080  static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw)
1081  {
1082  	uint32_t tmp;
1083  	tmp = ((Supc *)hw)->BOD12.reg;
1084  	tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos;
1085  	return (bool)tmp;
1086  }
1087  
1088  static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value)
1089  {
1090  	uint32_t tmp;
1091  	SUPC_CRITICAL_SECTION_ENTER();
1092  	tmp = ((Supc *)hw)->BOD12.reg;
1093  	tmp &= ~SUPC_BOD12_RUNSTDBY;
1094  	tmp |= value << SUPC_BOD12_RUNSTDBY_Pos;
1095  	((Supc *)hw)->BOD12.reg = tmp;
1096  	SUPC_CRITICAL_SECTION_LEAVE();
1097  }
1098  
1099  static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw)
1100  {
1101  	SUPC_CRITICAL_SECTION_ENTER();
1102  	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY;
1103  	SUPC_CRITICAL_SECTION_LEAVE();
1104  }
1105  
1106  static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw)
1107  {
1108  	SUPC_CRITICAL_SECTION_ENTER();
1109  	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY;
1110  	SUPC_CRITICAL_SECTION_LEAVE();
1111  }
1112  
1113  static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw)
1114  {
1115  	SUPC_CRITICAL_SECTION_ENTER();
1116  	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG;
1117  	SUPC_CRITICAL_SECTION_LEAVE();
1118  }
1119  
1120  static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw)
1121  {
1122  	uint32_t tmp;
1123  	tmp = ((Supc *)hw)->BOD12.reg;
1124  	tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos;
1125  	return (bool)tmp;
1126  }
1127  
1128  static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value)
1129  {
1130  	uint32_t tmp;
1131  	SUPC_CRITICAL_SECTION_ENTER();
1132  	tmp = ((Supc *)hw)->BOD12.reg;
1133  	tmp &= ~SUPC_BOD12_ACTCFG;
1134  	tmp |= value << SUPC_BOD12_ACTCFG_Pos;
1135  	((Supc *)hw)->BOD12.reg = tmp;
1136  	SUPC_CRITICAL_SECTION_LEAVE();
1137  }
1138  
1139  static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw)
1140  {
1141  	SUPC_CRITICAL_SECTION_ENTER();
1142  	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG;
1143  	SUPC_CRITICAL_SECTION_LEAVE();
1144  }
1145  
1146  static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw)
1147  {
1148  	SUPC_CRITICAL_SECTION_ENTER();
1149  	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG;
1150  	SUPC_CRITICAL_SECTION_LEAVE();
1151  }
1152  
1153  static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1154  {
1155  	SUPC_CRITICAL_SECTION_ENTER();
1156  	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask);
1157  	SUPC_CRITICAL_SECTION_LEAVE();
1158  }
1159  
1160  static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1161  {
1162  	uint32_t tmp;
1163  	tmp = ((Supc *)hw)->BOD12.reg;
1164  	tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos;
1165  	return tmp;
1166  }
1167  
1168  static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data)
1169  {
1170  	uint32_t tmp;
1171  	SUPC_CRITICAL_SECTION_ENTER();
1172  	tmp = ((Supc *)hw)->BOD12.reg;
1173  	tmp &= ~SUPC_BOD12_ACTION_Msk;
1174  	tmp |= SUPC_BOD12_ACTION(data);
1175  	((Supc *)hw)->BOD12.reg = tmp;
1176  	SUPC_CRITICAL_SECTION_LEAVE();
1177  }
1178  
1179  static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1180  {
1181  	SUPC_CRITICAL_SECTION_ENTER();
1182  	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask);
1183  	SUPC_CRITICAL_SECTION_LEAVE();
1184  }
1185  
1186  static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1187  {
1188  	SUPC_CRITICAL_SECTION_ENTER();
1189  	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask);
1190  	SUPC_CRITICAL_SECTION_LEAVE();
1191  }
1192  
1193  static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw)
1194  {
1195  	uint32_t tmp;
1196  	tmp = ((Supc *)hw)->BOD12.reg;
1197  	tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos;
1198  	return tmp;
1199  }
1200  
1201  static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1202  {
1203  	SUPC_CRITICAL_SECTION_ENTER();
1204  	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask);
1205  	SUPC_CRITICAL_SECTION_LEAVE();
1206  }
1207  
1208  static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1209  {
1210  	uint32_t tmp;
1211  	tmp = ((Supc *)hw)->BOD12.reg;
1212  	tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos;
1213  	return tmp;
1214  }
1215  
1216  static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data)
1217  {
1218  	uint32_t tmp;
1219  	SUPC_CRITICAL_SECTION_ENTER();
1220  	tmp = ((Supc *)hw)->BOD12.reg;
1221  	tmp &= ~SUPC_BOD12_PSEL_Msk;
1222  	tmp |= SUPC_BOD12_PSEL(data);
1223  	((Supc *)hw)->BOD12.reg = tmp;
1224  	SUPC_CRITICAL_SECTION_LEAVE();
1225  }
1226  
1227  static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1228  {
1229  	SUPC_CRITICAL_SECTION_ENTER();
1230  	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask);
1231  	SUPC_CRITICAL_SECTION_LEAVE();
1232  }
1233  
1234  static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1235  {
1236  	SUPC_CRITICAL_SECTION_ENTER();
1237  	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask);
1238  	SUPC_CRITICAL_SECTION_LEAVE();
1239  }
1240  
1241  static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw)
1242  {
1243  	uint32_t tmp;
1244  	tmp = ((Supc *)hw)->BOD12.reg;
1245  	tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos;
1246  	return tmp;
1247  }
1248  
1249  static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1250  {
1251  	SUPC_CRITICAL_SECTION_ENTER();
1252  	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask);
1253  	SUPC_CRITICAL_SECTION_LEAVE();
1254  }
1255  
1256  static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1257  {
1258  	uint32_t tmp;
1259  	tmp = ((Supc *)hw)->BOD12.reg;
1260  	tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos;
1261  	return tmp;
1262  }
1263  
1264  static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data)
1265  {
1266  	uint32_t tmp;
1267  	SUPC_CRITICAL_SECTION_ENTER();
1268  	tmp = ((Supc *)hw)->BOD12.reg;
1269  	tmp &= ~SUPC_BOD12_LEVEL_Msk;
1270  	tmp |= SUPC_BOD12_LEVEL(data);
1271  	((Supc *)hw)->BOD12.reg = tmp;
1272  	SUPC_CRITICAL_SECTION_LEAVE();
1273  }
1274  
1275  static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1276  {
1277  	SUPC_CRITICAL_SECTION_ENTER();
1278  	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask);
1279  	SUPC_CRITICAL_SECTION_LEAVE();
1280  }
1281  
1282  static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
1283  {
1284  	SUPC_CRITICAL_SECTION_ENTER();
1285  	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask);
1286  	SUPC_CRITICAL_SECTION_LEAVE();
1287  }
1288  
1289  static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw)
1290  {
1291  	uint32_t tmp;
1292  	tmp = ((Supc *)hw)->BOD12.reg;
1293  	tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos;
1294  	return tmp;
1295  }
1296  
1297  static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
1298  {
1299  	SUPC_CRITICAL_SECTION_ENTER();
1300  	((Supc *)hw)->BOD12.reg |= mask;
1301  	SUPC_CRITICAL_SECTION_LEAVE();
1302  }
1303  
1304  static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
1305  {
1306  	uint32_t tmp;
1307  	tmp = ((Supc *)hw)->BOD12.reg;
1308  	tmp &= mask;
1309  	return tmp;
1310  }
1311  
1312  static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data)
1313  {
1314  	SUPC_CRITICAL_SECTION_ENTER();
1315  	((Supc *)hw)->BOD12.reg = data;
1316  	SUPC_CRITICAL_SECTION_LEAVE();
1317  }
1318  
1319  static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
1320  {
1321  	SUPC_CRITICAL_SECTION_ENTER();
1322  	((Supc *)hw)->BOD12.reg &= ~mask;
1323  	SUPC_CRITICAL_SECTION_LEAVE();
1324  }
1325  
1326  static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
1327  {
1328  	SUPC_CRITICAL_SECTION_ENTER();
1329  	((Supc *)hw)->BOD12.reg ^= mask;
1330  	SUPC_CRITICAL_SECTION_LEAVE();
1331  }
1332  
1333  static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw)
1334  {
1335  	return ((Supc *)hw)->BOD12.reg;
1336  }
1337  
1338  static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw)
1339  {
1340  	SUPC_CRITICAL_SECTION_ENTER();
1341  	((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE;
1342  	SUPC_CRITICAL_SECTION_LEAVE();
1343  }
1344  
1345  static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw)
1346  {
1347  	uint32_t tmp;
1348  	tmp = ((Supc *)hw)->VREG.reg;
1349  	tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos;
1350  	return (bool)tmp;
1351  }
1352  
1353  static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value)
1354  {
1355  	uint32_t tmp;
1356  	SUPC_CRITICAL_SECTION_ENTER();
1357  	tmp = ((Supc *)hw)->VREG.reg;
1358  	tmp &= ~SUPC_VREG_ENABLE;
1359  	tmp |= value << SUPC_VREG_ENABLE_Pos;
1360  	((Supc *)hw)->VREG.reg = tmp;
1361  	SUPC_CRITICAL_SECTION_LEAVE();
1362  }
1363  
1364  static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw)
1365  {
1366  	SUPC_CRITICAL_SECTION_ENTER();
1367  	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE;
1368  	SUPC_CRITICAL_SECTION_LEAVE();
1369  }
1370  
1371  static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw)
1372  {
1373  	SUPC_CRITICAL_SECTION_ENTER();
1374  	((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE;
1375  	SUPC_CRITICAL_SECTION_LEAVE();
1376  }
1377  
1378  static inline void hri_supc_set_VREG_SEL_bit(const void *const hw)
1379  {
1380  	SUPC_CRITICAL_SECTION_ENTER();
1381  	((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL;
1382  	SUPC_CRITICAL_SECTION_LEAVE();
1383  }
1384  
1385  static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw)
1386  {
1387  	uint32_t tmp;
1388  	tmp = ((Supc *)hw)->VREG.reg;
1389  	tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos;
1390  	return (bool)tmp;
1391  }
1392  
1393  static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value)
1394  {
1395  	uint32_t tmp;
1396  	SUPC_CRITICAL_SECTION_ENTER();
1397  	tmp = ((Supc *)hw)->VREG.reg;
1398  	tmp &= ~SUPC_VREG_SEL;
1399  	tmp |= value << SUPC_VREG_SEL_Pos;
1400  	((Supc *)hw)->VREG.reg = tmp;
1401  	SUPC_CRITICAL_SECTION_LEAVE();
1402  }
1403  
1404  static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw)
1405  {
1406  	SUPC_CRITICAL_SECTION_ENTER();
1407  	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL;
1408  	SUPC_CRITICAL_SECTION_LEAVE();
1409  }
1410  
1411  static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw)
1412  {
1413  	SUPC_CRITICAL_SECTION_ENTER();
1414  	((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL;
1415  	SUPC_CRITICAL_SECTION_LEAVE();
1416  }
1417  
1418  static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw)
1419  {
1420  	SUPC_CRITICAL_SECTION_ENTER();
1421  	((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP;
1422  	SUPC_CRITICAL_SECTION_LEAVE();
1423  }
1424  
1425  static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw)
1426  {
1427  	uint32_t tmp;
1428  	tmp = ((Supc *)hw)->VREG.reg;
1429  	tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos;
1430  	return (bool)tmp;
1431  }
1432  
1433  static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value)
1434  {
1435  	uint32_t tmp;
1436  	SUPC_CRITICAL_SECTION_ENTER();
1437  	tmp = ((Supc *)hw)->VREG.reg;
1438  	tmp &= ~SUPC_VREG_RUNBKUP;
1439  	tmp |= value << SUPC_VREG_RUNBKUP_Pos;
1440  	((Supc *)hw)->VREG.reg = tmp;
1441  	SUPC_CRITICAL_SECTION_LEAVE();
1442  }
1443  
1444  static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw)
1445  {
1446  	SUPC_CRITICAL_SECTION_ENTER();
1447  	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP;
1448  	SUPC_CRITICAL_SECTION_LEAVE();
1449  }
1450  
1451  static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw)
1452  {
1453  	SUPC_CRITICAL_SECTION_ENTER();
1454  	((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP;
1455  	SUPC_CRITICAL_SECTION_LEAVE();
1456  }
1457  
1458  static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw)
1459  {
1460  	SUPC_CRITICAL_SECTION_ENTER();
1461  	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN;
1462  	SUPC_CRITICAL_SECTION_LEAVE();
1463  }
1464  
1465  static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw)
1466  {
1467  	uint32_t tmp;
1468  	tmp = ((Supc *)hw)->VREG.reg;
1469  	tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos;
1470  	return (bool)tmp;
1471  }
1472  
1473  static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value)
1474  {
1475  	uint32_t tmp;
1476  	SUPC_CRITICAL_SECTION_ENTER();
1477  	tmp = ((Supc *)hw)->VREG.reg;
1478  	tmp &= ~SUPC_VREG_VSEN;
1479  	tmp |= value << SUPC_VREG_VSEN_Pos;
1480  	((Supc *)hw)->VREG.reg = tmp;
1481  	SUPC_CRITICAL_SECTION_LEAVE();
1482  }
1483  
1484  static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw)
1485  {
1486  	SUPC_CRITICAL_SECTION_ENTER();
1487  	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN;
1488  	SUPC_CRITICAL_SECTION_LEAVE();
1489  }
1490  
1491  static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw)
1492  {
1493  	SUPC_CRITICAL_SECTION_ENTER();
1494  	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN;
1495  	SUPC_CRITICAL_SECTION_LEAVE();
1496  }
1497  
1498  static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
1499  {
1500  	SUPC_CRITICAL_SECTION_ENTER();
1501  	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask);
1502  	SUPC_CRITICAL_SECTION_LEAVE();
1503  }
1504  
1505  static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
1506  {
1507  	uint32_t tmp;
1508  	tmp = ((Supc *)hw)->VREG.reg;
1509  	tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos;
1510  	return tmp;
1511  }
1512  
1513  static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data)
1514  {
1515  	uint32_t tmp;
1516  	SUPC_CRITICAL_SECTION_ENTER();
1517  	tmp = ((Supc *)hw)->VREG.reg;
1518  	tmp &= ~SUPC_VREG_VSPER_Msk;
1519  	tmp |= SUPC_VREG_VSPER(data);
1520  	((Supc *)hw)->VREG.reg = tmp;
1521  	SUPC_CRITICAL_SECTION_LEAVE();
1522  }
1523  
1524  static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
1525  {
1526  	SUPC_CRITICAL_SECTION_ENTER();
1527  	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask);
1528  	SUPC_CRITICAL_SECTION_LEAVE();
1529  }
1530  
1531  static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
1532  {
1533  	SUPC_CRITICAL_SECTION_ENTER();
1534  	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask);
1535  	SUPC_CRITICAL_SECTION_LEAVE();
1536  }
1537  
1538  static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw)
1539  {
1540  	uint32_t tmp;
1541  	tmp = ((Supc *)hw)->VREG.reg;
1542  	tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos;
1543  	return tmp;
1544  }
1545  
1546  static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
1547  {
1548  	SUPC_CRITICAL_SECTION_ENTER();
1549  	((Supc *)hw)->VREG.reg |= mask;
1550  	SUPC_CRITICAL_SECTION_LEAVE();
1551  }
1552  
1553  static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
1554  {
1555  	uint32_t tmp;
1556  	tmp = ((Supc *)hw)->VREG.reg;
1557  	tmp &= mask;
1558  	return tmp;
1559  }
1560  
1561  static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data)
1562  {
1563  	SUPC_CRITICAL_SECTION_ENTER();
1564  	((Supc *)hw)->VREG.reg = data;
1565  	SUPC_CRITICAL_SECTION_LEAVE();
1566  }
1567  
1568  static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
1569  {
1570  	SUPC_CRITICAL_SECTION_ENTER();
1571  	((Supc *)hw)->VREG.reg &= ~mask;
1572  	SUPC_CRITICAL_SECTION_LEAVE();
1573  }
1574  
1575  static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
1576  {
1577  	SUPC_CRITICAL_SECTION_ENTER();
1578  	((Supc *)hw)->VREG.reg ^= mask;
1579  	SUPC_CRITICAL_SECTION_LEAVE();
1580  }
1581  
1582  static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw)
1583  {
1584  	return ((Supc *)hw)->VREG.reg;
1585  }
1586  
1587  static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw)
1588  {
1589  	SUPC_CRITICAL_SECTION_ENTER();
1590  	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN;
1591  	SUPC_CRITICAL_SECTION_LEAVE();
1592  }
1593  
1594  static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw)
1595  {
1596  	uint32_t tmp;
1597  	tmp = ((Supc *)hw)->VREF.reg;
1598  	tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos;
1599  	return (bool)tmp;
1600  }
1601  
1602  static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value)
1603  {
1604  	uint32_t tmp;
1605  	SUPC_CRITICAL_SECTION_ENTER();
1606  	tmp = ((Supc *)hw)->VREF.reg;
1607  	tmp &= ~SUPC_VREF_TSEN;
1608  	tmp |= value << SUPC_VREF_TSEN_Pos;
1609  	((Supc *)hw)->VREF.reg = tmp;
1610  	SUPC_CRITICAL_SECTION_LEAVE();
1611  }
1612  
1613  static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw)
1614  {
1615  	SUPC_CRITICAL_SECTION_ENTER();
1616  	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN;
1617  	SUPC_CRITICAL_SECTION_LEAVE();
1618  }
1619  
1620  static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw)
1621  {
1622  	SUPC_CRITICAL_SECTION_ENTER();
1623  	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN;
1624  	SUPC_CRITICAL_SECTION_LEAVE();
1625  }
1626  
1627  static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw)
1628  {
1629  	SUPC_CRITICAL_SECTION_ENTER();
1630  	((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE;
1631  	SUPC_CRITICAL_SECTION_LEAVE();
1632  }
1633  
1634  static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw)
1635  {
1636  	uint32_t tmp;
1637  	tmp = ((Supc *)hw)->VREF.reg;
1638  	tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos;
1639  	return (bool)tmp;
1640  }
1641  
1642  static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value)
1643  {
1644  	uint32_t tmp;
1645  	SUPC_CRITICAL_SECTION_ENTER();
1646  	tmp = ((Supc *)hw)->VREF.reg;
1647  	tmp &= ~SUPC_VREF_VREFOE;
1648  	tmp |= value << SUPC_VREF_VREFOE_Pos;
1649  	((Supc *)hw)->VREF.reg = tmp;
1650  	SUPC_CRITICAL_SECTION_LEAVE();
1651  }
1652  
1653  static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw)
1654  {
1655  	SUPC_CRITICAL_SECTION_ENTER();
1656  	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE;
1657  	SUPC_CRITICAL_SECTION_LEAVE();
1658  }
1659  
1660  static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw)
1661  {
1662  	SUPC_CRITICAL_SECTION_ENTER();
1663  	((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE;
1664  	SUPC_CRITICAL_SECTION_LEAVE();
1665  }
1666  
1667  static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw)
1668  {
1669  	SUPC_CRITICAL_SECTION_ENTER();
1670  	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL;
1671  	SUPC_CRITICAL_SECTION_LEAVE();
1672  }
1673  
1674  static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw)
1675  {
1676  	uint32_t tmp;
1677  	tmp = ((Supc *)hw)->VREF.reg;
1678  	tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos;
1679  	return (bool)tmp;
1680  }
1681  
1682  static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value)
1683  {
1684  	uint32_t tmp;
1685  	SUPC_CRITICAL_SECTION_ENTER();
1686  	tmp = ((Supc *)hw)->VREF.reg;
1687  	tmp &= ~SUPC_VREF_TSSEL;
1688  	tmp |= value << SUPC_VREF_TSSEL_Pos;
1689  	((Supc *)hw)->VREF.reg = tmp;
1690  	SUPC_CRITICAL_SECTION_LEAVE();
1691  }
1692  
1693  static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw)
1694  {
1695  	SUPC_CRITICAL_SECTION_ENTER();
1696  	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL;
1697  	SUPC_CRITICAL_SECTION_LEAVE();
1698  }
1699  
1700  static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw)
1701  {
1702  	SUPC_CRITICAL_SECTION_ENTER();
1703  	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL;
1704  	SUPC_CRITICAL_SECTION_LEAVE();
1705  }
1706  
1707  static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw)
1708  {
1709  	SUPC_CRITICAL_SECTION_ENTER();
1710  	((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY;
1711  	SUPC_CRITICAL_SECTION_LEAVE();
1712  }
1713  
1714  static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw)
1715  {
1716  	uint32_t tmp;
1717  	tmp = ((Supc *)hw)->VREF.reg;
1718  	tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos;
1719  	return (bool)tmp;
1720  }
1721  
1722  static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value)
1723  {
1724  	uint32_t tmp;
1725  	SUPC_CRITICAL_SECTION_ENTER();
1726  	tmp = ((Supc *)hw)->VREF.reg;
1727  	tmp &= ~SUPC_VREF_RUNSTDBY;
1728  	tmp |= value << SUPC_VREF_RUNSTDBY_Pos;
1729  	((Supc *)hw)->VREF.reg = tmp;
1730  	SUPC_CRITICAL_SECTION_LEAVE();
1731  }
1732  
1733  static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw)
1734  {
1735  	SUPC_CRITICAL_SECTION_ENTER();
1736  	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY;
1737  	SUPC_CRITICAL_SECTION_LEAVE();
1738  }
1739  
1740  static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw)
1741  {
1742  	SUPC_CRITICAL_SECTION_ENTER();
1743  	((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY;
1744  	SUPC_CRITICAL_SECTION_LEAVE();
1745  }
1746  
1747  static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw)
1748  {
1749  	SUPC_CRITICAL_SECTION_ENTER();
1750  	((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND;
1751  	SUPC_CRITICAL_SECTION_LEAVE();
1752  }
1753  
1754  static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw)
1755  {
1756  	uint32_t tmp;
1757  	tmp = ((Supc *)hw)->VREF.reg;
1758  	tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos;
1759  	return (bool)tmp;
1760  }
1761  
1762  static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value)
1763  {
1764  	uint32_t tmp;
1765  	SUPC_CRITICAL_SECTION_ENTER();
1766  	tmp = ((Supc *)hw)->VREF.reg;
1767  	tmp &= ~SUPC_VREF_ONDEMAND;
1768  	tmp |= value << SUPC_VREF_ONDEMAND_Pos;
1769  	((Supc *)hw)->VREF.reg = tmp;
1770  	SUPC_CRITICAL_SECTION_LEAVE();
1771  }
1772  
1773  static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw)
1774  {
1775  	SUPC_CRITICAL_SECTION_ENTER();
1776  	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND;
1777  	SUPC_CRITICAL_SECTION_LEAVE();
1778  }
1779  
1780  static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw)
1781  {
1782  	SUPC_CRITICAL_SECTION_ENTER();
1783  	((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND;
1784  	SUPC_CRITICAL_SECTION_LEAVE();
1785  }
1786  
1787  static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
1788  {
1789  	SUPC_CRITICAL_SECTION_ENTER();
1790  	((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask);
1791  	SUPC_CRITICAL_SECTION_LEAVE();
1792  }
1793  
1794  static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
1795  {
1796  	uint32_t tmp;
1797  	tmp = ((Supc *)hw)->VREF.reg;
1798  	tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos;
1799  	return tmp;
1800  }
1801  
1802  static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data)
1803  {
1804  	uint32_t tmp;
1805  	SUPC_CRITICAL_SECTION_ENTER();
1806  	tmp = ((Supc *)hw)->VREF.reg;
1807  	tmp &= ~SUPC_VREF_SEL_Msk;
1808  	tmp |= SUPC_VREF_SEL(data);
1809  	((Supc *)hw)->VREF.reg = tmp;
1810  	SUPC_CRITICAL_SECTION_LEAVE();
1811  }
1812  
1813  static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
1814  {
1815  	SUPC_CRITICAL_SECTION_ENTER();
1816  	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask);
1817  	SUPC_CRITICAL_SECTION_LEAVE();
1818  }
1819  
1820  static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
1821  {
1822  	SUPC_CRITICAL_SECTION_ENTER();
1823  	((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask);
1824  	SUPC_CRITICAL_SECTION_LEAVE();
1825  }
1826  
1827  static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw)
1828  {
1829  	uint32_t tmp;
1830  	tmp = ((Supc *)hw)->VREF.reg;
1831  	tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos;
1832  	return tmp;
1833  }
1834  
1835  static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
1836  {
1837  	SUPC_CRITICAL_SECTION_ENTER();
1838  	((Supc *)hw)->VREF.reg |= mask;
1839  	SUPC_CRITICAL_SECTION_LEAVE();
1840  }
1841  
1842  static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
1843  {
1844  	uint32_t tmp;
1845  	tmp = ((Supc *)hw)->VREF.reg;
1846  	tmp &= mask;
1847  	return tmp;
1848  }
1849  
1850  static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data)
1851  {
1852  	SUPC_CRITICAL_SECTION_ENTER();
1853  	((Supc *)hw)->VREF.reg = data;
1854  	SUPC_CRITICAL_SECTION_LEAVE();
1855  }
1856  
1857  static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
1858  {
1859  	SUPC_CRITICAL_SECTION_ENTER();
1860  	((Supc *)hw)->VREF.reg &= ~mask;
1861  	SUPC_CRITICAL_SECTION_LEAVE();
1862  }
1863  
1864  static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
1865  {
1866  	SUPC_CRITICAL_SECTION_ENTER();
1867  	((Supc *)hw)->VREF.reg ^= mask;
1868  	SUPC_CRITICAL_SECTION_LEAVE();
1869  }
1870  
1871  static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw)
1872  {
1873  	return ((Supc *)hw)->VREF.reg;
1874  }
1875  
1876  static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw)
1877  {
1878  	SUPC_CRITICAL_SECTION_ENTER();
1879  	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF;
1880  	SUPC_CRITICAL_SECTION_LEAVE();
1881  }
1882  
1883  static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw)
1884  {
1885  	uint32_t tmp;
1886  	tmp = ((Supc *)hw)->BBPS.reg;
1887  	tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos;
1888  	return (bool)tmp;
1889  }
1890  
1891  static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value)
1892  {
1893  	uint32_t tmp;
1894  	SUPC_CRITICAL_SECTION_ENTER();
1895  	tmp = ((Supc *)hw)->BBPS.reg;
1896  	tmp &= ~SUPC_BBPS_CONF;
1897  	tmp |= value << SUPC_BBPS_CONF_Pos;
1898  	((Supc *)hw)->BBPS.reg = tmp;
1899  	SUPC_CRITICAL_SECTION_LEAVE();
1900  }
1901  
1902  static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw)
1903  {
1904  	SUPC_CRITICAL_SECTION_ENTER();
1905  	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF;
1906  	SUPC_CRITICAL_SECTION_LEAVE();
1907  }
1908  
1909  static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw)
1910  {
1911  	SUPC_CRITICAL_SECTION_ENTER();
1912  	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF;
1913  	SUPC_CRITICAL_SECTION_LEAVE();
1914  }
1915  
1916  static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw)
1917  {
1918  	SUPC_CRITICAL_SECTION_ENTER();
1919  	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN;
1920  	SUPC_CRITICAL_SECTION_LEAVE();
1921  }
1922  
1923  static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw)
1924  {
1925  	uint32_t tmp;
1926  	tmp = ((Supc *)hw)->BBPS.reg;
1927  	tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos;
1928  	return (bool)tmp;
1929  }
1930  
1931  static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value)
1932  {
1933  	uint32_t tmp;
1934  	SUPC_CRITICAL_SECTION_ENTER();
1935  	tmp = ((Supc *)hw)->BBPS.reg;
1936  	tmp &= ~SUPC_BBPS_WAKEEN;
1937  	tmp |= value << SUPC_BBPS_WAKEEN_Pos;
1938  	((Supc *)hw)->BBPS.reg = tmp;
1939  	SUPC_CRITICAL_SECTION_LEAVE();
1940  }
1941  
1942  static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw)
1943  {
1944  	SUPC_CRITICAL_SECTION_ENTER();
1945  	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN;
1946  	SUPC_CRITICAL_SECTION_LEAVE();
1947  }
1948  
1949  static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw)
1950  {
1951  	SUPC_CRITICAL_SECTION_ENTER();
1952  	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN;
1953  	SUPC_CRITICAL_SECTION_LEAVE();
1954  }
1955  
1956  static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
1957  {
1958  	SUPC_CRITICAL_SECTION_ENTER();
1959  	((Supc *)hw)->BBPS.reg |= mask;
1960  	SUPC_CRITICAL_SECTION_LEAVE();
1961  }
1962  
1963  static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
1964  {
1965  	uint32_t tmp;
1966  	tmp = ((Supc *)hw)->BBPS.reg;
1967  	tmp &= mask;
1968  	return tmp;
1969  }
1970  
1971  static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data)
1972  {
1973  	SUPC_CRITICAL_SECTION_ENTER();
1974  	((Supc *)hw)->BBPS.reg = data;
1975  	SUPC_CRITICAL_SECTION_LEAVE();
1976  }
1977  
1978  static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
1979  {
1980  	SUPC_CRITICAL_SECTION_ENTER();
1981  	((Supc *)hw)->BBPS.reg &= ~mask;
1982  	SUPC_CRITICAL_SECTION_LEAVE();
1983  }
1984  
1985  static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
1986  {
1987  	SUPC_CRITICAL_SECTION_ENTER();
1988  	((Supc *)hw)->BBPS.reg ^= mask;
1989  	SUPC_CRITICAL_SECTION_LEAVE();
1990  }
1991  
1992  static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw)
1993  {
1994  	return ((Supc *)hw)->BBPS.reg;
1995  }
1996  
1997  static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
1998  {
1999  	SUPC_CRITICAL_SECTION_ENTER();
2000  	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask);
2001  	SUPC_CRITICAL_SECTION_LEAVE();
2002  }
2003  
2004  static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2005  {
2006  	uint32_t tmp;
2007  	tmp = ((Supc *)hw)->BKOUT.reg;
2008  	tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos;
2009  	return tmp;
2010  }
2011  
2012  static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data)
2013  {
2014  	uint32_t tmp;
2015  	SUPC_CRITICAL_SECTION_ENTER();
2016  	tmp = ((Supc *)hw)->BKOUT.reg;
2017  	tmp &= ~SUPC_BKOUT_EN_Msk;
2018  	tmp |= SUPC_BKOUT_EN(data);
2019  	((Supc *)hw)->BKOUT.reg = tmp;
2020  	SUPC_CRITICAL_SECTION_LEAVE();
2021  }
2022  
2023  static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2024  {
2025  	SUPC_CRITICAL_SECTION_ENTER();
2026  	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask);
2027  	SUPC_CRITICAL_SECTION_LEAVE();
2028  }
2029  
2030  static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2031  {
2032  	SUPC_CRITICAL_SECTION_ENTER();
2033  	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask);
2034  	SUPC_CRITICAL_SECTION_LEAVE();
2035  }
2036  
2037  static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw)
2038  {
2039  	uint32_t tmp;
2040  	tmp = ((Supc *)hw)->BKOUT.reg;
2041  	tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos;
2042  	return tmp;
2043  }
2044  
2045  static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2046  {
2047  	SUPC_CRITICAL_SECTION_ENTER();
2048  	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask);
2049  	SUPC_CRITICAL_SECTION_LEAVE();
2050  }
2051  
2052  static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2053  {
2054  	uint32_t tmp;
2055  	tmp = ((Supc *)hw)->BKOUT.reg;
2056  	tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos;
2057  	return tmp;
2058  }
2059  
2060  static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data)
2061  {
2062  	uint32_t tmp;
2063  	SUPC_CRITICAL_SECTION_ENTER();
2064  	tmp = ((Supc *)hw)->BKOUT.reg;
2065  	tmp &= ~SUPC_BKOUT_CLR_Msk;
2066  	tmp |= SUPC_BKOUT_CLR(data);
2067  	((Supc *)hw)->BKOUT.reg = tmp;
2068  	SUPC_CRITICAL_SECTION_LEAVE();
2069  }
2070  
2071  static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2072  {
2073  	SUPC_CRITICAL_SECTION_ENTER();
2074  	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask);
2075  	SUPC_CRITICAL_SECTION_LEAVE();
2076  }
2077  
2078  static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2079  {
2080  	SUPC_CRITICAL_SECTION_ENTER();
2081  	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask);
2082  	SUPC_CRITICAL_SECTION_LEAVE();
2083  }
2084  
2085  static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw)
2086  {
2087  	uint32_t tmp;
2088  	tmp = ((Supc *)hw)->BKOUT.reg;
2089  	tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos;
2090  	return tmp;
2091  }
2092  
2093  static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2094  {
2095  	SUPC_CRITICAL_SECTION_ENTER();
2096  	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask);
2097  	SUPC_CRITICAL_SECTION_LEAVE();
2098  }
2099  
2100  static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2101  {
2102  	uint32_t tmp;
2103  	tmp = ((Supc *)hw)->BKOUT.reg;
2104  	tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos;
2105  	return tmp;
2106  }
2107  
2108  static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data)
2109  {
2110  	uint32_t tmp;
2111  	SUPC_CRITICAL_SECTION_ENTER();
2112  	tmp = ((Supc *)hw)->BKOUT.reg;
2113  	tmp &= ~SUPC_BKOUT_SET_Msk;
2114  	tmp |= SUPC_BKOUT_SET(data);
2115  	((Supc *)hw)->BKOUT.reg = tmp;
2116  	SUPC_CRITICAL_SECTION_LEAVE();
2117  }
2118  
2119  static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2120  {
2121  	SUPC_CRITICAL_SECTION_ENTER();
2122  	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask);
2123  	SUPC_CRITICAL_SECTION_LEAVE();
2124  }
2125  
2126  static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2127  {
2128  	SUPC_CRITICAL_SECTION_ENTER();
2129  	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask);
2130  	SUPC_CRITICAL_SECTION_LEAVE();
2131  }
2132  
2133  static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw)
2134  {
2135  	uint32_t tmp;
2136  	tmp = ((Supc *)hw)->BKOUT.reg;
2137  	tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos;
2138  	return tmp;
2139  }
2140  
2141  static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2142  {
2143  	SUPC_CRITICAL_SECTION_ENTER();
2144  	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask);
2145  	SUPC_CRITICAL_SECTION_LEAVE();
2146  }
2147  
2148  static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2149  {
2150  	uint32_t tmp;
2151  	tmp = ((Supc *)hw)->BKOUT.reg;
2152  	tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos;
2153  	return tmp;
2154  }
2155  
2156  static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data)
2157  {
2158  	uint32_t tmp;
2159  	SUPC_CRITICAL_SECTION_ENTER();
2160  	tmp = ((Supc *)hw)->BKOUT.reg;
2161  	tmp &= ~SUPC_BKOUT_RTCTGL_Msk;
2162  	tmp |= SUPC_BKOUT_RTCTGL(data);
2163  	((Supc *)hw)->BKOUT.reg = tmp;
2164  	SUPC_CRITICAL_SECTION_LEAVE();
2165  }
2166  
2167  static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2168  {
2169  	SUPC_CRITICAL_SECTION_ENTER();
2170  	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask);
2171  	SUPC_CRITICAL_SECTION_LEAVE();
2172  }
2173  
2174  static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
2175  {
2176  	SUPC_CRITICAL_SECTION_ENTER();
2177  	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask);
2178  	SUPC_CRITICAL_SECTION_LEAVE();
2179  }
2180  
2181  static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw)
2182  {
2183  	uint32_t tmp;
2184  	tmp = ((Supc *)hw)->BKOUT.reg;
2185  	tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos;
2186  	return tmp;
2187  }
2188  
2189  static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
2190  {
2191  	SUPC_CRITICAL_SECTION_ENTER();
2192  	((Supc *)hw)->BKOUT.reg |= mask;
2193  	SUPC_CRITICAL_SECTION_LEAVE();
2194  }
2195  
2196  static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
2197  {
2198  	uint32_t tmp;
2199  	tmp = ((Supc *)hw)->BKOUT.reg;
2200  	tmp &= mask;
2201  	return tmp;
2202  }
2203  
2204  static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data)
2205  {
2206  	SUPC_CRITICAL_SECTION_ENTER();
2207  	((Supc *)hw)->BKOUT.reg = data;
2208  	SUPC_CRITICAL_SECTION_LEAVE();
2209  }
2210  
2211  static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
2212  {
2213  	SUPC_CRITICAL_SECTION_ENTER();
2214  	((Supc *)hw)->BKOUT.reg &= ~mask;
2215  	SUPC_CRITICAL_SECTION_LEAVE();
2216  }
2217  
2218  static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
2219  {
2220  	SUPC_CRITICAL_SECTION_ENTER();
2221  	((Supc *)hw)->BKOUT.reg ^= mask;
2222  	SUPC_CRITICAL_SECTION_LEAVE();
2223  }
2224  
2225  static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw)
2226  {
2227  	return ((Supc *)hw)->BKOUT.reg;
2228  }
2229  
2230  static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw)
2231  {
2232  	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos;
2233  }
2234  
2235  static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw)
2236  {
2237  	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos;
2238  }
2239  
2240  static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw)
2241  {
2242  	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos;
2243  }
2244  
2245  static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw)
2246  {
2247  	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos;
2248  }
2249  
2250  static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw)
2251  {
2252  	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos;
2253  }
2254  
2255  static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw)
2256  {
2257  	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos;
2258  }
2259  
2260  static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw)
2261  {
2262  	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos;
2263  }
2264  
2265  static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw)
2266  {
2267  	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos;
2268  }
2269  
2270  static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask)
2271  {
2272  	uint32_t tmp;
2273  	tmp = ((Supc *)hw)->STATUS.reg;
2274  	tmp &= mask;
2275  	return tmp;
2276  }
2277  
2278  static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw)
2279  {
2280  	return ((Supc *)hw)->STATUS.reg;
2281  }
2282  
2283  static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask)
2284  {
2285  	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos;
2286  }
2287  
2288  static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw)
2289  {
2290  	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos;
2291  }
2292  
2293  static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask)
2294  {
2295  	uint32_t tmp;
2296  	tmp = ((Supc *)hw)->BKIN.reg;
2297  	tmp &= mask;
2298  	return tmp;
2299  }
2300  
2301  static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw)
2302  {
2303  	return ((Supc *)hw)->BKIN.reg;
2304  }
2305  
2306  #ifdef __cplusplus
2307  }
2308  #endif
2309  
2310  #endif /* _HRI_SUPC_D51_H_INCLUDED */
2311  #endif /* _SAMD51_SUPC_COMPONENT_ */