1  #!/usr/bin/env python3
  2  
  3  import os
  4  import sys
  5  import argparse
  6  
  7  from amaranth import *
  8  
  9  
 10  if __name__ == "__main__":
 11      parent = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
 12      sys.path.insert(0, parent)
 13  
 14  from coreblocks.params.genparams import GenParams
 15  from coreblocks.core import Core
 16  from coreblocks.socks.socks import Socks
 17  from transactron import TransactronContextComponent
 18  from transactron.utils import DependencyManager, DependencyContext
 19  from transactron.utils.gen import generate_verilog
 20  
 21  from coreblocks.params.configurations import *
 22  
 23  str_to_coreconfig: dict[str, CoreConfiguration] = {
 24      "basic": basic_core_config,
 25      "tiny": tiny_core_config,
 26      "small_linux": small_linux_config,
 27      "full": full_core_config,
 28  }
 29  
 30  
 31  def gen_verilog(
 32      core_config: CoreConfiguration, output_path: str, *, wrap_socks: bool = False, enable_vivado_hacks: bool = False
 33  ):
 34      with DependencyContext(DependencyManager()):
 35          gp = GenParams(core_config)
 36          core = Core(gen_params=gp)
 37          if wrap_socks:
 38              core = Socks(core, core_gen_params=gp)
 39  
 40          top = TransactronContextComponent(core, dependency_manager=DependencyContext.get())
 41  
 42          # use known working yosys version shipped with amaranth by default
 43          if "AMARANTH_USE_YOSYS" not in os.environ:
 44              os.environ["AMARANTH_USE_YOSYS"] = "builtin"
 45  
 46          enable_hacks = []
 47          if enable_vivado_hacks:
 48              enable_hacks.append("fixup_vivado_transparent_memories")
 49  
 50          verilog_text, gen_info = generate_verilog(top, enable_hacks=enable_hacks)
 51  
 52          gen_info.encode(f"{output_path}.json")
 53          with open(output_path, "w") as f:
 54              f.write(verilog_text)
 55  
 56  
 57  def main():
 58      parser = argparse.ArgumentParser()
 59      parser.add_argument(
 60          "-v",
 61          "--verbose",
 62          action="store_true",
 63          help="Enables verbose output. Default: %(default)s",
 64      )
 65  
 66      parser.add_argument(
 67          "-c",
 68          "--config",
 69          action="store",
 70          default="basic",
 71          help="Select core configuration. "
 72          + f"Available configurations: {', '.join(list(str_to_coreconfig.keys()))}. Default: %(default)s",
 73      )
 74  
 75      parser.add_argument(
 76          "--strip-debug",
 77          action="store_true",
 78          help="Remove debugging signals. Default: %(default)s",
 79      )
 80  
 81      parser.add_argument(
 82          "--with-socks",
 83          action="store_true",
 84          help="Wrap Coreblocks in CoreSoCks providing additional memory-mapped or CSR peripherals",
 85      )
 86  
 87      parser.add_argument(
 88          "--enable-vivado-hacks",
 89          action="store_true",
 90          help="Enable elaboration and generation hacks for Vivado toolchain",
 91      )
 92  
 93      parser.add_argument("--reset-pc", action="store", default="0x0", help="Set core reset address")
 94  
 95      parser.add_argument(
 96          "-o", "--output", action="store", default="core.v", help="Output file path. Default: %(default)s"
 97      )
 98  
 99      args = parser.parse_args()
100  
101      os.environ["AMARANTH_verbose"] = "true" if args.verbose else "false"
102  
103      if args.config not in str_to_coreconfig:
104          raise KeyError(f"Unknown config '{args.config}'")
105  
106      config = str_to_coreconfig[args.config]
107      if args.strip_debug:
108          config = config.replace(debug_signals=False)
109  
110      assert args.reset_pc[:2] == "0x", "Expected hex number as --reset-pc"
111      config = config.replace(start_pc=int(args.reset_pc[2:], base=16))
112  
113      gen_verilog(config, args.output, wrap_socks=args.with_socks, enable_vivado_hacks=args.enable_vivado_hacks)
114  
115  
116  if __name__ == "__main__":
117      main()